CN106228730B - A kind of fire alarm control system - Google Patents

A kind of fire alarm control system Download PDF

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Publication number
CN106228730B
CN106228730B CN201610454669.7A CN201610454669A CN106228730B CN 106228730 B CN106228730 B CN 106228730B CN 201610454669 A CN201610454669 A CN 201610454669A CN 106228730 B CN106228730 B CN 106228730B
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cycle
time
voltage
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CN106228730A (en
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张金木
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Guangxi Anxin Technology Co., Ltd
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Fuzhou Alignment Mdt Infotech Ltd
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    • GPHYSICS
    • G08SIGNALLING
    • G08BSIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B17/00Fire alarms; Alarms responsive to explosion
    • GPHYSICS
    • G08SIGNALLING
    • G08BSIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B25/00Alarm systems in which the location of the alarm condition is signalled to a central station, e.g. fire or police telegraphic systems
    • G08B25/01Alarm systems in which the location of the alarm condition is signalled to a central station, e.g. fire or police telegraphic systems characterised by the transmission medium
    • G08B25/06Alarm systems in which the location of the alarm condition is signalled to a central station, e.g. fire or police telegraphic systems characterised by the transmission medium using power transmission lines

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  • Emergency Management (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Alarm Systems (AREA)

Abstract

The present invention relates to a kind of fire alarm control systems, include fire detector, zone controller, Centralized Controller and Fire extinguisher, fire alarm detected by fire detector, warning message is transferred to zone controller, each zone controller is alarmed to Centralized Controller, Centralized Controller opens Fire extinguisher starting fire-extinguishing apparatus and sends alarm, is alarmed by GSM nets with short message mode to administrator and relevant department.

Description

A kind of fire alarm control system
(1) technical field:
The present invention relates to a kind of fire alarm control system, comprising fire detector, zone controller, Centralized Controller and Fire extinguisher, the fire alarm detected by fire detector transfer warning message, each zone controller to zone controller It alarms to Centralized Controller, Centralized Controller or unlatching Fire extinguisher start fire-extinguishing apparatus and send alarm, pass through GSM nets It is alarmed with short message mode to administrator and relevant department.
(2) background technology:
The control system of power supply is provided by power network, each electronic equipment or intermodule are communicated by special circuit, The timing time of each electronic equipment or electronic module is corrected, reaches synchronous operation purpose.Due to being made using special circuit communication Wiring complicates and increases cost, if timing time is not corrected by line traffic, due to traditional timing error, runs number After hour, accumulation timing error can make system control action inconsistent, may cause system crash, and at some, often change is set Meter, its products application of the big occasion of wiring installation amount are restricted.
(3) content of the invention:
The present invention relates to a kind of fire alarm control system, comprising fire detector, zone controller, Centralized Controller and Fire extinguisher.At the top of room and multiple fire detectors are installed in the region of easily generation fire, are selected according to ambient enviroment feature Different fire detectors such as temperature-sensitive, photosensitive, sense cigarette and its compound etc. are selected, makes system that there is extensive adaptability, each fire is visited It surveys device and unique number is all set, set by code switch.After start, zone controller first registers each fire detector, It was found that failure is alarmed.Fire alarm detected by fire detector, through signal processing into the letter with different fire alarm grades Wherein microcontroller processing number is sent, microcontroller judges and is classified according to features such as the duration of alarm signal, intensity, paces of change Afterwards, warning message is transferred to zone controller through conventional communication lines, each zone controller is by fire alarm position, fire alarm grade through electricity Half wave communication of the line of force is alarmed to Centralized Controller, and half wave communication or unlatching Fire extinguisher of the Centralized Controller through power line rise It moves fire-extinguishing apparatus and sends alarm, and pass through GSM nets and alarmed with short message mode to administrator and relevant department.Zone controller Multiple fire detectors are controlled, and the power supply of fire detector is provided.The output of Fire extinguisher is through in driving circuit of putting out a fire Phototube Coupling, bidirectional triode thyristor control or contact relay circuit control, fire-extinguishing apparatus power supply is connected on the alternating current outside system.Respectively Fire extinguisher, each zone controller and Centralized Controller are respectively provided with cycle discriminator circuit in device, for generation system Synchronization time keeps system to keep strokes, while communications electronics switch, a switch drive mould are respectively set in its telecommunication circuit Block.Above device is connected on same electric power cable and sets master switch, installs isolating diode after master switch, at system In the half wave communication half-wave power supply state through power line.
Each zone controller, Fire extinguisher and Centralized Controller, therebetween communication are to be controlled by synchronization time to keep dynamic Make unanimously, the switch drive module of communications electronics switch is to be followed by the CLK ends of d type flip flop through electric resistance partial pressure from electric power cable, and D is touched The external interrupt mouth (INT0 or INT1) of the Q termination microcontrollers of device is sent out, fracture is arranged to level triggers in this.The D ends of d type flip flop Ground connection, S ends connect with the I/O mouths of microcontroller, and original state S puts 1 in end.When the positive square-wave signal at CLK ends arrives, rise Interruption is generated along d type flip flop is made to set to 0 middle fracture low level, first setting to 0 S ends in interrupt service routine makes d type flip flop put 1 i.e. Q It holds as 1 and the Central Shanxi Plain is broken, then communicates, communications electronics switch is connected to microcontroller corresponding port according to used communication mode, and Signal condition is carried out, S ends, which put 1, before sign off makes out the communication of the lower cycle of interrupt latency, so realizes half-wave in cycles Communication.
SMS R-T unit in system is installed, using GSM network, is communicated with receiving and dispatching short message mode, at present The SMS messaging service of GSM is still that a kind of highest SMS of short message service GSM of domestic popularity rate possesses data transmission work(in itself Can, the transmission of a message, which just constitutes, once to communicate, and the transmission of message is the SMS service center by being in outside GSM (SMSC) relayed, it does not have to dialing and can establish connection by the SMS service SMS of GSM, and user adds the information to be sent out Stay of two nights data sending is then forwarded to the final stay of two nights to short message service center after short message service center completes storage.So When the no start of GSM terminals, information will not lose.
The present invention utilizes the positive half cycle ascent stage of power network cycle, takes three to screen point and realize and the identification of cycle signal is sentenced It is fixed, the cycle time is recycled to establish synchronization time, the synchronous operation of each zone controller and Centralized Controller in realization system.
Cycle discriminator circuit structure diagram such as Fig. 2 institutes of each Fire extinguisher, each zone controller and Centralized Controller Show, formed by three using the voltage comparator of hysteresis loop comparator, comprising filter circuit, voltage in each voltage comparator The reference voltage of comparator is provided by regulator circuit.System sets clock timer and synchrotimer.If it detects adjacent Two cycle signals be true, then take out the clock timer timing time between this two adjacent cycle signal zero passages, It is sequentially stored in cycle time memory cell, which can store 100 cycle times, be often stored in when being filled with One cycle time first removes the cycle time being stored at first, and calculates the average value Tz of the cycle time of deposit simultaneously It preserves, differentiates cycle signal to be identified using Tz values, to reduce the influence of power network frequency fluctuation, while using three examination points Reduce erroneous judgement possibility.
Three comparators are respectively used to three examination points, that is, screen point 0, screen point 1, screen point 2, as shown in Figure 1.In week At the cycle zero passage of ripple positive half cycle ascent stage, that is, screen point 0 and voltage zero-crossing comparator is set, due to power network cycle negative half period quilt Rectifier diode is isolated, in order to improve accuracy of detection, in the signal input part series diode isolation again of voltage zero-crossing comparator Negative half period, reference voltage is increased to 10mv to 100mv from zero, and depending on the offset voltage of comparator, which can profit It is obtained with diode drop through electric resistance partial pressure.Remaining two comparator is separately positioned on cycle positive half cycle ascent stage, crest voltage 35% to 50% place examination point 1 and 50% to 70% place examination point 2.
Cycle signal determining:After setting time opens interruption, clock timer resets and starts timing microcontroller, works as cycle During voltage zero-cross, the output voltage overturning for the voltage Zero-cross comparator Qi ﹙ V0 ﹚ for screening point 0 is arranged on, is generated in its voltage trailing edge It interrupts, records its zero crossing break period Th0 and the Central Shanxi Plain is broken;Hereafter, electricity pressure comparator ﹙ V1 ﹚ at point 1 are screened in microcontroller scanning Output voltage, when all wave voltages are reached to the threshold voltage of ﹙ V1 ﹚, output voltage is overturn from high to low, when scanning records its overturning Between Th1;Similary scanning record screens electricity pressure comparator ﹙ V2 ﹚ output voltage flip-flop transition Th2 at point 2, by Th0 and voltage zero-cross The output voltage flip-flop transition setting value Ts0 of Bi compare Qi ﹙ V0 ﹚ makes comparisons;The output voltage of Th1 and electricity pressure comparator ﹙ V1 ﹚ are overturn Time setting value Ts1 and Th2 makes comparisons respectively with the output voltage flip-flop transition setting value Ts2 of electricity pressure comparator ﹙ V2 ﹚, such as For fruit in the range of allowable error, then the discriminator signal detected is true, is otherwise false.When above-mentioned judgement discriminator signal is true, Calculate the clock timer meter between cycle signal zero passage when this cycle signal zero passage and an adjacent preceding discriminator signal are true When time Tzu, it is made comparisons with the average value Tz of cycle time, the cycle if no more than setting cycle time error Tzv Signal is true, at this moment preserves Tzu and 20ms is taken to be added with synchrotimer timing time, the value deposit synchrotimer that will add up In.
When clock timer starts timing with cycle voltage zero-cross, then timing to 16ms opens the break period between 18.5ms Open interruption during setting value Tk, clock timer timing to 25ms to Central Shanxi Plain during pass break period setting value Tn between 27ms is broken.
After system boot, clock timer starts timing, when detecting first cycle voltage zero-cross, is arranged on examination The output voltage overturning of the voltage Zero-cross comparator Qi ﹙ V0 ﹚ of point 0, interrupts so as to generate, takes out the time T0 of cycle voltage over zero It preserves, clock timer is reset and starts timing, at this moment cycle time voltage crosses zero Th0 is 0, while microcontroller presses above-mentioned side Method scans and judges discriminator signal.What it is due to detection is first cycle, and clock timer is started in cycle voltage zero-cross Timing, the value of Th0, Th1 and Th2 must add the difference that cycle time 20ms subtracts out break period setting value Tk, if Three discriminator signals are true, and i.e. opening the break period for the first time takes Tk next time.Otherwise for fictitious time, clock timer time palpus at this time In addition T0, continues to detect.
When detecting first and second adjacent cycle voltage zero-cross, due to not preserving the cycle time of detection, Therefore the clock timer timing time twice between cycle signal zero passage is made comparisons with cycle time 20ms, judges cycle signal When being true, then take out clock timer cumulative time T1=T0+Tk when opening interruption and be stored in synchrotimer as initial time In, open interruption after clock timer reset, otherwise judge cycle signal be fictitious time, at this time the clock timer time must add T1, Continue to detect first cycle again as stated above.After it is very to detect first cycle signal, recover above-described week Ripple signal determining.
If as shown in Figure 1, detecting that cycle signal is false, the break period is opened next time and opens the break period at this Afterwards, open interruptions during average value Tz through the cycle time that is delayed, and open interrupt after be delayed Tns when the Central Shanxi Plain break, when setting the Central Shanxi Plain to break Between be when cycle signal screen point 0 when do not generating interruption, at this moment must be in the setting time point more than Ts0 allowable error scopes When starting to scan and scanning examination point 1 and screen point 2, voltage comparator output voltage does not generate overturning, all breaks in the Central Shanxi Plain Scanning is broken and is stopped in the time Tns Central Shanxi Plain, and Tns is:
Tns=Tn-Tk
If it is true to detect cycle signal, next cycle opens break period Tks and is:
Tks=Tk+Th0
I.e. from opening for the first time after the break period takes Tk, clock timer is that timing opens interruption to Tks, and weight after resetting New to start timing, timing is broken to Central Shanxi Plain during Tns, so that the synchrotimer time is corrected be subject to cycle time voltage crosses zero.
It repeats the above process.If the upper cycle signal detected is true, when this cycle judges, discriminator signal is Vacation or the cycle time detected are more than setting cycle time error Tzv or clock meter compared with the average value Tz of cycle time When device timing to close break period setting value Tns when, voltage Zero-cross comparator device ﹙ V0 ﹚ output voltages are not overturn, in not generating Disconnected, then when clock timer timing is to Tns, the Central Shanxi Plain is broken, and at this moment remembers that not counting cycle N is 1 and stores, when opening interruption next time Between be to open the break period in last time to open interruption after Tz, hereafter every time judge the cycle signal true and false, if false or this detection Though discriminator signal is true but last time is false, then N is taken, will be restored after N+1 in memory, clock timer is not reset after interruption is opened Continue timing, at this moment, next cycle of setting opens the break period and temporarily uses out break period interim setting value Tkz instead:
Tkz=(N+1) × Tz
Meanwhile next cycle closes break period temporary use instead and closes break period interim setting value Tnz:
Tnz=Tkz+Tns
When clock timer to after Tkz, the time that point is screened in scanning can be obtained by simple computation.If it at this moment examines It is true to measure cycle signal, then takes out in memory N and preserve, and by N zero setting in memory, makes clock timer clocking value Ts For:(Ts-Tkz) at this moment → Ts takes the value of (N+1) × 20ms to be added in synchrotimer, and recover using setting value Tks with Tns, recovered clock timer are reset after interruption is opened.
The system synchronization time be synchrotimer time, along with currently just timing clock timer time.
When judging to screen the point signal true and false, Th0, Th1, Th2 are by being set with voltage comparator output voltage flip-flop transition Definite value Ts0, Ts1, Ts2 make comparisons see it is whether overproof, come judge screen point a signal true and false, can select:Th0, Th1, Th2 are The cycle discriminator signal is true when true or Th0 is true, while when one of Th1, Th2 are true or when Th1, Th2 are true, it should Cycle discriminator signal is true, depending on to judging the different requirements of the cycle signal true and false.
If system fault, when N is more than a setting value between 25 to 70, due to each Fire extinguisher in system, Each zone controller and Centralized Controller, Tz values and the N values of detection may be different, and at this moment, power network frequency accumulated error can The synchrotimer time can be caused to be corrected when can not be by detecting true cycle signal, when detecting that cycle signal is true When, it is directly added on using clocking value of the clock timer at Tkz in synchrotimer, to reduce the asynchronous time of system, N is much smaller than 25 in the case of power network normal operation.
The cycle time error Tzv of permission and the flip-flop transition setting value of voltage comparator output voltage, by test assessment Its average value is taken to obtain.
(4) illustrate:
Fig. 1 is that cycle screens data relationship schematic diagram;
Fig. 2 is cycle discriminator circuit structure diagram;
Fig. 3 is a kind of circuit structure block diagram of fire alarm control system.
(5) specific embodiment:
Fig. 3 is that a kind of circuit structure block diagram of fire alarm control system includes:10 ﹚ of centralized Control Qi ﹙, communications electronics Open pass 11 ﹚ of ﹙, switch drives 12 ﹚ of dynamic model block ﹙, SMS receives 13 ﹚, SIM card ﹙ of transmitting apparatus ﹙, 14 ﹚, 15 ﹚ of device ﹙, cycle are surveyed in fiery calamity spy It screens 16 ﹚ of electricity road ﹙, 17 ﹚ of area domain controller ﹙, fiery 18 ﹚ of controller ﹙ that go out, 19 ﹚ of fire extinguishing Qu Dong electricity road ﹙, the fire that goes out and sets 20 ﹚ of standby ﹙.Wherein 11 ﹚ of communications electronics Kai Guan ﹙, 12 ﹚ of switch Qu dynamic model Kuai ﹙, cycle are screened Dan Pian Ji ﹙ U0 ﹚ in 16 ﹚ and Fig. 2 of electricity Lu ﹙ and are respectively included In 17 ﹚ of area domain controller ﹙, 10 ﹚ of fiery 18 ﹚ of controller ﹙ and centralized Control device ﹙ that goes out.Wherein 11 ﹚ of communications electronics Kai Guan ﹙ use double To silicon-controlled as switch.
Fig. 2 is the structure diagram that cycle screens 16 ﹚ of electricity Lu ﹙, by:Shu enters electricity Lu ﹙ S0 ﹚, voltage zero-cross Jian and surveys Mo Kuai ﹙ V0 ﹚, electricity pressure comparator ﹙ V1 ﹚ and electricity pressure comparator ﹙ V2 ﹚ are formed.Single piece machine ﹙ U0 ﹚ refer to 17 ﹚ of area domain controller ﹙, fire extinguishing control Microcontroller in 18 ﹚ of Qi ﹙ and 10 ﹚ of centralized Control Qi ﹙.Shu enters electricity Lu ﹙ S0 ﹚ for mains AC voltage to be passed through resistance and two The partial pressure of pole pipe is converted to the suitably stable input voltage of voltage comparator.Dan Pian Ji ﹙ U0 ﹚ use 89C55WD, voltage mistake Zero inspection surveys mould block ﹙ V0 ﹚, electricity pressure comparator ﹙ V1 ﹚, electricity pressure comparator ﹙ V2 ﹚ using dedicated voltage comparator LM339, base Quasi- voltage is come the threshold voltage of burning voltage comparator using the regulator circuit of voltage-stabiliser tube.
When mains AC voltage cycle signal zero passage, voltage zero-cross Jian surveys the output voltage saltus step of Mo Kuai ﹙ V0 ﹚, single Pian Ji ﹙ U0 ﹚ generate interruption, record the break period, while Dan Pian Ji ﹙ U0 ﹚ are additionally operable to scanning voltage Bi compare Qi ﹙ V1 ﹚ and voltage ratio The output voltage of compare Qi ﹙ V2 ﹚, bound-time is recorded when output voltage saltus step, for judging power network cycle signal so as to producing Raw synchronization time.
Single chip computer89C51 realizes serial communication, the microcontroller by I2C buses and main controller in SMS R-T unit 89C51 is connected also by serial line interface integrated circuit MAX232 with gsm module TC35i carries out data exchange, gsm module chip TC35i is RS232 data ports, supports AT Command Set, wherein contain the control to SMS, single chip computer89C51 is by GSM moulds Block sends a series of AT instructions, completes the initialization to gsm module and receiving short message.The transmitting-receiving of SMS uses TEXT patterns, TEXT patterns are a kind of tactic patterns based on ASCII character.

Claims (2)

1. a kind of fire alarm control system, it is characterized in that, fire detector is transferred through conventional communication lines to zone controller Warning message, half wave communication of each zone controller through power line are alarmed to Centralized Controller, and Centralized Controller is through power line Half wave communication opens Fire extinguisher and starts fire-extinguishing apparatus, and passes through GSM nets with short message mode to administrator and relevant department Alarm;Each Fire extinguisher, each zone controller and Centralized Controller are respectively provided with cycle discriminator circuit in device, for producing The synchronization time of raw system keeps system to keep strokes, while respectively sets a communications electronics switch in its telecommunication circuit, opens Drive module is closed, above device is connected on same electric power cable and sets master switch, two poles of installation isolation after master switch Pipe, system are in the half wave communication half-wave power supply state through power line;
Each zone controller, Fire extinguisher and Centralized Controller, therebetween communication are to be controlled by synchronization time to keep action one It causes, the switch drive module of communications electronics switch is to be followed by d type flip flop through diode partial pressure again from electric power cable through resistance decompression CLK ends, d type flip flop Q termination microcontroller external interrupt mouth, when CLK ends positive square-wave signal arrive when, rising edge makes D type flip flop is set to 0, which generates interruption, then communicates;
Cycle discriminator circuit is formed by three using the voltage comparator of hysteresis, and the reference voltage of voltage comparator is by voltage stabilizing electricity Road provides, and cycle discriminator circuit is the positive half cycle ascent stage using power network cycle, takes three to screen point and realizes to cycle signal Identification decision, the cycle time is recycled to establish synchronization time, system sets clock timer and synchrotimer, if detection It is true to two adjacent cycle signals, then takes out the clock timer timing between this two adjacent cycle signal zero passages Time, that is, cycle time is sequentially stored in cycle time memory cell, when a cycle is often stored in when being filled with 100 cycle time Between, the cycle time being stored at first is first removed, and calculate the average value Tz of the cycle time of deposit and preserve, utilize Tz Value differentiates cycle signal to be identified;
Three comparators are respectively used to three examination points, that is, screen point 0, screen point 1, screen point 2, in the cycle positive half cycle ascent stage Cycle zero passage at, that is, screen point 0 set a voltage zero-crossing comparator, concatenate two again in the signal input part of voltage zero-crossing comparator Pole pipe isolates negative half period, and reference voltage is 10mv to 100mv, and depending on the offset voltage of comparator, which can profit It is obtained with diode drop through electric resistance partial pressure, remaining two comparator is separately positioned on cycle positive half cycle ascent stage, crest voltage 35% to 50% place examination point 1 and 50% to 70% place examination point 2;
Cycle signal determining process:After setting time opens interruption, clock timer resets and starts timing microcontroller, works as cycle During voltage zero-cross, the output voltage overturning for the voltage zero-crossing comparator for screening point 0 is arranged on, in the generation of its voltage trailing edge It is disconnected, it records its zero crossing break period Th0 and the Central Shanxi Plain is broken;Hereafter, microcontroller scanning screens 1 first voltage Bi compare Qi ﹙ V1 ﹚'s of point Output voltage, when all wave voltages reach first voltage than threshold voltage compared with device ﹙ V1 ﹚, output voltage is overturn from high to low, is swept Trace record its flip-flop transition Th1;Similary scanning record screens second voltage Bi compare Qi ﹙ V2 ﹚ output voltage flip-flop transitions at point 2 Th2 is otherwise vacation if the discriminator signal that the flip-flop transition Th1 and Th2 in the range of allowable error, is detected is true, When above-mentioned judgement discriminator signal is true, calculates cycle when this cycle signal zero passage and an adjacent preceding discriminator signal are true and believe Clock timer timing time Tzu between number zero passage, it is made comparisons with the average value Tz of cycle time, if no more than setting Then cycle signal is true to cycle time error Tzv, at this moment preserves Tzu and 20ms is taken to be added with synchrotimer timing time, will In the value deposit synchrotimer of addition;
When clock timer starts timing with cycle voltage zero-cross, then timing to 16ms opens break period setting between 18.5ms Open interruption during value Tk, clock timer timing to 25ms to Central Shanxi Plain during pass break period setting value Tn between 27ms is broken;
When detecting first cycle voltage zero-cross, the output voltage overturning for the voltage zero-crossing comparator for screening point 0 is arranged on, It is interrupted so as to generate, the time T0 for taking out cycle voltage over zero is preserved, and clock timer is reset and starts timing, at this moment all Wave voltage zero-crossing timing Th0 is 0, and microcontroller scans and judges discriminator signal, and the value of Th0, Th1 and Th2 must add cycle Time 20ms subtracts out the difference of break period setting value Tk, if three discriminator signals are true, detects all wave voltages next time The break period of opening of zero crossing takes Tk, is otherwise fictitious time, at this time the clock timer time must add T0, continue to detect;
When it is true to detect first and second adjacent cycle voltage zero-cross judgement cycle signal, then when interruption is opened in taking-up Clock timer cumulative time T1=T0+Tk as initial time be stored in synchrotimer in, open interruption after clock timer Reset, otherwise judge cycle signal be fictitious time, at this time the clock timer time must add T1, again detect first cycle, when Detection first cycle signal be very after, recover above-described cycle signal determining;
If it is false to detect cycle signal, open the break period next time after this opens the break period, through be delayed cycle when Between average value Tz when open interruption, and open interrupt after be delayed Tns when the Central Shanxi Plain break, it is when cycle signal is discriminated to set and close the break period Not Wei fictitious time, break and stop to scan closing the break period Tns Central Shanxi Plain, Tns is:
Tns=Tn-Tk
If it is true to detect cycle signal, next cycle opens break period Tks and is:
Tks=Tk+Th0
I.e. from opening for the first time after the break period takes Tk, clock timer is that timing opens interruption to Tks, and is opened again after resetting Beginning timing, timing are broken to Central Shanxi Plain during Tns, repeat above-mentioned cycle signal determining process, if the upper cycle letter detected Number it is true, when this cycle judges, discriminator signal is false, then when clock timer timing is to Tns, the Central Shanxi Plain is broken, and at this moment remembers cycle N is 1 and stores that it is to open the break period in last time to open interruption after Tz to open the break period next time, hereafter judges cycle every time The signal true and false, though if false or this detection discriminator signal be false true last time, then take out stored N, and will be returned after N+1 It is stored in the memory of storage N, clock timer does not reset continuation timing after interruption is opened, and at this moment, next cycle of setting is opened Break period temporarily uses out break period interim setting value Tkz instead:
Tkz=(N+1) × Tz
Meanwhile next cycle closes break period temporary use instead and closes break period interim setting value Tnz:
Tnz=Tkz+Tns
When clock timer to after Tkz, if at this moment detecting that cycle signal is true, take out N in memory and preserve, and By N zero setting in memory, the clock timer clocking value Ts is set to be:Ts-Tkz is first calculated again with results modification Ts values are calculated, at this moment The value of (N+1) × 20ms is taken to be added in synchrotimer, and is recovered using setting value Tks and Tns, recovered clock timer is being opened It is reset after interruption;
The system synchronization time be synchrotimer time, along with currently just timing clock timer time;
And it selects:Cycle discriminator signal is true when Th0, Th1, Th2 are true or Th0 is true, while one of Th1, Th2 are When true or when Th1, Th2 are true, cycle discriminator signal is true, if N is more than a setting value between 25 to 70, is used Clocking value of the clock timer at Tkz is directly added in synchrotimer.
2. a kind of fire alarm control system according to claim 1, it is characterised in that including:
10 ﹚ of centralized Control device ﹙, communications electronics, which are opened, closes 11 ﹚ of ﹙, 12 ﹚ of switch drive dynamic model block ﹙, SMS receipts transmitting apparatus ﹙ 13 ﹚, SIM Block 14 ﹚ of ﹙, fiery calamity is visited and surveys 15 ﹚ of device ﹙, 16 ﹚ of cycle examination electricity road ﹙, 17 ﹚ of area domain controller ﹙, fiery 18 ﹚ of controller ﹙ that go out, fire extinguishing driving 19 ﹚, Mie fire She Bei ﹙ of electricity Lu ﹙ 20 ﹚, wherein 11 ﹚ of communications electronics Kai Guan ﹙, 12 ﹚ of switch Qu dynamic model Kuai ﹙, cycle screen 16 ﹚ of electricity Lu ﹙ It is respectively included in single piece machine ﹙ U0 ﹚ in 17 ﹚ of area domain controller ﹙, 10 ﹚ of fiery 18 ﹚ of controller ﹙ and centralized Control device ﹙ that goes out;
Cycle screens 16 ﹚ of electricity Lu ﹙, by:Shu enter electricity Lu ﹙ S0 ﹚, voltage Zero-cross comparator Qi ﹙ V0 ﹚, screen point 1 at first voltage compare Qi ﹙ V1 ﹚ are formed with second voltage Bi compare Qi ﹙ V2 ﹚ at point 2 are screened, and Shu enters electricity Lu ﹙ S0 ﹚ for mains AC voltage to be passed through The partial pressure of resistance and diode is converted to the suitably stable input voltage of voltage comparator;
Single chip computer89C51 realizes serial communication, the microcontroller by I2C buses and main controller in SMS R-T unit 89C51 is connected also by serial port MAX232 with gsm module TC35i carries out data exchange.
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CN110533873A (en) * 2019-08-14 2019-12-03 吴飞宇 For the flame detection method of fire mobile in tunnel
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