CN106207966B - A kind of thermal-shutdown circuit - Google Patents
A kind of thermal-shutdown circuit Download PDFInfo
- Publication number
- CN106207966B CN106207966B CN201610562987.5A CN201610562987A CN106207966B CN 106207966 B CN106207966 B CN 106207966B CN 201610562987 A CN201610562987 A CN 201610562987A CN 106207966 B CN106207966 B CN 106207966B
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- Prior art keywords
- pmos tube
- connects
- operational amplifier
- tube
- grid
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H5/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection
- H02H5/04—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection responsive to abnormal temperature
- H02H5/042—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection responsive to abnormal temperature using temperature dependent resistors
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The invention belongs to electronic circuit technology fields, are related to a kind of thermal-shutdown circuit.The thermal-shutdown circuit of the present invention is typically overcome compared with thermal-shutdown circuit with current when temperature reached the shortcoming that warm spot immediately turns off chip; in chip over-temperature; degree according to excess temperature linearly reduces the output current of chip, forms Zigzag type overheat protector.
Description
Technical field
The invention belongs to electronic circuit technology fields, are related to a kind of thermal-shutdown circuit.
Background technology
In power integrated circuit, chip can be inevitably generated power dissipation at work so that the temperature of chip
Raising.When chip temperature is excessively high, stability, the reliability of chip can be caused to damage, therefore thermal-shutdown circuit has weight
The meaning wanted.Typical thermal-shutdown circuit when circuit reached warm spot, can immediately turn off chip, this limits excess temperature
Protect the scope of application of circuit.
Invention content
It is to be solved by this invention, aiming at the above problem existing for typical thermal-shutdown circuit, it is proposed that a kind of
Zigzag type thermal-shutdown circuit structure.
The technical scheme is that：A kind of thermal-shutdown circuit, including the first operational amplifier A 1, the second operation amplifier
Device A2, third operational amplifier A 3, trsanscondutance amplifier OTA, first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance
R4, the 5th resistance R5, the first diode D1, the second diode D2, the first PMOS tube MP1 and the second PMOS tube MP2；Wherein,
The normal phase input end of one operational amplifier A 1 connects the voltage generated by negative temperature coefficient thermistor, and the first operational amplifier A 1 is born
By being grounded after second resistance R2, the negative-phase input of the first operational amplifier A 1 is also followed by phase input terminal by first resistor R1
Its output terminal；The negative-phase input of trsanscondutance amplifier OTA connects the output terminal of the first operational amplifier A 1, trsanscondutance amplifier OTA's
Normal phase input end connects the second external reference voltages, the anode and second of the first diode D1 of output termination of trsanscondutance amplifier OTA
The anode of diode D2；The normal phase input end of third operational amplifier A 3 connects the drain electrode of the second PMOS tube MP2, third operation amplifier
The negative-phase input of device A3 connects third external reference voltages, and the second diode D2's of output termination of third operational amplifier A 3 is negative
Pole；The normal phase input end of second operational amplifier A2 connects the drain electrode of the first PMOS tube MP1；The negative of second operational amplifier A2 is defeated
Enter the first external reference voltages of termination；The source electrode of first PMOS tube MP1 connects power supply, and grid connects the defeated of second operational amplifier A2
Outlet, by being grounded after 3rd resistor R3, the cathode of the first diode D1 connects the first PMOS tube for the drain electrode of the first PMOS tube MP1
The tie point that MP1 drains with 3rd resistor R3；The source electrode of second PMOS tube MP2 connects power supply, and grid connects second operational amplifier
The output terminal of A2, the drain electrode of the second PMOS tube MP2 are grounded after passing sequentially through the 5th resistance R5 and the 4th resistance R4；5th resistance R5
Tie point with the 4th resistance R4 is the output terminal of thermal-shutdown circuit；
The third operational amplifier A 3 is a two-stage calculation amplifier, and the first order is folded common source and common grid amplifier,
The second level for source with amplifier, specifically include the first NMOS tube MN1, the second NMOS tube MN2, third PMOS tube MP3, the 4th PMOS
Pipe MP4, the 5th PMOS tube MP5, the 6th PMOS tube MP6, the 7th PMOS tube MP7, the 8th PMOS tube MP8, the 9th PMOS tube MP9,
First current source I1, the second current source I2, third current source I3, the 4th current source I4 and capacitance C；Wherein, third PMOS tube MP3
The first electric current is connect to pipe, the source electrode of third PMOS tube MP3 and the source electrode of the 4th PMOS tube MP4 for input with the 4th PMOS tube MP4
One end of source I1, another termination power of the first current source I1, the grid of third PMOS tube MP3 connect positive voltage input terminal, and the 4th
The grid of PMOS tube MP4 connects negative voltage input terminal；The source electrode of 5th PMOS tube MP5 connects power supply, and the grid of the 5th PMOS tube MP5 connects
The drain electrode of 8th PMOS tube MP8；The source electrode of 8th PMOS tube MP8 connects the drain electrode of the 5th PMOS tube MP5, the 8th PMOS tube MP8's
Grid connects the second bias voltage；The drain electrode of first NMOS tube MN1 connects the drain electrode of the 8th PMOS tube MP8, the grid of the first NMOS tube MN1
Pole connects the first bias voltage；The drain electrode of the source electrode and third PMOS tube MP3 of first NMOS tube MN1 connects the one of third current source I3
End, the other end ground connection of third current source I3；The source electrode of 6th PMOS tube MP6 connects power supply, and the grid of the 6th PMOS tube MP6 connects
The drain electrode of eight PMOS tube MP8；The source electrode of 7th PMOS tube MP7 connects the drain electrode of the 6th PMOS tube MP6, the grid of the 7th PMOS tube MP7
Pole connects the second bias voltage；The drain electrode of second NMOS tube MN2 connects the drain electrode of the 7th PMOS tube MP7, the grid of the second NMOS tube MN2
The first bias voltage is connect, the drain electrode of the source electrode and the 4th PMOS tube MP4 of the second NMOS tube MN2 connects one end of the 4th current source I4,
The other end ground connection of 4th current source I4；The source electrode of 9th PMOS tube MP9 meets one end of the second current source I2, the second current source I2
Another termination power, the grid of the 9th PMOS tube MP9 meets the company of the second NMOS tube MN2 drain electrodes and the 7th PMOS tube MP7 drain electrodes
Contact, the grid of the 9th PMOS tube MP9 after capacitance C also by being grounded；The source electrode of 9th PMOS tube MP9 and the second current source I2's
Tie point is the output terminal of third operational amplifier A 3.
Beneficial effects of the present invention are, thermal-shutdown circuit of the invention is compared with current typical thermal-shutdown circuit gram
It has taken when temperature reached the shortcoming that warm spot immediately turns off chip, in chip over-temperature, the degree according to excess temperature is linearly
Reduce the output current of chip, form Zigzag type overheat protector.
Description of the drawings
Fig. 1 is technical scheme of the present invention topology diagram；
Fig. 2 is the electrical block diagram of the amplifier A3 in the present invention；
Electrical characteristic schematic diagram when Fig. 3 is present invention work.
Specific embodiment
Below in conjunction with the accompanying drawings, detailed description of the present invention technical solution：
The topology diagram of the present invention is as shown in Figure 1, will be on R3 by amplifier A2, MP1 pipe and the R3 feedback circuit formed
Voltage clamping is VREF1 so that the electric current for flowing through R3 is definite value VREF1/R3, and MP2 manages and R3=R4+R5 identical with MP1 pipes, this
The electric current that sample flows through MP1 is equal to the electric current for flowing through MP2.The voltage VNTC of amplifier A1 positives termination linearly subtracts as temperature increases
It is small, this cause OTA negative terminal voltage (Also reduce.The output current △ I of OTA flow into resistance R3, therefore flow through
The electric current of MP1 pipes can accordingly reduce △ I so that flow through the electric currents of MP2 pipes and also accordingly reduce voltage on △ I, such R4
Vocp can also reduce △ IR4.Wherein Vocp is the input signal as electric current limit comparator in circuit system.VNTC's in this way
Variation can cause the input Vocp of electric current limit comparator accordingly to change.The course of work is analyzed in detail below in conjunction with Fig. 3.
Fig. 3 is the operating diagram of the present invention.Horizontal axis represents thermistor voltage VNTC, and left vertical represents output current
Peak value, right vertical represent electric current limit comparator input voltage.When temperature is T1, the output of VNTC VNTC1, OTA
Electric current △ I are zero, and the electric current for flowing through MP2 pipes keeps VREF1/R3 constant, at this moment electric current limit comparator input voltage is Vocp1,
Corresponding peak point current is Ipk.At this moment connection amplifier A3 positive terminal voltages areIt is enabled to be more than reference voltage
VREF3, amplifier A3 output are high level so that diode D2 is turned off.As temperature increases, VNTC voltages decline, by before
Description understands that Vocp also declines therewith, allows for current peak in this way and is also begun to decline by Ipk.Before temperature rise to T2,
The positive terminal voltage of amplifier A3 is consistently greater than VREF3, and A3 exports high level always during this, and diode D2 is also at shutdown shape
State.
When temperature rise reaches T2, the size of VNTC is VNTC2 at this time, and the output current of OTA is △ I2, flows through MP2
The electric current of pipe reduces △ I2, and at this moment Vocp falls to Vocp2, and circuit pair at this time can be realized by reasonably designing circuit parameter
The peak point current drop by half answered, as Ipk/2.By analyzing it is found that at this timeAt this moment the positive terminal of amplifier A3
Voltage isIt is exactly equal to reference voltage V REF3.It is assumed that temperature is after of continuing rising
Height causes voltage VNTC to continue to decline, so that the output current of OTA is slightly larger than △ I2, the electric current for flowing through MP2 in this way can be small
In VREF1/R3-△ I2, this can cause the positive terminal voltage of amplifier A3 less than VREF3, to pass through the amplification of A3 so that A3
Output voltage decline, so as to enable diode D2 be connected.A3 concrete structures shown in Fig. 2 are analyzed to will also realize that, the A3 second level
Source electrode device can absorb electric current.This can cause the one part of current that OTA is exported to flow into A3 by D2.From this analysis, amplifier
A3, A2 and MP2 form feedback loop.Obtain the function that A3 at this time is switched to trsanscondutance amplifier by comparator function.
When temperature continues raising, the output current of OTA is △ I ', by the analysis of VNTC=VNTC2 states it is found that A3,
The feedback loop that A2 and MP2 is formed so that the positive terminal voltage clamping of A3 is VREF3, the unwanted currents △ of such OTA outputs
The electric current of I '-△ I2 flows into A3 by diode D2, and it is constant that such Vocp remains Vocp2 so that output current keeps Ipk/2
It is constant.
Beneficial effects of the present invention are to devise a kind of Zigzag type thermal-shutdown circuit, realize line when the temperature rises
Property reduce output current come reduce chip generation heat so that chip can work on rather than immediately turn off chip, expand
The use scope of thermal-shutdown circuit.
Claims (1)
1. a kind of thermal-shutdown circuit, including the first operational amplifier A 1, second operational amplifier A2, third operational amplifier
A3, trsanscondutance amplifier OTA, first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, first
Diode D1, the second diode D2, the first PMOS tube MP1 and the second PMOS tube MP2；Wherein, the first operational amplifier A 1 is being just
The voltage that mutually input termination is generated by negative temperature coefficient thermistor, the negative-phase input of the first operational amplifier A 1 pass through the second electricity
It is grounded after resistance R2, the negative-phase input of the first operational amplifier A 1 is also followed by its output terminal by first resistor R1；Mutual conductance is amplified
The negative-phase input of device OTA connects the output terminal of the first operational amplifier A 1, and the normal phase input end of trsanscondutance amplifier OTA is connect outside second
Portion's reference voltage, the anode of the first diode D1 of output termination of trsanscondutance amplifier OTA and the anode of the second diode D2；Third
The normal phase input end of operational amplifier A 3 connects the drain electrode of the second PMOS tube MP2, and the negative-phase input of third operational amplifier A 3 connects
Third external reference voltages, the cathode of the second diode D2 of output termination of third operational amplifier A 3；Second operational amplifier
The normal phase input end of A2 connects the drain electrode of the first PMOS tube MP1；The negative-phase input of second operational amplifier A2 connects the first outside base
Quasi- voltage；The source electrode of first PMOS tube MP1 connects power supply, and grid connects the output terminal of second operational amplifier A2, the first PMOS tube
By being grounded after 3rd resistor R3, the cathode of the first diode D1 connects the first PMOS tube MP1 drain electrodes and 3rd resistor for the drain electrode of MP1
The tie point of R3；The source electrode of second PMOS tube MP2 connects power supply, and grid connects the output terminal of second operational amplifier A2, and second
The drain electrode of PMOS tube MP2 is grounded after passing sequentially through the 5th resistance R5 and the 4th resistance R4；5th resistance R5's and the 4th resistance R4
Tie point is the output terminal of thermal-shutdown circuit；
The third operational amplifier A 3 is a two-stage calculation amplifier, and the first order is folded common source and common grid amplifier, second
Grade for source with amplifier, specifically include the first NMOS tube MN1, the second NMOS tube MN2, third PMOS tube MP3, the 4th PMOS tube
MP4, the 5th PMOS tube MP5, the 6th PMOS tube MP6, the 7th PMOS tube MP7, the 8th PMOS tube MP8, the 9th PMOS tube MP9,
One current source I1, the second current source I2, third current source I3, the 4th current source I4 and capacitance C；Wherein, third PMOS tube MP3 and
4th PMOS tube MP4 connects the first current source for input to pipe, the source electrode of third PMOS tube MP3 and the source electrode of the 4th PMOS tube MP4
One end of I1, another termination power of the first current source I1, the grid of third PMOS tube MP3 connect positive voltage input terminal, and the 4th
The grid of PMOS tube MP4 connects negative voltage input terminal；The source electrode of 5th PMOS tube MP5 connects power supply, and the grid of the 5th PMOS tube MP5 connects
The drain electrode of 8th PMOS tube MP8；The source electrode of 8th PMOS tube MP8 connects the drain electrode of the 5th PMOS tube MP5, the 8th PMOS tube MP8's
Grid connects the second bias voltage；The drain electrode of first NMOS tube MN1 connects the drain electrode of the 8th PMOS tube MP8, the grid of the first NMOS tube MN1
Pole connects the first bias voltage；The drain electrode of the source electrode and third PMOS tube MP3 of first NMOS tube MN1 connects the one of third current source I3
End, the other end ground connection of third current source I3；The source electrode of 6th PMOS tube MP6 connects power supply, and the grid of the 6th PMOS tube MP6 connects
The drain electrode of eight PMOS tube MP8；The source electrode of 7th PMOS tube MP7 connects the drain electrode of the 6th PMOS tube MP6, the grid of the 7th PMOS tube MP7
Pole connects the second bias voltage；The drain electrode of second NMOS tube MN2 connects the drain electrode of the 7th PMOS tube MP7, the grid of the second NMOS tube MN2
The first bias voltage is connect, the drain electrode of the source electrode and the 4th PMOS tube MP4 of the second NMOS tube MN2 connects one end of the 4th current source I4,
The other end ground connection of 4th current source I4；The source electrode of 9th PMOS tube MP9 meets one end of the second current source I2, the second current source I2
Another termination power, the grid of the 9th PMOS tube MP9 meets the company of the second NMOS tube MN2 drain electrodes and the 7th PMOS tube MP7 drain electrodes
Contact, the grid of the 9th PMOS tube MP9 after capacitance C also by being grounded；The source electrode of 9th PMOS tube MP9 and the second current source I2's
Tie point is the output terminal of third operational amplifier A 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610562987.5A CN106207966B (en) | 2016-07-18 | 2016-07-18 | A kind of thermal-shutdown circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610562987.5A CN106207966B (en) | 2016-07-18 | 2016-07-18 | A kind of thermal-shutdown circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106207966A CN106207966A (en) | 2016-12-07 |
| CN106207966B true CN106207966B (en) | 2018-06-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610562987.5A Expired - Fee Related CN106207966B (en) | 2016-07-18 | 2016-07-18 | A kind of thermal-shutdown circuit |
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| CN (1) | CN106207966B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107634505B (en) * | 2017-10-10 | 2019-03-29 | 郑州财经学院 | A kind of electronic equipment with protection circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104967095A (en) * | 2015-07-29 | 2015-10-07 | 电子科技大学 | Over-temperature protection circuit |
| CN104967094A (en) * | 2015-07-29 | 2015-10-07 | 电子科技大学 | Over-temperature protection circuit |
| CN104980016A (en) * | 2015-06-19 | 2015-10-14 | 西安三馀半导体有限公司 | DC-DC converter with linear over-temperature protection circuit |
-
2016
- 2016-07-18 CN CN201610562987.5A patent/CN106207966B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104980016A (en) * | 2015-06-19 | 2015-10-14 | 西安三馀半导体有限公司 | DC-DC converter with linear over-temperature protection circuit |
| CN104967095A (en) * | 2015-07-29 | 2015-10-07 | 电子科技大学 | Over-temperature protection circuit |
| CN104967094A (en) * | 2015-07-29 | 2015-10-07 | 电子科技大学 | Over-temperature protection circuit |
Non-Patent Citations (3)
| Title |
|---|
| 一种基于电流比较的新型过温保护电路;蔡小祥等;《微电子学》;20120229;第42卷(第1期);58-62 * |
| 一种带过温保护和折返电流限的LDO设计;刘明亮等;《微电子学》;20110630;第41卷(第3期) * |
| 一种新型双稳态过温保护电路;吕连国等;《电子科技大学学报》;20070228;第36卷(第1期);50-52 * |
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| Publication number | Publication date |
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| CN106207966A (en) | 2016-12-07 |
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