CN106207966A - A kind of thermal-shutdown circuit - Google Patents
A kind of thermal-shutdown circuit Download PDFInfo
- Publication number
- CN106207966A CN106207966A CN201610562987.5A CN201610562987A CN106207966A CN 106207966 A CN106207966 A CN 106207966A CN 201610562987 A CN201610562987 A CN 201610562987A CN 106207966 A CN106207966 A CN 106207966A
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- pmos
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- drain electrode
- operational amplifier
- grid
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H5/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection
- H02H5/04—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection responsive to abnormal temperature
- H02H5/042—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection responsive to abnormal temperature using temperature dependent resistors
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The invention belongs to electronic circuit technology field, relate to a kind of thermal-shutdown circuit.The thermal-shutdown circuit of the present invention overcomes compared with the most typical thermal-shutdown circuit and immediately turned off the weak point of chip when temperature arrives warm spot; when chip over-temperature; reduce the output electric current of chip according to the degree of excess temperature linearly, form Zigzag type overheat protector.
Description
Technical field
The invention belongs to electronic circuit technology field, relate to a kind of thermal-shutdown circuit.
Background technology
In power integrated circuit, chip operationally can be inevitably generated power dissipation so that the temperature of chip
Raise.When chip temperature is too high, the stability of chip, reliability can be caused damage, therefore thermal-shutdown circuit has weight
The meaning wanted.Typical thermal-shutdown circuit, when circuit reached warm spot, can immediately turn off chip, and this limits excess temperature
The scope of application of protection circuit.
Summary of the invention
To be solved by this invention, it is simply that the problems referred to above existed for typical thermal-shutdown circuit, it is proposed that a kind of
Zigzag type thermal-shutdown circuit structure.
The technical scheme is that a kind of thermal-shutdown circuit, including first operational amplifier A the 1, second operation amplifier
Device A2, the 3rd operational amplifier A 3, trsanscondutance amplifier OTA, the first resistance R1, the second resistance R2, the 3rd resistance E3, the 4th resistance
R4, the 5th resistance R5, the first diode D1, the second diode D2, the first PMOS MP1 and the second PMOS MP2；Wherein,
The normal phase input end of one operational amplifier A 1 connects the voltage produced by negative temperature coefficient critesistor, bearing of the first operational amplifier A 1
Phase input is by ground connection after the second resistance R2, and the negative-phase input of the first operational amplifier A 1 is followed by also by the first resistance R1
Its outfan；The negative-phase input of trsanscondutance amplifier OTA connects the outfan of the first operational amplifier A 1, trsanscondutance amplifier OTA's
Normal phase input end connects the second external reference voltages, the positive pole and second of the output termination first diode D1 of trsanscondutance amplifier OTA
The positive pole of diode D2；The normal phase input end of the 3rd operational amplifier A 3 connects the drain electrode of the second PMOS MP2, the 3rd operation amplifier
The negative-phase input of device A3 connects the 3rd external reference voltages, and the output termination second diode D2's of the 3rd operational amplifier A 3 is negative
Pole；The normal phase input end of the second operational amplifier A 2 connects the drain electrode of the first PMOS MP1；The negative of the second operational amplifier A 2 is defeated
Enter termination the first external reference voltages；The source electrode of the first PMOS MP1 connects power supply, and its grid connects the defeated of the second operational amplifier A 2
Going out end, the drain electrode of the first PMOS MP1 connects the first PMOS by ground connection after the 3rd resistance R3, the negative pole of the first diode D1
MP1 drain electrode and the junction point of the 3rd resistance R3；The source electrode of the second PMOS MP2 connects power supply, and its grid connects the second operational amplifier
The outfan of A2, the drain electrode of the second PMOS MP2 passes sequentially through ground connection after the 5th resistance R5 and the 4th resistance R4；5th resistance R5
With the outfan that the junction point of the 4th resistance R4 is temperature protection circuit；
Described 3rd operational amplifier A 3 is a two-stage calculation amplifier, and the first order is folded common source and common grid amplifier,
The second level be source with amplifier, specifically include the first NMOS tube MN1, the second NMOS tube MN2, the 3rd PMOS MP3, the 4th PMOS
Pipe MP4, the 5th PMOS MP5, the 6th PMOS MP6, the 7th PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9,
First current source I1, the second current source I2, the 3rd current source I3, the 4th current source I4 and electric capacity C；Wherein, the 3rd PMOS MP3
For input, pipe, the source electrode of the 3rd PMOS MP3 and the source electrode of the 4th PMOS MP4 are connect the first electric current with the 4th PMOS MP4
One end of source I1, another termination power of the first current source I1, the grid of the 3rd PMOS MP3 connects positive voltage input, and the 4th
The grid of PMOS MP4 connects negative voltage input；The source electrode of the 5th PMOS MP5 connects power supply, and the grid of the 5th PMOS MP5 connects
The drain electrode of the 8th PMOS MP8；The source electrode of the 8th PMOS MP8 connects the drain electrode of the 5th PMOS MP5, the 8th PMOS MP8
Grid connects the second bias voltage；The drain electrode of the first NMOS tube MN1 connects the drain electrode of the 8th PMOS MP8, the grid of the first NMOS tube MN1
Pole connects the first bias voltage；The source electrode of the first NMOS tube MN1 and the drain electrode of the 3rd PMOS MP3 meet the one of the 3rd current source I3
End, the other end ground connection of the 3rd current source I3；The source electrode of the 6th PMOS MP6 connects power supply, and the grid of the 6th PMOS MP6 connects
The drain electrode of eight PMOS MP8；The source electrode of the 7th PMOS MP7 connects the drain electrode of the 6th PMOS MP6, the grid of the 7th PMOS MP7
Pole connects the second bias voltage；The drain electrode of the second NMOS tube MN2 connects the drain electrode of the 7th PMOS MP7, the grid of the second NMOS tube MN2
Connecing the first bias voltage, the source electrode of the second NMOS tube MN2 and the drain electrode of the 4th PMOS MP4 connect one end of the 4th current source I4,
The other end ground connection of the 4th current source I4；The source electrode of the 9th PMOS MP9 meets one end of the second current source I2, the second current source I2
Another termination power, the grid of the 9th PMOS MP9 connect second NMOS tube MN2 drain electrode and the 7th PMOS MP7 drain electrode company
Contact, the grid of the 9th PMOS MP9 is also by ground connection after electric capacity C；The source electrode of the 9th PMOS MP9 and the second current source I2's
Junction point is the outfan of the 3rd operational amplifier A 3.
Beneficial effects of the present invention is, the thermal-shutdown circuit of the present invention and the most typical thermal-shutdown circuit phase Bick
Having taken and immediately turned off the weak point of chip when temperature arrives warm spot, when chip over-temperature, the degree of foundation excess temperature is linearly
Reduce the output electric current of chip, form Zigzag type overheat protector.
Accompanying drawing explanation
Fig. 1 is technical scheme topology diagram；
Fig. 2 is the electrical block diagram of amplifier A3 in the present invention；
Fig. 3 is present invention electrical characteristic schematic diagram when working.
Detailed description of the invention
Below in conjunction with the accompanying drawings, technical scheme is described in detail:
The topology diagram of the present invention is as it is shown in figure 1, the feedback circuit being made up of amplifier A2, MP1 pipe and R3 is by R3
Voltage clamp is VREF1 so that the electric current flowing through R3 is definite value VREF1/R3, and MP2 manages and R3=R4+R5 identical with MP1 pipe, this
Sample flows through the electric current of MP1 equal to the electric current flowing through MP2.The voltage VNTC of amplifier A1 positive termination raises along with temperature and linearly subtracts
Little, this makes the negative phase end voltage of OTAAlso reduce.The output electric current △ I of OTA flows into resistance R3, therefore flows through
The electric current of MP1 pipe can reduce △ I accordingly so that the electric current flowing through MP2 pipe reduces △ I, the voltage on such R4 the most accordingly
Vocp also can reduce △ I R4.Wherein Vocp is as the input signal of electric current limit comparator in circuit system.So VNTC's
Change can make the input Vocp of electric current limit comparator change accordingly.Work process is analyzed in detail below in conjunction with Fig. 3.
Fig. 3 is the operating diagram of the present invention.Transverse axis represents that thermistor voltage VNTC, left vertical represent output electric current
Peak value, right vertical represent electric current limit comparator input voltage.When temperature is T1, VNTC is the output of VNTC1, OTA
Electric current △ I is zero, and the electric current flowing through MP2 pipe keeps VREF1/R3 constant, and at this moment electric current limit comparator input voltage is Vocp1,
Corresponding peak point current is Ipk.At this moment connecting amplifier A3 positive terminal voltage isIt is made to be more than reference voltage
VREF3, amplifier A3 is output as high level so that diode D2 turns off.Along with temperature raises, VNTC voltage declines, by before
Vocp knowable to describing declines the most therewith, thus makes current peak also be begun to decline by Ipk.Before temperature rises to T2,
The positive terminal voltage of amplifier A3 is consistently greater than VREF3, and during this, A3 exports high level all the time, and diode D2 is also at turning off shape
State.
When temperature rise reach T2 time, now the size of VNTC be the output electric current of VNTC2, OTA be △ I2, flow through MP2
The electric current of pipe reduces △ I2, and at this moment Vocp drops to Vocp2, can realize now circuit pair by reasonably design circuit parameter
The peak point current drop by half answered, is Ipk/2.By analyzing, nowAt this moment the positive terminal of amplifier A3
Voltage isIt is exactly equal to reference voltage V REF3.It is assumed that temperature continues to rise
Height, causes voltage VNTC to continue to decline, so that the output electric current of OTA is slightly larger than △ I2, the electric current so flowing through MP2 can be little
In VREF1/R3 △ I2, this can make the positive terminal voltage of amplifier A3 be less than VREF3, by the amplification of A3 so that A3
Output voltage decline, thus make diode D2 turn on.A3 concrete structure shown in analysis chart 2 will also realize that, the A3 second level
Source electrode device can absorb electric current.This one part of current that OTA can be made to export flows into A3 through D2.Thus analyze and understand, amplifier
A3, A2 and MP2 constitute feedback loop.Obtain now A3 and transferred to the function of trsanscondutance amplifier by comparator function.
When temperature continues to raise, the output electric current of OTA is △ I ', from the analysis of VNTC=VNTC2 state, A3,
The feedback loop that A2 and MP2 is constituted makes the positive terminal voltage clamp of A3 be VREF3, the unwanted currents △ of such OTA output
The electric current of I ' △ I2 is flowed into A3 by diode D2, and it is constant that such Vocp remains Vocp2 so that output electric current keeps Ipk/2
Constant.
Beneficial effects of the present invention is, devises a kind of Zigzag type thermal-shutdown circuit, it is achieved that the line when temperature raises
Property reduce output electric current reduce chip produce heat so that chip can work on rather than immediately turn off chip, expand
The range of thermal-shutdown circuit.
Claims (1)
1. a thermal-shutdown circuit, including first operational amplifier A the 1, second operational amplifier A the 2, the 3rd operational amplifier
A3, trsanscondutance amplifier OTA, the first resistance R1, the second resistance R2, the 3rd resistance E3, the 4th resistance R4, the 5th resistance R5, first
Diode D1, the second diode D2, the first PMOS MP1 and the second PMOS MP2；Wherein, the first operational amplifier A 1 is just
The voltage that input termination mutually is produced by negative temperature coefficient critesistor, the negative-phase input of the first operational amplifier A 1 is by the second electricity
Ground connection after resistance R2, the negative-phase input of the first operational amplifier A 1 is followed by its outfan also by the first resistance R1；Mutual conductance is amplified
The negative-phase input of device OTA connects the outfan of the first operational amplifier A 1, and the normal phase input end of trsanscondutance amplifier OTA connects outside second
Portion's reference voltage, the positive pole of the output termination first diode D1 of trsanscondutance amplifier OTA and the positive pole of the second diode D2；3rd
The normal phase input end of operational amplifier A 3 connects the drain electrode of the second PMOS MP2, and the negative-phase input of the 3rd operational amplifier A 3 connects
3rd external reference voltages, the negative pole of the output termination second diode D2 of the 3rd operational amplifier A 3；Second operational amplifier
The normal phase input end of A2 connects the drain electrode of the first PMOS MP1；The negative-phase input of the second operational amplifier A 2 connects the first outside base
Quasi-voltage；The source electrode of the first PMOS MP1 connects power supply, and its grid connects the outfan of the second operational amplifier A 2, the first PMOS
The drain electrode of MP1 is by ground connection after the 3rd resistance R3, and the negative pole of the first diode D1 connects the first PMOS MP1 drain electrode and the 3rd resistance
The junction point of R3；The source electrode of the second PMOS MP2 connects power supply, and its grid connects the outfan of the second operational amplifier A 2, and second
The drain electrode of PMOS MP2 passes sequentially through ground connection after the 5th resistance R5 and the 4th resistance R4；5th resistance R5's and the 4th resistance R4
Junction point is the outfan of temperature protection circuit；
Described 3rd operational amplifier A 3 is a two-stage calculation amplifier, and the first order is folded common source and common grid amplifier, second
Level be source with amplifier, specifically include the first NMOS tube MN1, the second NMOS tube MN2, the 3rd PMOS MP3, the 4th PMOS
MP4, the 5th PMOS MP5, the 6th PMOS MP6, the 7th PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9,
One current source I1, the second current source I2, the 3rd current source I3, the 4th current source I4 and electric capacity C；Wherein, the 3rd PMOS MP3 and
4th PMOS MP4 connects the first current source for input to pipe, the source electrode of the 3rd PMOS MP3 and the source electrode of the 4th PMOS MP4
One end of I1, another termination power of the first current source I1, the grid of the 3rd PMOS MP3 connects positive voltage input, and the 4th
The grid of PMOS MP4 connects negative voltage input；The source electrode of the 5th PMOS MP5 connects power supply, and the grid of the 5th PMOS MP5 connects
The drain electrode of the 8th PMOS MP8；The source electrode of the 8th PMOS MP8 connects the drain electrode of the 5th PMOS MP5, the 8th PMOS MP8
Grid connects the second bias voltage；The drain electrode of the first NMOS tube MN1 connects the drain electrode of the 8th PMOS MP8, the grid of the first NMOS tube MN1
Pole connects the first bias voltage；The source electrode of the first NMOS tube MN1 and the drain electrode of the 3rd PMOS MP3 meet the one of the 3rd current source I3
End, the other end ground connection of the 3rd current source I3；The source electrode of the 6th PMOS MP6 connects power supply, and the grid of the 6th PMOS MP6 connects
The drain electrode of eight PMOS MP8；The source electrode of the 7th PMOS MP7 connects the drain electrode of the 6th PMOS MP6, the grid of the 7th PMOS MP7
Pole connects the second bias voltage；The drain electrode of the second NMOS tube MN2 connects the drain electrode of the 7th PMOS MP7, the grid of the second NMOS tube MN2
Connecing the first bias voltage, the source electrode of the second NMOS tube MN2 and the drain electrode of the 4th PMOS MP4 connect one end of the 4th current source I4,
The other end ground connection of the 4th current source I4；The source electrode of the 9th PMOS MP9 meets one end of the second current source I2, the second current source I2
Another termination power, the grid of the 9th PMOS MP9 connect second NMOS tube MN2 drain electrode and the 7th PMOS MP7 drain electrode company
Contact, the grid of the 9th PMOS MP9 is also by ground connection after electric capacity C；The source electrode of the 9th PMOS MP9 and the second current source I2's
Junction point is the outfan of the 3rd operational amplifier A 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610562987.5A CN106207966B (en) | 2016-07-18 | 2016-07-18 | A kind of thermal-shutdown circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610562987.5A CN106207966B (en) | 2016-07-18 | 2016-07-18 | A kind of thermal-shutdown circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106207966A true CN106207966A (en) | 2016-12-07 |
| CN106207966B CN106207966B (en) | 2018-06-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610562987.5A Expired - Fee Related CN106207966B (en) | 2016-07-18 | 2016-07-18 | A kind of thermal-shutdown circuit |
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| CN (1) | CN106207966B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107634505A (en) * | 2017-10-10 | 2018-01-26 | 郑州财经学院 | A kind of electronic equipment with protection circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104967095A (en) * | 2015-07-29 | 2015-10-07 | 电子科技大学 | Over-temperature protection circuit |
| CN104967094A (en) * | 2015-07-29 | 2015-10-07 | 电子科技大学 | Over-temperature protection circuit |
| CN104980016A (en) * | 2015-06-19 | 2015-10-14 | 西安三馀半导体有限公司 | DC-DC converter with linear over-temperature protection circuit |
-
2016
- 2016-07-18 CN CN201610562987.5A patent/CN106207966B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104980016A (en) * | 2015-06-19 | 2015-10-14 | 西安三馀半导体有限公司 | DC-DC converter with linear over-temperature protection circuit |
| CN104967095A (en) * | 2015-07-29 | 2015-10-07 | 电子科技大学 | Over-temperature protection circuit |
| CN104967094A (en) * | 2015-07-29 | 2015-10-07 | 电子科技大学 | Over-temperature protection circuit |
Non-Patent Citations (3)
| Title |
|---|
| 刘明亮等: "一种带过温保护和折返电流限的LDO设计", 《微电子学》 * |
| 吕连国等: "一种新型双稳态过温保护电路", 《电子科技大学学报》 * |
| 蔡小祥等: "一种基于电流比较的新型过温保护电路", 《微电子学》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107634505A (en) * | 2017-10-10 | 2018-01-26 | 郑州财经学院 | A kind of electronic equipment with protection circuit |
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| Publication number | Publication date |
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| CN106207966B (en) | 2018-06-19 |
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Granted publication date: 20180619 Termination date: 20210718 |