CN106206617A - Array base palte based on low temperature polycrystalline silicon and preparation method thereof - Google Patents
Array base palte based on low temperature polycrystalline silicon and preparation method thereof Download PDFInfo
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- CN106206617A CN106206617A CN201610763642.6A CN201610763642A CN106206617A CN 106206617 A CN106206617 A CN 106206617A CN 201610763642 A CN201610763642 A CN 201610763642A CN 106206617 A CN106206617 A CN 106206617A
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- Prior art keywords
- elongated slot
- layer
- metal level
- display area
- array base
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 22
- 238000002360 preparation method Methods 0.000 title description 2
- 229910052751 metal Inorganic materials 0.000 claims abstract description 43
- 239000002184 metal Substances 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 14
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 2
- 239000010931 gold Substances 0.000 claims 2
- 229910052737 gold Inorganic materials 0.000 claims 2
- 230000000694 effects Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses the manufacture method of a kind of array base palte based on low temperature polycrystalline silicon, including: make insulating barrier；Described insulating barrier makes metal level, and etching forms the first pattern on described metal level；Described first pattern is coated with one layer of flatness layer, and on described flatness layer, digs out the second pattern of the elongated slot including running through its thickness direction along the length direction of described flatness layer；Described flatness layer covers layer of transparent conductive layer, and etches the 3rd pattern.The invention also discloses a kind of array base palte based on low temperature polycrystalline silicon.The present invention is by producing second pattern with the elongated slot running through its thickness direction on flatness layer, make can more convenient, reliably produce the countersink both being connected between the common electrode layer of array base palte and drain electrode, add the contact area between countersink and drain electrode, reduce contact impedance, reduce source electrode, drain electrode and the loose contact rate of public electrode, and then improve display effect.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly relate to a kind of array base palte based on low temperature polycrystalline silicon and system thereof
Make method.
Background technology
In LTPS (Low Temperature Poly-silicon, low temperature polycrystalline silicon) element makes, need to pass through source
Pole, drain contact ITO (Indium-Tin Oxide, tin indium oxide) supply public electrode voltages signal.The most traditional sets
In meter mode, by perforate on flatness layer as public electrode cabling, source electrode, drain electrode are bigger with the contact impedance of ITO so that
The voltage of input public electrode is more to be consumed with ITO contact impedance by source electrode, drain electrode, or owing to etching is uneven or other are different
Often result in source electrode, drain electrode and ITO loose contact so that the actual public electrode voltages in effective display area is relatively low causes display bad.
Summary of the invention
The deficiency existed in view of prior art, the invention provides a kind of array base palte based on low temperature polycrystalline silicon and system thereof
Making method, can reduce source electrode, drain electrode and the contact impedance of public electrode, reduction source electrode, drain electrode contact not with public electrode
Yield, and then improve display effect.
In order to realize above-mentioned purpose, present invention employs following technical scheme:
A kind of manufacture method of array base palte based on low temperature polycrystalline silicon, including:
Make insulating barrier；
Described insulating barrier makes metal level, and etching forms the first pattern on described metal level；
Described first pattern is coated with one layer of flatness layer, and along the length direction of described flatness layer on described flatness layer
Dig out the second pattern of the elongated slot including running through its thickness direction；
Described flatness layer covers layer of transparent conductive layer, and etches the 3rd pattern.
As one of which embodiment, described metal level is titanium or aluminum.
Preferably, described elongated slot is opened in non-display area, and described elongated slot is one, and with described in non-display area
The shape of metal level is identical.
Or, described elongated slot is opened in non-display area, and described elongated slot is multiple, is disposed on non-display area
On the bearing of trend of described metal level.
Or, described elongated slot is opened in non-display area, and described elongated slot is multiple, and each described elongated slot is with non-display
The shape of the described metal level in region is identical, is disposed side by side on the width of described metal level of non-display area.
Another object of the present invention is to provide a kind of array base palte based on low temperature polycrystalline silicon, be included in non-display area
Insulating barrier, metal level, flatness layer and the transparency conducting layer set gradually from bottom to top, described flatness layer includes running through its thickness side
To elongated slot, described transparency conducting layer includes being formed in described elongated slot, is fitted in the countersink of described layer on surface of metal.
As one of which embodiment, described metal level is titanium or aluminum.
Preferably, described elongated slot is opened in non-display area, and described elongated slot is one, and with described in non-display area
The shape of metal level is identical.
Or, described elongated slot is opened in non-display area, and described elongated slot is multiple, is disposed on non-display area
On the bearing of trend of described metal level.
Or, described elongated slot is opened in non-display area, and described elongated slot is multiple, and each described elongated slot is with non-display
The shape of the described metal level in region is identical, is disposed side by side on the width of described metal level of non-display area.
The present invention is by producing second pattern with the elongated slot running through its thickness direction on flatness layer so that array
Can more convenient, reliably produce the countersink both being connected between the common electrode layer of substrate with drain electrode, add down
Contact area between sinking partly and draining, reduces contact impedance, reduces source electrode, drain electrode and the loose contact of public electrode
Rate, and then improve display effect.
Accompanying drawing explanation
Fig. 1 is the metal level processing technology schematic diagram of the embodiment of the present invention.
Fig. 2 is the local section schematic diagram after the metal level making of the embodiment of the present invention.
Fig. 3 is the flatness layer processing technology schematic diagram of the embodiment of the present invention.
Fig. 4 is the local section schematic diagram after the flatness layer making of the embodiment of the present invention.
Fig. 5 is the transparency conducting layer processing technology schematic diagram of the embodiment of the present invention.
Fig. 6 is the local section schematic diagram after the transparency conducting layer making of the embodiment of the present invention.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, right
The present invention further describes.Should be appreciated that specific embodiment described herein, and need not only in order to explain the present invention
In limiting the present invention.
Refering to Fig. 1～6, the manufacture method of the array base palte based on low temperature polycrystalline silicon of the embodiment of the present invention includes:
Make insulating barrier 10；
Insulating barrier 10 makes metal level 20, and etching forms the first pattern (such as Fig. 1 and Fig. 2) on metal level 20；
First pattern is coated with one layer of flatness layer 30, and on flatness layer 30, digs out bag along the length direction of flatness layer 30
Include second pattern (such as Fig. 3 and Fig. 4) of the elongated slot 300 running through its thickness direction；
Flatness layer 30 covers layer of transparent conductive layer 40, and etches the 3rd pattern (such as Fig. 5 and Fig. 6).
Preferably, metal level 20 is titanium or aluminum, metal level 20 is low temperature polycrystalline silicon after etching formation the first pattern thin
The drain electrode of film transistor, transparency conducting layer 40 is electrically conducting transparent ITO, as public electrode.It is understood that insulating barrier 10
Bottom has glass substrate, is also provided with gate electrode etc. simultaneously.
The elongated slot 300 of the present embodiment is opened in non-display area, and elongated slot 300 only one of which, and its shape is with non-display
The shape of the metal level 20 in region is identical, i.e. extends around viewing area.Owing to whole flatness layer 30 is only offered in the middle part of its width
Having the elongated slot 300 of a channel-like, the transparency conducting layer 40 on its top etches processing procedure can be much smoother, do not have etching uneven or
Other are abnormal and cause loose contact, therefore can improve processing technology well.
In other embodiments, elongated slot 300 is offered also at non-display area, but elongated slot 300 is provided with multiple, and interval sets
Put on the bearing of trend of the metal level 20 of non-display area, such as, each edge of corresponding metal level 20, flatness layer 30 is offered
There is the elongated slot 300 of a length direction running through corresponding sides.Or, elongated slot 300 is opened in non-display area, and elongated slot 300 is
Multiple, but each elongated slot 300 is identical with the shape of the metal level 20 of non-display area, is disposed side by side on the metal of non-display area
On the width of layer 20, i.e. the width at metal level 20 offers a plurality of elongated elongated slot 300.But both technique is still
Cannot be compared with above preferred embodiment, the etching of transparency conducting layer 40 is it is possible to there is the phenomenon that etching is uneven.
Therefore, according to above-mentioned manufacture method, the embodiment of the present invention array base palte have non-display area from lower and
On the insulating barrier 10, metal level 20, flatness layer 30 and the transparency conducting layer 40 that set gradually, flatness layer 30 includes running through its thickness side
To elongated slot 300, transparency conducting layer 40 includes being formed in elongated slot 300, is fitted in the countersink 400 on metal level 20 surface.
Area just because of the single elongated slot 300 decreasing the quantity of elongated slot 300, increase so that transparency conducting layer 40
Etching process in be not easy to occur the phenomenons such as residual, uneven or breach, transparency conducting layer 40 has and runs through this elongated slot 300 and paste
It is combined in the countersink 400 (such as Fig. 6) on metal level 20 surface.Elongated slot 300 compared with prior art area is bigger, effectively reduces
The contact impedance of public electrode and drain electrode, it is ensured that lighting picture normal.
In sum, the present invention is by producing second figure with the elongated slot running through its thickness direction on flatness layer
Case so that can more convenient, reliably produce the sinking portion both being connected between the common electrode layer of array base palte with drain electrode
Point, add the contact area between countersink and drain electrode, reduce contact impedance, reduce source electrode, drain electrode and public electrode
Loose contact rate, and then improve display effect.
The above is only the detailed description of the invention of the application, it is noted that for the ordinary skill people of the art
For Yuan, on the premise of without departing from the application principle, it is also possible to make some improvements and modifications, these improvements and modifications also should
It is considered as the protection domain of the application.
Claims (10)
1. the manufacture method of an array base palte based on low temperature polycrystalline silicon, it is characterised in that including:
Make insulating barrier (10)；
Described insulating barrier (10) makes metal level (20), and forms the first pattern in the upper etching of described metal level (20)；
Described first pattern is coated with one layer of flatness layer (30), and along the length direction of described flatness layer (30) described smooth
The second pattern of the elongated slot (300) including running through its thickness direction is dug out on layer (30)；
At described flatness layer (30) upper covering layer of transparent conductive layer (40), and etch the 3rd pattern.
The manufacture method of array base palte based on low temperature polycrystalline silicon the most according to claim 1, it is characterised in that described gold
Belonging to layer (20) is titanium or aluminum.
The manufacture method of array base palte based on low temperature polycrystalline silicon the most according to claim 1 and 2, it is characterised in that institute
State elongated slot (300) and be opened in non-display area, and described elongated slot (300) is one, and with the described metal level of non-display area
(20) shape is identical.
The manufacture method of array base palte based on low temperature polycrystalline silicon the most according to claim 1 and 2, it is characterised in that institute
State elongated slot (300) and be opened in non-display area, and described elongated slot (300) is multiple, is disposed on the described of non-display area
On the bearing of trend of metal level (20).
The manufacture method of array base palte based on low temperature polycrystalline silicon the most according to claim 1 and 2, it is characterised in that institute
State elongated slot (300) and be opened in non-display area, and described elongated slot (300) is multiple, and each described elongated slot (300) is with non-display
The shape of the described metal level (20) in region is identical, is disposed side by side on the width of the described metal level (20) of non-display area
On.
6. an array base palte based on low temperature polycrystalline silicon, it is characterised in that be included in non-display area and set the most successively
Insulating barrier (10), metal level (20), flatness layer (30) and the transparency conducting layer (40) put, described flatness layer (30) includes running through it
The elongated slot (300) of thickness direction, described transparency conducting layer (40) includes being formed in described elongated slot (300), is fitted in described gold
Belong to the countersink (400) on layer (20) surface.
Array base palte based on low temperature polycrystalline silicon the most according to claim 6, it is characterised in that described metal level (20) is
Titanium or aluminum.
8. according to the array base palte based on low temperature polycrystalline silicon described in claim 6 or 7, it is characterised in that described elongated slot (300)
It is opened in non-display area, and described elongated slot (300) is one, and the shape phase of the described metal level (20) with non-display area
With.
9. according to the array base palte based on low temperature polycrystalline silicon described in claim 6 or 7, it is characterised in that described elongated slot (300)
It is opened in non-display area, and described elongated slot (300) is multiple, be disposed on the described metal level (20) of non-display area
On bearing of trend.
10. according to the array base palte based on low temperature polycrystalline silicon described in claim 6 or 7, it is characterised in that described elongated slot
(300) it is opened in non-display area, and described elongated slot (300) is multiple, and each described elongated slot (300) and non-display area
The shape of described metal level (20) is identical, is disposed side by side on the width of described metal level (20) of non-display area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610763642.6A CN106206617A (en) | 2016-08-29 | 2016-08-29 | Array base palte based on low temperature polycrystalline silicon and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610763642.6A CN106206617A (en) | 2016-08-29 | 2016-08-29 | Array base palte based on low temperature polycrystalline silicon and preparation method thereof |
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| CN106206617A true CN106206617A (en) | 2016-12-07 |
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| CN201610763642.6A Pending CN106206617A (en) | 2016-08-29 | 2016-08-29 | Array base palte based on low temperature polycrystalline silicon and preparation method thereof |
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Application publication date: 20161207 |