CN106206456B - 一种阵列基板的制作方法、阵列基板及显示装置 - Google Patents
一种阵列基板的制作方法、阵列基板及显示装置 Download PDFInfo
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Abstract
本发明涉及一种阵列基板的制作方法、阵列基板及显示装置,用以解决目前常见的LTPS工艺或其他顶栅结构中制作的遮光层,会在沉积缓冲层时形成段差进而造成各种不良的问题。该方法包括:在衬底基板上形成一整层不透光的膜层;对膜层进行处理,使膜层上形成透光区域和不透光区域;其中,不透光区域与有源层的沟道区域对应;在处理后的膜层上形成薄膜晶体管。本发明的制作方法,在形成薄膜晶体管之前形成一整层不透光的膜层,使其形成透光区域和不透光区域,因而在一整层的膜层上沉积其它膜层时不会出现段差,因而也避免了由于段差而造成的其它各种不良的问题。
Description
技术领域
本发明涉及显示器技术领域,尤其涉及一种阵列基板的制作方法、阵列基板及显示装置。
背景技术
目前,LTPS(Low Temperature Poly-Silicon,低温多晶硅)技术成为了中小尺寸显示行业的主流。在LTPS技术中由于多晶硅对背光较为敏感,因而会采用在底部增加遮光层的方式解决这一问题。现有技术中常利用金属作为LTPS或其他顶栅结构的遮光层,而在形成遮光层的图形时,通常采用刻蚀工艺将多余的遮光金属刻蚀掉,再在遮光层上沉积一定厚度的缓冲层,然后再沉积非晶硅,并将其转换为多晶硅,由于沉积的缓冲层在遮光层的位置处会产生突起,形成段差,进而在制作有源层时,导致准分子激光退火工艺过程中,多晶硅结晶性能变差,甚至造成结晶不良的问题;为了减小缓冲层上的段差,现有技术中通常会增加缓冲层的厚度,但过厚的缓冲层会导致缓冲层与玻璃基板的应力不匹配,造成玻璃弯曲或者膜层脱落等各种不良的问题。
综上所述,目前常见的LTPS工艺或其他顶栅结构中制作的遮光层,会在沉积缓冲层时形成段差,进而影响多晶硅的结晶性能,现有的通过增加缓冲层的厚度减小段差的方式,无法有效的改善结晶不良的问题,甚至还会造成其它各种不良的问题。
发明内容
本发明实施例提供的一种阵列基板的制作方法、阵列基板及显示装置,用以解决目前常见的LTPS工艺或其他顶栅结构中制作的遮光层,会在沉积其它膜层时形成段差进而造成各种不良的问题。
本发明实施例提供的一种阵列基板的制作方法,包括:
在衬底基板上形成一整层不透光的膜层;
对所述膜层进行处理,使所述膜层上形成透光区域和不透光区域;其中,所述不透光区域与有源层的沟道区域对应;
在处理后的膜层上形成薄膜晶体管。
本发明实施例提供的阵列基板的制作方法,在形成薄膜晶体管之前形成一整层不透光的膜层,并对该膜层进行处理,使其形成透光区域和不透光区域,因而后续在一整层的膜层上沉积其它膜层时,不会使其它膜层出现段差,进而也避免了由于段差而造成的其它各种不良的问题。
较佳的,对所述膜层进行处理,使所述膜层上没有与有源层的沟道区域对应的区域透光,具体包括:
在所述膜层上沉积光刻胶;
使用掩膜板对所述光刻胶曝光显影,保留待形成不透光区域对应的光刻胶;
利用保留的光刻胶的遮挡,采用氧化剂对所述膜层上待形成透光区域的膜层进行氧化处理,使得所述待形成透光区域的膜层透光;
剥离所述保留的光刻胶,得到所述膜层上的透光区域和不透光区域。
较佳的,所述氧化剂的材料为双氧水。
较佳的,所述有源层的沟道区域在所述衬底基板上的正投影位于所述不透光区域在所述衬底基板上的正投影内。
较佳的,所述一整层不透光的膜层的材料为钽。
较佳的,在处理后的膜层上形成薄膜晶体管的步骤,具体包括:
在处理后的膜层上沉积非晶硅层,对所述非晶硅层进行准分子激光退火处理,使所述非晶硅层晶化为多晶硅层;
通过一次构图工艺在所述多晶硅层上形成有源层的图形。
本发明实施例提供的一种阵列基板,包括:衬底基板,设置在所述衬底基板上的一整层的膜层和薄膜晶体管;其中,
所述膜层上设置有透光区域和不透光区域,所述不透光区域与有源层的沟道区域对应。
较佳的,所述有源层的沟道区域在所述衬底基板上的正投影位于所述不透光区域在所述衬底基板上的正投影内。
较佳的,所述透光区域的膜层为经过氧化处理后的膜层。
较佳的,所述不透光区域的材料为钽;所述透光区域的材料为钽的氧化物。
较佳的,所述薄膜晶体管为顶栅型结构。
较佳的,所述阵列基板还包括:设置在所述膜层和所述薄膜晶体管之间的缓冲层;所述缓冲层的厚度为1000埃-5000埃。
本发明实施例提供的一种显示装置,所述显示装置包括本发明实施例提供的上述阵列基板。
附图说明
图1为本发明实施例提供的阵列基板的制作方法的流程图;
图2a-图2c分别为本发明实施例提供的阵列基板的制作方法中各步骤执行后的结构示意图;
图2d为本发明实施例提供的制作有源层的图形后的结构示意图;
图3为本发明实施例提供的对一整层不透光的膜层进行处理的方法流程图;
图4a-4c分别为本发明实施例提供的对一整层不透光的膜层进行处理的方法中各步骤执行后的结构示意图;
图5为本发明实施例提供的上述阵列基板的制作方法的整体步骤流程图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅是本发明一部分实施例,并不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
附图中各层薄膜厚度和区域形状大小不反映阵列基板的真实比例,目的只是示意说明本发明内容。
本发明实施例提供的一种阵列基板的制作方法,是在现有阵列基板的制作方法的基础上,对制作遮光层的工艺进行了重新设计优化,改变了现有的遮光层的结构,下面对其具体制作方法进行详细的说明。
本发明实施例提供了一种阵列基板的制作方法,如图1所示,为本发明实施例提供的阵列基板的制作方法的步骤流程图,具体包括以下步骤:
步骤101,在衬底基板上形成一整层不透光的膜层;
步骤102,对膜层进行处理,使膜层上形成透光区域和不透光区域;其中,不透光区域与有源层的沟道区域对应;
步骤103,在处理后的膜层上形成薄膜晶体管。
在本发明实施例提供的上述阵列基板的制作方法中,由于在衬底基板上形成了一整层的遮光膜层,可以避免在遮光膜层上制作其它膜层时出现段差,减少段差带来的不良影响。
目前,常见的LTPS工艺或其他顶栅结构中制作的遮光层,会在沉积缓冲层时形成段差,进而影响多晶硅的结晶性能,现有的通过增加缓冲层的厚度减小段差的方式,无法有效的改善结晶不良的问题,甚至还会造成其它各种不良的问题。
基于此,本发明实施例提供的阵列基板的制作方法,在形成缓冲层之前,形成了一整层不透光的膜层,并对该膜层进行处理,使其形成透光区域和不透光区域,因而在一整层的膜层上沉积缓冲层,不会使缓冲层出现段差,在后续准分子激光退火工艺过程中,也不会影响多晶硅的结晶性能;同时,本发明的方法无需增加缓冲层的厚度就可以有效消除段差对结晶性能的影响,因而也避免了由于缓冲层过厚而造成的其它各种不良的问题。
在具体实施时,在实现上述步骤101时,如图2a所示,先在衬底基板10上形成一整层不透光的膜层20;该不透光的膜层20用于制作阵列基板的遮光膜层。由于形成的一整层不透光的膜层20,必须能够被氧化为透明的膜层,因而该一整层不透光的膜层的材料可以为钽金属。
在具体实施时,在实现上述步骤102时,如图2b所示,对上述形成的一整层的膜层20进行处理,使该膜层上形成透光区域a和不透光区域b;其中,不透光区域b与有源层的沟道区域对应,也就是使图中的两个区域a变为透光区域,而与有源层的沟道区域对应的不透光区域b不进行处理,仍为不透光的形式。
在具体实施时,在实现上述步骤101和102之后,需要执行步骤103,即在处理后的膜层上形成薄膜晶体管;如图2c所示,薄膜晶体管位于膜层20上方,且薄膜晶体管的栅极50位于有源层40上方,为顶栅型的薄膜晶体管。
在具体实施时,在处理后的膜层上形成薄膜晶体管时,还需要在处理后的膜层上沉积缓冲层30,并在缓冲层30上形成薄膜晶体管。较佳的,在执行步骤103时,还包括在缓冲层上制作有源层的步骤,具体制作有源层可以通过下述方式实现:
首先,在处理后的膜层20上沉积一整层的非晶硅层,由于处理后的膜层20上需要先沉积缓冲层再制作有源层,因而实际上是在缓冲层30上沉积一整层的非晶硅层,对非晶硅层进行准分子激光退火处理,使非晶硅层晶化为多晶硅层;然后,再通过一次构图工艺在多晶硅层上形成有源层的图形,如图2d所示,为本发明实施例提供的制作有源层的图形后的结构示意图。
如图3所示,为本发明实施例提供的对一整层不透光的膜层进行处理的方法流程图。具体地,本发明实施例提供的上述阵列基板的制作方法中,较佳的,步骤102对膜层进行处理,具体可以采用如下步骤实现:
步骤1021,在膜层上沉积光刻胶;
步骤1022,使用掩膜板对光刻胶曝光显影,保留待形成不透光区域对应的光刻胶;
步骤1023,利用保留的光刻胶的遮挡,采用氧化剂对膜层上待形成透光区域的膜层进行氧化处理,使得待形成透光区域的膜层透光;
步骤1024,剥离保留的光刻胶,得到膜层上的透光区域和不透光区域。
在具体实施时,首先,如图4a所示,在一整层的不透光膜层上沉积一整层光刻胶60。
其次,如图4b所示,采用掩膜版对上述一整层的光刻胶进行曝光、显影等操作,保留待形成不透光区域对应的光刻胶,保留的这部分光刻胶与有源层的沟道区域对应。
然后,如图4c所示,再利用上述图4b中保留的光刻胶的遮挡,采用氧化剂对不透光的膜层进行氧化处理,使得待形成透光区域的膜层(即两个区域a)变得透光;较佳的,上述氧化剂的材料可以选用为双氧水。
最后,氧化工艺完成以后,剥离保留的光刻胶,如图2b所示,得到氧化处理后的一整层的膜层,且与有源层的沟道区域对应的区域b不透光,而其它没有与有源层的沟道区域对应的区域a透光。
在具体实施时,为了防止不透光区域漏光,如图2c所示,较佳的,有源层的沟道区域c在衬底基板上的正投影位于不透光区域b在衬底基板上的正投影内。具体的,膜层上的不透光区域b的面积,要比有源层的沟道区域c的面积要大,即不透光区域b至少能够完全覆盖有源层的沟道区域c,以防止由于不透光区域的边缘区域透光,而造成有源层上的多晶硅材料受光照后导致性能下降的问题。
为了清楚的说明本发明实施例提供的阵列基板的制作方法,如图5所示,为本发明实施例提供的上述阵列基板的制作方法的整体步骤流程图,包括以下步骤:
步骤501,在衬底基板上形成一整层不透光的膜层;
步骤502,在膜层上沉积光刻胶;
步骤503,使用掩膜板对光刻胶曝光显影,保留待形成不透光区域对应的光刻胶;
步骤504,利用保留的光刻胶的遮挡,采用氧化剂对膜层上待形成透光区域的膜层进行氧化处理,使得待形成透光区域的膜层透光;
步骤505,剥离保留的光刻胶,得到膜层上的透光区域和不透光区域。
步骤506,在处理后的膜层上沉积非晶硅层,对非晶硅层进行准分子激光退火处理,使非晶硅层晶化为多晶硅层;
步骤507,通过一次构图工艺在多晶硅层上形成有源层的图形。
步骤508,在有源层上形成薄膜晶体管的栅极、源漏极。
基于同一发明构思,本发明实施例提供的一种阵列基板,如图2c所示,包括:衬底基板10,设置在衬底基板10上的一整层的膜层20和薄膜晶体管;其中,膜层上设置有透光区域a和不透光区域b,不透光区域b与有源层的沟道区域c对应。
在具体实施时,本发明实施例提供的阵列基板,将遮光层设置为一整层结构、且具有透光区域和不透光区域的膜层,由于是在一整层的膜层上设置的缓冲层,因而不会出现段差的问题,在后续准分子激光退火工艺多晶硅结晶时,可以有效减少段差对结晶效果的影响。同时,由于没有段差,缓冲层的厚度也可以根据需要进行调整,相比于现有技术,可以适当降低缓冲层的厚度,以消除应力造成的其他不利影响,较佳的,该阵列基板还包括:设置在膜层和薄膜晶体管之间的缓冲层;缓冲层的厚度为1000埃-5000埃。
为了不影响显示屏的显示效果,除了与有源层的沟道区域c对应的区域b外,膜层上的其它区域a需要能够透光,较佳的,透光区域(即区域a)的膜层为经过氧化处理后的膜层。在具体实施时,氧化处理可以将不透光的膜层变成透明的氧化物膜层。
在具体实施时,由于钽金属耐高温,且能够转换为透明,因而上述不透光的膜层可以采用钽金属制作,较佳的,不透光区域的材料为钽;透光区域的材料为钽的氧化物。例如,钽金属可以被双氧水氧化为无色透明的钽的氧化物(三氧化二钽或五氧化二钽)。
在具体实施时,为了使缓冲层上不会出现段差,因而本发明实施例提供的阵列基板中设置了一整层结构,且具有透过区域和不透光区域的膜层,而实际上,也可以根据需要不设置完全一整层的膜层,例如,设置至少能够覆盖有源层、且具有透过区域和不透光区域的膜层作为遮光膜层,只要是能够保证在后续准分子激光退火工艺多晶硅结晶时,段差不影响结晶效果即可。
例如,采用半色调掩膜版制作膜层的图形,以及对膜层进行氧化的光刻胶,也可以在不增加掩膜版数量的前提下,制作出至少能够覆盖有源层的膜层、且具有透过区域和不透光区域的遮光膜层。
其中,本发明实施例提供的上述阵列基板主要是针对需要设置遮光层的结构,较佳的,薄膜晶体管为顶栅型结构。由于本发明主要是针对现有技术中的遮光层金属改进,因而需要设置在有遮光层的薄膜晶体管中,如顶栅型结构的薄膜晶体管,或者是低温多晶硅的薄膜晶体管等。
基于同一构思,本发明实施例中还提供了一种显示装置,该显示装置包括本发明实施例中提供的阵列基板,该显示装置可以为:手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。由于该显示装置解决问题的原理与本发明实施例一种阵列基板相似,因此该显示装置的实施可以参见阵列基板的实施,重复之处不再赘述。
综上所述,本发明实施例提供的阵列基板的制作方法,在形成薄膜晶体管之前形成一整层不透光的膜层,并对该膜层进行处理,使其形成透光区域和不透光区域,因而在一整层的膜层上沉积缓冲层,不会使缓冲层出现段差,在后续准分子激光退火工艺过程中,也不会影响多晶硅的结晶性能;同时,本发明的方法无需增加缓冲层的厚度就可以有效消除段差对结晶性能的影响,因而也避免了由于缓冲层过厚而造成的其它各种不良的问题。
显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。
Claims (12)
1.一种阵列基板的制作方法,其特征在于,包括:
在衬底基板上形成一整层不透光的膜层;
对所述膜层进行处理,使所述膜层上形成透光区域和不透光区域;其中,所述不透光区域与有源层的沟道区域对应;
在处理后的膜层上形成薄膜晶体管;
其中,所述对所述膜层进行处理具体为,采用氧化剂对所述膜层进行氧化处理。
2.如权利要求1所述的方法,其特征在于,对所述膜层进行处理,使所述膜层上形成透光区域和不透光区域的步骤,具体包括:
在所述膜层上沉积光刻胶;
使用掩膜板对所述光刻胶曝光显影,保留待形成不透光区域对应的光刻胶;
利用保留的光刻胶的遮挡,采用氧化剂对所述膜层上待形成透光区域的膜层进行氧化处理,使得所述待形成透光区域的膜层透光;
剥离所述保留的光刻胶,得到所述膜层上的透光区域和不透光区域。
3.如权利要求2所述的方法,其特征在于,所述氧化剂的材料为双氧水。
4.如权利要求1所述的方法,其特征在于,所述有源层的沟道区域在所述衬底基板上的正投影位于所述不透光区域在所述衬底基板上的正投影内。
5.如权利要求1所述的方法,其特征在于,所述一整层不透光的膜层的材料为钽。
6.如权利要求1-5任一项所述的方法,其特征在于,在处理后的膜层上形成薄膜晶体管的步骤,具体包括:
在处理后的膜层上沉积非晶硅层,对所述非晶硅层进行准分子激光退火处理,使所述非晶硅层晶化为多晶硅层;
通过一次构图工艺在所述多晶硅层上形成有源层的图形。
7.一种阵列基板,其特征在于,包括:衬底基板,设置在所述衬底基板上的一整层的膜层和薄膜晶体管;其中,
所述膜层上设置有透光区域和不透光区域,所述不透光区域与有源层的沟道区域对应;所述膜层为不透光膜层,所述透光区域是经过对所述膜层氧化处理后得到的区域。
8.如权利要求7所述的阵列基板,其特征在于,所述有源层的沟道区域在所述衬底基板上的正投影位于所述不透光区域在所述衬底基板上的正投影内。
9.如权利要求7所述的阵列基板,其特征在于,所述不透光区域的材料为钽;所述透光区域的材料为钽的氧化物。
10.如权利要求7所述的阵列基板,其特征在于,所述薄膜晶体管为顶栅型结构。
11.如权利要求7-10任一项所述的阵列基板,其特征在于,所述阵列基板还包括:设置在所述膜层和所述薄膜晶体管之间的缓冲层;所述缓冲层的厚度为1000埃-5000埃。
12.一种显示装置,其特征在于,所述显示装置包括权利要求7-11任一项所述的阵列基板。
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103579356A (zh) * | 2012-08-10 | 2014-02-12 | 北京京东方光电科技有限公司 | 一种氧化物tft及其制备方法、显示面板和显示装置 |
CN103592801A (zh) * | 2013-11-19 | 2014-02-19 | 合肥京东方光电科技有限公司 | 顶栅型tft阵列基板及其制造方法、显示面板及显示装置 |
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JP2013037293A (ja) * | 2011-08-10 | 2013-02-21 | Japan Display East Co Ltd | 表示装置及び表示装置の製造方法 |
CN103367165A (zh) * | 2013-07-01 | 2013-10-23 | 北京京东方光电科技有限公司 | 薄膜晶体管及其制作方法、阵列基板及显示器 |
CN104576523A (zh) * | 2013-10-16 | 2015-04-29 | 北京京东方光电科技有限公司 | 一种阵列基板及其制作方法和显示装置 |
CN103545378B (zh) * | 2013-11-05 | 2016-09-07 | 京东方科技集团股份有限公司 | 氧化物薄膜晶体管及其制作方法、阵列基板、显示装置 |
US10083990B2 (en) | 2014-08-29 | 2018-09-25 | Lg Display Co., Ltd. | Thin film transistor substrate and display device using the same |
CN106206456B (zh) * | 2016-08-10 | 2019-08-27 | 京东方科技集团股份有限公司 | 一种阵列基板的制作方法、阵列基板及显示装置 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103579356A (zh) * | 2012-08-10 | 2014-02-12 | 北京京东方光电科技有限公司 | 一种氧化物tft及其制备方法、显示面板和显示装置 |
CN103592801A (zh) * | 2013-11-19 | 2014-02-19 | 合肥京东方光电科技有限公司 | 顶栅型tft阵列基板及其制造方法、显示面板及显示装置 |
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