CN106201973A - A kind of method and system of single wire serial communication interface - Google Patents
A kind of method and system of single wire serial communication interface Download PDFInfo
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- CN106201973A CN106201973A CN201610515190.XA CN201610515190A CN106201973A CN 106201973 A CN106201973 A CN 106201973A CN 201610515190 A CN201610515190 A CN 201610515190A CN 106201973 A CN106201973 A CN 106201973A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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Abstract
The invention discloses the method and system of a kind of single wire serial communication interface, the method is applied to single wire serial communication interface arrangement, described single wire serial communication interface arrangement includes control module, physical layer block, receiver module and sending module, one main frame is communicated from equipment by single wire serial communication interface and one, sends signal including main frame to physical layer block；Signal is synchronized by physical layer block；Control module controls the read-write that receiver module Receiving Host sends, and described read-write includes from device address, read-write mode signals and register address, and read-write is carried out even-odd check；Control module controls sending module and sends read-write to from equipment.The one-wire interface device of the present invention belongs to a line interface, achieve the data exchanging function between equipment simply and easily, provide the selection of a kind of practicality for circuit design engineer, one-wire interface device is greatly reduced area and the number of pin of interface chip, reduces interconnection cost.
Description
Technical field
The present invention relates to serial communication technology field, particularly relate to the method and system of a kind of single wire serial communication interface.
Background technology
Along with the development of society, the life of people come into by increasing electronic equipment, the communication between electronic equipment
More and more frequent, how the interface between selection equipment is particularly important.In the low-speed serial communications field, circuit design engineering
Teacher typically uses the I2C bus that Philips develops.I2C bus belongs to two line interfaces, I2C (Inter-Integrated
Circuit) bus is the twin wire universal serial bus developed by PHILIPS company, is used for connecting microcontroller and ancillary equipment thereof.
It it is the widely used a kind of bus standard in microelectronics Control on Communication field.I2C bus supports that any IC production process is (CMOS, double
Polarity).Information of transmitting it is being connected between the device of bus by serial data (SDA) line and serial clock (SCL) line.Each device
Part has a unique Address Recognition (either microcontroller, lcd driver, memorizer or keyboard interface), and
And can serve as a transmitter or receptor (being determined by the function of device).Lcd driver is only as receptor, and deposits
Reservoir the most not only can receive but also can send data.In addition to transmitters and receivers, device also may be used when performing data transmission
To be counted as main frame or from machine.Main frame is the device that the clock signal allowing transmission was transmitted and produced to the data of initialization bus
Part.Now, any addressed device is considered as from machine.
But the quantity of the area and pin that those skilled in the art are in order to reduce interface chip still makes effort.
Summary of the invention
In order to overcome the deficiencies in the prior art, an object of the present invention is to provide the side of single wire serial communication interface
Method, it can solve the problem that interface chip area is big and number of pin is many.
The two of the purpose of the present invention are to provide the system of single wire serial communication interface, and it is big that it can solve interface chip area
The problem many with number of pin.
An object of the present invention realizes by the following technical solutions:
A kind of method of single wire serial communication interface, is applied to single wire serial communication interface arrangement, and described single serial leads to
Letter interface arrangement includes that control module, physical layer block, receiver module and sending module, a main frame are connect by single wire serial communication
Mouth device and communicates from equipment, comprises the following steps:
S1: control module controls the read-write that receiver module Receiving Host sends, and to the read-write mould in read-write
Formula signal judges, if reading mode, then performs step S2, if WriteMode, then performs step S4, and described read-write is believed
Number also include from device address and the register address from equipment, described from the register address of equipment with corresponding from equipment
Depositor forms one-to-one relationship；
S2: control module control receiver module according to from the register address of equipment from correspondence the depositor from equipment
Read data, then perform step S3；
S3: control module controls sending module and receives the reply read signal from equipment；
S4: control module control receiver module according to from the register address of equipment from correspondence the depositor from equipment
Write data, perform step S5；
S5: control module controls sending module and receives the reply write signal from equipment, described to notify that main frame is successfully written
Write data.
Preferably, comprised the following steps before step S1:
S00: main frame sends synchronizing signal to physical layer block；
S01: synchronizing signal is synchronized by physical layer block, if synchronization failure, then sends synchronization failure to main frame and disappears
Breath, if synchronizing successfully, then performs step S1.The technical problem that physical layer block carries out synchronizing can be solved further.
Preferably, in step sl, described read-write also includes the first parity signal, and receiver module is strange to first
Even parity check signal is tested, if correctly, then transmits even-odd check consequential signal to sending module, if mistake, then goes up
Pass error message to main frame.The technical problem of the even-odd check of read-write can be solved further.
Preferably, in step s3, described reply read signal includes being properly received letter from device address and main frame read command
Number.Can solve further reply read signal concrete signal problem.
Preferably, in step s3, described reply read signal includes the second parity signal, and sending module is strange to second
Even parity check signal is tested, if correctly, then transmits even-odd check consequential signal to main frame, if mistake, then uploads mistake
False information is to main frame.Can solve to reply the technical problem of the even-odd check of read signal further.
Preferably, in step s 5, described reply write signal includes being properly received letter from device address and main frame write order
Number.Can solve to reply the technical problem of the even-odd check of write signal further.
Preferably, in step s 5, described reply write signal includes the 3rd parity signal, and sending module is to the 3rd
Parity signal is tested, if correctly, then transmits even-odd check consequential signal to main frame, if mistake, then uploads
Error message is to main frame.Can solve to reply the technical problem of the even-odd check write letter further.
The two of the purpose of the present invention realize by the following technical solutions:
The system of a kind of single wire serial communication interface, applies the single wire serial communication interface dress of method described above including it
Put, main frame and from equipment, described main frame by single wire serial communication interface arrangement with carry out data communication from equipment.
Preferably, described is multiple from the quantity of equipment.Can solve to arrange from equipment the technical problem of quantity further.
Compared to existing technology, the beneficial effects of the present invention is:
The one-wire interface device of the present invention belongs to a line interface, achieves the data exchange merit between equipment simply and easily
Can, the selection of a kind of practicality is provided for circuit design engineer, one-wire interface device is greatly reduced the face of interface chip
Amass and number of pin, reduce interconnection cost.This device designing technique threshold is low, and debugging is the simplest, additionally, this device is prone to
It is integrated on silicon chip, thus there is good market using value.
Accompanying drawing explanation
Fig. 1 is the flow chart of single wire serial communication interface method of the present invention；
Fig. 2 is the state machine diagram of control module of the present invention；
Fig. 3 is physical layer block state machine diagram of the present invention；
Fig. 4 is receiver module state machine diagram of the present invention；
Fig. 5 is sending module state machine diagram of the present invention；
Fig. 6 is communication structure schematic diagram of the present invention；
Fig. 7 is main frame write order sequential chart of the present invention；
Fig. 8 is that the present invention responds write order sequential chart from equipment；
Fig. 9 is main frame read command sequential chart of the present invention；
Figure 10 is that the present invention responds read command sequential chart from equipment.
Detailed description of the invention
Below, in conjunction with accompanying drawing and detailed description of the invention, the present invention is described further:
As it is shown in figure 1, a kind of method that the invention provides single wire serial communication interface, it is applied to single wire serial communication
Interface arrangement, described single wire serial communication interface arrangement includes control module, physical layer block, receiver module and sending module,
One main frame is communicated from equipment by single wire serial communication interface arrangement and one, comprises the following steps:
S00: main frame sends synchronizing signal to physical layer block；
S01: synchronizing signal is synchronized by physical layer block, if synchronization failure, then sends synchronization failure to main frame and disappears
Breath, if synchronizing successfully, then performs step S1；
S1: control module controls the read-write that receiver module Receiving Host sends, and to the read-write mould in read-write
Formula signal judges, if reading mode, then performs step S2, if WriteMode, then performs step S4, and described read-write is believed
Number also include from device address and the register address from equipment, described from the register address of equipment with corresponding from equipment
Depositor forms one-to-one relationship；Described read-write also includes the first parity signal, and receiver module is to the first odd even
Checking signal is tested, if correctly, then transmits even-odd check consequential signal to sending module, if mistake, then uploads
Error message is to main frame.
S2: control module control receiver module according to from the register address of equipment from correspondence the depositor from equipment
Read data, then perform step S3；
S3: control module controls sending module and receives the reply read signal from equipment；Described reply read signal includes from setting
Standby address and main frame read command are properly received signal；Described reply read signal includes the second parity signal, sending module pair
Second parity signal is tested, if correctly, then transmits even-odd check consequential signal to main frame, if mistake, then
Uploading error message to main frame, it is the confirmation to the first even-odd check result that main frame read command is properly received signal.
S4: control module control receiver module according to from the register address of equipment from correspondence the depositor from equipment
Write data, perform step S5；
S5: control module controls sending module and receives the reply write signal from equipment, described to notify that main frame is successfully written
Write data；Described reply write signal includes being properly received signal from device address and main frame write order.Described reply write signal bag
Including the 3rd parity signal, the 3rd parity signal is tested by sending module, if correctly, then even-odd check is tied
Really signal transmits to main frame, if mistake, then uploads error message to main frame.
The specific works principle of modules state machine of the present invention:
Described sending module, control module, receiver module and physical layer block are parallel relations.Described sending module shape
State machine, control module state machine, receiver module state machine and physical layer block state machine be i.e. can according to control signal according to
State set in advance carries out state transfer, thus coordinates coherent signal action, completes specific operation.
As in figure 2 it is shown, be control module state machine diagram of the present invention, it be defaulted as RECP state (i.e. receiving state), connect
Forward SHFT state (i.e. transfering state) after receipts to, wait that 4 bit week after dates forward TRAN state (i.e. transmission state) to, send out
Forwarding ENDP state (i.e. done state) after sending to, now read-write flow process terminates, and returns RECP state.Control module is as whole
The control action of body, to sending signal, reading signal, send and receive conversion and flow process terminates to carry out overall control.Each shape
State represents a kind of triggering state, when this state is reached, what kind of carries out and controls.
As it is shown on figure 3, be physical layer block state machine diagram of the present invention, it is defaulted as IDLE state (i.e. idle condition),
Forwarding SYN0 state (the i.e. first synchronous regime) after detecting input signal trailing edge to, low level forwards to after continuing for some time
SYN1 state (the i.e. second synchronous regime), (the i.e. the 3rd synchronizes shape to detect the SYN2 state that forwards to after high level continues for some time
State), detect the SYN3 state that forwards to after low level continues for some time (the i.e. the 4th synchronous regime), synchronize successfully, above-mentioned be i.e.
First two steps in method step, synchronize synchronizing signal, and about 1 bit week after date forwards DATA state to and (i.e. receives data
State), forward ENDP state after receiving to, now receive flow process and terminate, return IDLE state.If stopped in SYN1 state
Overlong time, then report error (i.e. mistake), return IDLE state
As shown in Figure 4, for receiver module state machine diagram of the present invention, it is defaulted as sync state (i.e. synchronous regime), thing
When reason layer state machine is SYN2 state (the 3rd synchronous regime), receiver module forwards SRCE state (reception state) to, receives form
Host (from main frame) read-write, forwards DEVC state (reception state) to after 1 signal period, receive and believe from device address
Number, after 2 signal periods, if ours then forwards PARI state to from device address signal, if it is not, then forward ENDP to
State, PARI state (i.e. parity state) receives parity signal, forwards MODE state (i.e. mould after 1 signal period to
Formula state), receive read/write signal, forward ANTI state (i.e. antilogical state) after 1 signal period to, after 1 signal period
Forward ADDR state (i.e. address reception state) to, receive 8bits register address, if reading mode turns after 9 signal periods
To ENDP state, if WriteMode then forwards WDAT state (i.e. writing data mode) to, WDAT state receives 8bits and writes data, and 9
Forward ENDP state (done state) after the individual signal period to, now receive flow process and terminate, return sync state (synchronous regime).This
Concrete implementation mode for S3.
As it is shown in figure 5, be sending module state machine diagram of the present invention, it is defaulted as IDLE state (idle condition), controls
Module status machine forwards to during TRAN (transmission state), and when sending preparation, sending module forwards sync state (synchronous regime) to,
Forward SRCE (extraction state) after sending 3bits synchronous code to, forward to after sending 1bits from device (since equipment)
ADDR state (address state), sends 2bits and forwards PARI state (parity state) behind device address to, sends 1bit and connects
Forward CHEK state (i.e. checking state) after receiving the even-odd check result of module to, after sending 1bit even-odd check, forward ANTI shape to
State, after sending 1bit antilogical signal, if responding write order, then forwarding ENDP state to, if responding read command, then forwarding to
RDAT state (i.e. reads data mode), after sending 8bits reading data and 1bit antilogical signal, forwards ENDP state to and (terminates shape
State), transmission flow terminates, and returns IDLE state (idle condition).This is the concrete implementation mode of S3 and S5.
As shown in Figure 6, for communication structure schematic diagram of the present invention, wherein sda is data signal line, present invention also offers one
The system of kind of single wire serial communication interface, including single wire serial communication interface arrangement, main frame (host) and from equipment (device),
Main frame sends signal to single wire serial communication interface arrangement, extracts read-write from equipment from single wire serial communication interface arrangement.
Wherein, described from the quantity of equipment be four.
In the present embodiment with register address D8h and write data 75h to main frame write order and from equipment respond write life
Order is explained in detail.Aforesaid method is based on single wire serial communication interface arrangement, carries out its communication process in detail
Thin elaboration, Fig. 7 and Fig. 8 is that also Fig. 9 and Figure 10 reads life by main frame by main frame write order with from equipment response write order
Make and respond read command from equipment and communication mechanism is specifically described.
As it is shown in fig. 7, main frame write order sequential chart of the present invention, front 3 bit of first phase (the first phase) are sync
Code (synchronous code) 010b, the 4th bit is from host (main frame) (0b) mark, and the 5th and the 6th bit is device
Address (from device address) (00b, 01b, 10b, 11b), the 7th bit is parity check bit, by register address
(register address) and write data (writing data) totally 16 bit calculate, and the 8th bit is write (0b) (writing data)
Mark, the 9th bit is reverse (1b) of the 8th bit.Second phase (the second phase) represents 8bits register
Address (register address), wherein the 5th bit is the reverse of the 4th bit.Third phase (third phase) represents 8bits
Write data (writes data), and wherein the 5th bit is the reverse of the 4th bit.
As shown in Figure 8, the present invention responds write order sequential chart, front 3 bit of first phase (the first phase) from equipment
For sync code (synchronous code) 010b, the 4th bit is from device (1b) (from equipment) mark, and the 5th and the 6th bit is
Device address (i.e. from device address) (00b, 01b, 10b, 11b), the 7th bit are that Host (main frame) write order is correct
The mark received, the 8th bit is parity check bit, is set to 0b, and the 9th bit is reverse (1b) of the 8th bit.
As it is shown in figure 9, main frame read command sequential chart of the present invention, front 3 bit of first phase are sync code
010b, the 4th bit are from host (0b) mark, the 5th and the 6th bit be device address (00b, 01b, 10b,
11b), the 7th bit is parity check bit, register address totally 8 bit calculate, and the 8th bit is read
(1b) mark, the 9th bit is reverse (0b) of the 8th bit.Second phase represents 8bits register address,
Wherein the 5th bit is the reverse of the 4th bit.
As shown in Figure 10, the present invention responds read command sequential chart from equipment, and front 3 bit of first phase are sync
Code 010b, the 4th bit are from device (1b) mark, the 5th and the 6th bit be device address (00b,
01b, 10b, 11b), the 7th bit is the mark that Host read command is properly received, and the 8th bit is parity check bit, by read
Data totally 8 bit calculate, and the 9th bit is the reverse of the 8th bit.Second phase represents 8bits read
Data, wherein the 5th bit is the reverse of the 4th bit.
It will be apparent to those skilled in the art that can technical scheme as described above and design, make other various
Corresponding change and deformation, and all these change and deformation all should belong to the protection domain of the claims in the present invention
Within.
Claims (9)
1. the method for a single wire serial communication interface, it is characterised in that be applied to single wire serial communication interface arrangement, described list
Line serial communication interface device includes control module, physical layer block, receiver module and sending module, and a main frame passes through single line string
Row communication interface and one communicates from equipment, comprises the following steps:
S1: control module controls the read-write that receiver module Receiving Host sends, and believes the read-write mode in read-write
Number judging, if reading mode, then perform step S2, if WriteMode, then performing step S4, described read-write is also
Including from device address and the register address from equipment, described from the register address of equipment and corresponding depositing from equipment
Device forms one-to-one relationship；
S2: control module controls receiver module and reads from the corresponding depositor from equipment according to from the register address of equipment
Read data, then perform step S3；
S3: control module controls sending module and receives the reply read signal from equipment；
S4: control module controls receiver module and writes from the corresponding depositor from equipment according to from the register address of equipment
Write data, perform step S5；
S5: control module controls sending module and receives the reply write signal from equipment, to notify that main frame writes number described in being successfully written
According to.
2. the method for single wire serial communication interface as claimed in claim 1, it is characterised in that included following before step S1
Step:
S00: main frame sends synchronizing signal to physical layer block；
S01: synchronizing signal is synchronized by physical layer block, if synchronization failure, then sends synchronization failure message to main frame, as
Fruit synchronizes successfully, then perform step S1.
3. the method for single wire serial communication interface as claimed in claim 1, it is characterised in that in step sl, described read-write
Signal also includes the first parity signal, and the first parity signal is tested by receiver module, if correctly, then and will be strange
Even parity check consequential signal transmits to sending module, if mistake, then uploads error message to main frame.
4. the method for single wire serial communication interface as claimed in claim 1, it is characterised in that in step s3, described reply
Read signal includes being properly received signal from device address and main frame read command.
5. the method for single wire serial communication interface as claimed in claim 1, it is characterised in that in step s3, described reply
Read signal includes the second parity signal, and the second parity signal is tested by sending module, if correctly, then and will be strange
Even parity check consequential signal transmits to main frame, if mistake, then uploads error message to main frame.
6. the method for single wire serial communication interface as claimed in claim 1, it is characterised in that in step s 5, described reply
Write signal includes being properly received signal from device address and main frame write order.
7. the method for single wire serial communication interface as claimed in claim 1, it is characterised in that in step s 5, described reply
Write signal includes the 3rd parity signal, and the 3rd parity signal is tested by sending module, if correctly, then and will be strange
Even parity check consequential signal transmits to main frame, if mistake, then uploads error message to main frame.
8. the system of a single wire serial communication interface, it is characterised in that include being applied to method described in claim 1-7
Single wire serial communication interface arrangement, main frame and from equipment, described main frame is entered with from equipment by single wire serial communication interface arrangement
Row data communication.
9. the system of single wire serial communication interface as claimed in claim 8, it is characterised in that described is many from the quantity of equipment
Individual.
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| CN201610515190.XA CN106201973B (en) | 2016-06-30 | 2016-06-30 | Method and system for single-wire serial communication interface |
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| CN201610515190.XA CN106201973B (en) | 2016-06-30 | 2016-06-30 | Method and system for single-wire serial communication interface |
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| CN107748805A (en) * | 2017-09-06 | 2018-03-02 | 芯海科技（深圳）股份有限公司 | A kind of one-wire interface technology for ICD |
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| CN109902046A (en) * | 2019-02-01 | 2019-06-18 | 福瑞泰克智能***有限公司 | A kind of communication means, relevant device and system for Serial Peripheral bus system |
| CN110737622A (en) * | 2019-10-15 | 2020-01-31 | 上海智汇电器有限公司 | single-wire bidirectional communication charging method |
| CN112564882A (en) * | 2020-11-26 | 2021-03-26 | 北京工业大学 | Single-wire digital communication interface based on AHB bus |
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| CN110737622A (en) * | 2019-10-15 | 2020-01-31 | 上海智汇电器有限公司 | single-wire bidirectional communication charging method |
| CN110737622B (en) * | 2019-10-15 | 2021-05-07 | 上海智汇电器有限公司 | Single-wire bidirectional communication charging method |
| CN112564882A (en) * | 2020-11-26 | 2021-03-26 | 北京工业大学 | Single-wire digital communication interface based on AHB bus |
| CN112564882B (en) * | 2020-11-26 | 2023-06-20 | 北京工业大学 | Single-wire digital communication interface based on AHB bus |
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