CN106169428B - Chip-packaging structure for slowing down electromagnetic interference and packaging method - Google Patents
Chip-packaging structure for slowing down electromagnetic interference and packaging method Download PDFInfo
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- CN106169428B CN106169428B CN201610779283.3A CN201610779283A CN106169428B CN 106169428 B CN106169428 B CN 106169428B CN 201610779283 A CN201610779283 A CN 201610779283A CN 106169428 B CN106169428 B CN 106169428B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The present invention discloses a kind of chip-packaging structure and its packaging method for slowing down electromagnetic interference, by making subsidence trough on a silicon substrate, and chip front side weld pad is embedded to subsidence trough upward, save encapsulated space, by the inductance wiring for forming horizontal arrangement or vertical arrangement in chip front side and silicon substrate first surface, and horizontal arrangement or the capacitance wiring of vertical arrangement are formed on the first insulating layer, first metal reroutes or the second metal reroutes and soldered ball extends on silicon substrate, it realizes and chip pad is electrically fanned out into silicon substrate, improve package reliability, it is simple for process, it is at low cost；Horizontal arrangement or the wiring of the inductance of vertical arrangement constitute inductance, and the capacitance wiring of horizontal arrangement or vertical arrangement and dielectric layer therebetween constitute capacitance, inductance and capacitance with filtering characteristic can slow down the crosstalk of signal between chip interior circuit, filter out unwanted electric signal, enhance the reliability and performance of encapsulating products, while reducing cost.
Description
Technical field
The present invention relates to a kind of field of semiconductor package, more particularly, to a kind of chip package for slowing down electromagnetic interference
Structure and packaging method.
Technical background
Chip needs to carry out surface mount printed circuit board after completing level package, connects other elements, realizes its function.
Electronic Packaging miniaturization, high density, multi-functional development trend, elements on circuit board quantity is followed to increase, adjacent elements spacing
From shortening, the probability of interelement generation radiation interference is substantially improved when circuit works, and line impedance mismatches and circuit noise
Phenomenon increases, and influences signal and transmits quality.
Under normal circumstances, wiring board reduces the influence of above-mentioned phenomenon using embedded set capacitance, inductance.Reducing encapsulating face
Product, while improving the integrated level of potted element, can also slow down has larger challenge in electromagnetic interference.
Invention content
The present invention is to meet above-mentioned challenge, provides a kind of chip-packaging structure and its encapsulation for slowing down electromagnetic interference
Method passes through direct stack capacitor, inductance or horizontal arrangement capacitance, inductance on a single chip on single-chip vertical direction, contracting
Small package area, improves the integrated level of potted element.
Specific implementation is as follows：
It is a kind of for slowing down the chip-packaging structure of electromagnetic interference, including silicon substrate and chip, the silicon substrate has the
It is recessed to be formed at least one sinking towards second surface on the first surface for one surface and second surface corresponding thereto
Slot, at least one chip back mount the slot bottom to the subsidence trough downward, and the chip front side includes weld pad；Institute
It states between chip side and the subsidence trough side wall, be formed with the first insulation on the chip front side and the first surface
Layer；It is formed with the inductance wiring of horizontal arrangement or vertical arrangement on first insulating layer, and is formed on first insulating layer
There are horizontal arrangement or the capacitance wiring of vertical arrangement, is also formed on first insulating layer and electrically exports the chip pad
Metal reroute, inductance wiring, the capacitance wiring and the chip weld pad be electrically connected.
Further, the rewiring of the first metal, the wiring of the first inductance, the first capacitance cloth are formed on first insulating layer
Line, first metal reroute the weld pad that the chip is electrically connected through first insulating layer, the first metal weight cloth
Line, first inductance connect up, are formed with second insulating layer on first capacitance wiring, are formed in the second insulating layer
Second metal reroutes, the wiring of the second inductance and the second capacitance wiring, second metal are rerouted through second insulation
Layer is electrically connected first metal and reroutes, between each circuit of the first inductance wiring, second inductance wiring it is each
Between circuit, first inductance wiring circuit and second inductance wiring circuit between by broken line mode continuously around
Row is connected up at inductance, and parallel between each circuit or close to parallel, between first capacitance wiring and second capacitance wiring
Equipped with dielectric layer；Second metal reroutes, second inductance connects up, is covered with protection on second capacitance wiring
Layer, an at least circuit extends on the silicon substrate outside the chip area during second metal reroutes.
Further, be formed on first insulating layer the first metal reroute, the wiring of the first inductance for continuously detouring,
Middle ware is separated at least two first capacitance wirings of dielectric layer, and first metal reroutes, the first inductance wiring and the
One capacitance wiring is electrically connected the weld pad of the chip through first insulating layer；The first metal rewiring, described first
Protective layer is covered in inductance wiring, first capacitance wiring, an at least circuit prolongs during first metal reroutes
It reaches on the silicon substrate outside the chip area.
Further, first capacitance wiring and the second capacitance wiring are the identical metal derby of size.
Further, first insulating layer and the material of the second insulating layer are polymer latex.
Further, second metal reroutes the soldered ball/salient point being connected with through the protective layer.
Further, the chip back is attached to the slot bottom of the subsidence trough by cohering sticker, the glue that coheres
Thickness is less than 50 microns, is more than 1 micron.
Further, the number of chips for being embedded to same subsidence trough is more than or equal to 2.
Further, the thickness that first metal reroutes is more than 0.2 micron.
A kind of packaging method for slowing down the chip-packaging structure of electromagnetic interference includes the following steps：
A., one second surface silicon substrate disc with first surface and corresponding thereto is provided, is formed on the first surface
There are at least one subsidence trough towards second surface, at least one chip back to mount the slot to the subsidence trough downward
Bottom, the chip front side is concordant with the silicon substrate first surface or close to concordantly, and the chip front side includes weld pad；
B. between the chip side and the subsidence trough side wall, the chip front side and the first surface upper berth
If one layer of first insulating layer；
C. the rewiring of the first metal, the wiring of the first inductance and the first capacitance wiring, institute are formed on first insulating layer
It states the first metal and reroutes the weld pad for being electrically connected the chip through first insulating layer；
D. it reroutes in first metal, first inductance wiring, be laid with one layer the on first capacitance wiring
Two insulating layers；
E. the rewiring of the second metal, the wiring of the second inductance and the second capacitance wiring, institute are formed in the second insulating layer
The second metal is stated to reroute through second insulating layer electrical connection the first metal rewiring, the second inductance wiring
The excessively described second insulating layer of partial line Reuter is electrically connected the part circuit of the first inductance wiring, and first inductance is made to connect up
And the second inductance wiring constitutes the inductance wiring continuously detoured, and make an at least line in the second metal rewiring
Road extends on the silicon substrate outside the chip area；
F. one layer of guarantor of covering on second metal rewiring, second inductance wiring, second capacitance wiring
Sheath；
G. the position formation protective layer opening done salient point or plant soldered ball is reserved in second metal rewiring, and at this
Protective layer opening forms soldered ball or salient point；
H. scribing is carried out to silicon substrate disc, forms the chip-packaging structure that monolithic is used to slow down electromagnetic interference.
The advantageous effects of the present invention are as follows：The present invention is used to slow down chip-packaging structure and its encapsulation of electromagnetic interference
Method is embedded to subsidence trough, in this way, saving upward by making subsidence trough on a silicon substrate, and by chip front side weld pad
Encapsulated space, and silicon substrate can make forming fine wiring, vertically be set by being formed in chip front side and silicon substrate first surface
The inductance/capacitance structure set, i.e. the first metal reroute and the second metal reroutes, the first inductance connects up and the second inductance cloth
Line, the first capacitance wiring and the second capacitance wiring, the second metal reroute and soldered ball extend on silicon substrate, realize by
Chip pad electrically fans out to silicon substrate, improves package reliability, simple process and low cost；First inductance connect up and
The wiring of second inductance constitutes inductance wiring, the first capacitance wiring and the second capacitance wiring and constitutes capacitance wiring, with filtering
The inductance and capacitance of characteristic can slow down the crosstalk of signal between chip interior circuit, filter out unwanted electric signal；Or in core
Horizontally disposed inductance/capacitance structure is formed on piece front and silicon substrate first surface, i.e., is rerouted same with the first metal
The the first inductance wiring of plane continuously detoured and middle ware are separated at least two first capacitance wirings of dielectric layer, to drop
The crosstalk of signal between low chip interior circuit, enhances the reliability and performance of encapsulating products, while reducing cost.
Description of the drawings
Fig. 1 is the diagrammatic cross-section that silicon substrate of the present invention is embedded to chip；
Fig. 2 is that the present invention forms the first insulating layer and makes the diagrammatic cross-section of insulating layer openings；
Fig. 3 is that whole face deposits the diagrammatic cross-section after the first seed layer to the present invention on the first insulating layer；
Fig. 4 is the diagrammatic cross-section of present invention coating photoresist in the first seed layer；
Fig. 5 is that the present invention carves to form the rewiring of the first metal, the wiring of the first inductance and the first electricity in the first seed layer glazing
Hold the diagrammatic cross-section of wiring；
Fig. 6 is that the present invention forms second insulating layer on the first metal line and makes the section signal of insulating layer openings
Figure；
Fig. 7 is that whole face deposits the diagrammatic cross-section after second of sublayer to the present invention over the second dielectric；
Fig. 8 is the diagrammatic cross-section of present invention coating photoresist in second of sublayer；
Fig. 9 is that the present invention carves to form the rewiring of the second metal, the wiring of the second inductance and the second electricity in second of sublayer glazing
Hold the diagrammatic cross-section of wiring；
Figure 10 is that the present invention forms protective layer on the second metal line and makes the diagrammatic cross-section of protective layer opening；
Figure 11 is that the present invention forms the diagrammatic cross-section (dotted line cutaway along Figure 12) after soldered ball；
Figure 12 is the stereoscopic schematic diagram of 1 vertical structure inductance capacitance of the embodiment of the present invention；
Figure 13 is the diagrammatic cross-section of 2 horizontal structure inductance capacitance of the embodiment of the present invention；
Figure 14 is the schematic top plan view of 2 horizontal structure inductance capacitance of the embodiment of the present invention；
In conjunction with attached drawing, make the following instructions：
1 --- silicon substrate 101 --- first surface
102 --- second surface 103 --- grooves
2 --- chip 201 --- weld pads
3 --- cohere glue
4 --- the first insulating layer 401 --- first insulating layer openings
5 --- the first seed layer 501 --- first metals reroute
502 --- the first inductance wiring 503 --- first capacitance wirings
6 --- photoresist 7 --- second insulating layers
701 --- second insulating layer opening 8 --- second of sublayer
Second inductance connects up 801 --- the second metal reroutes 802 ---
803 --- the second capacitance wiring 9 --- photoresists
10 --- protective layer 1001 --- protective layers are open
11 --- soldered ball/salient point
Specific implementation mode
In order to be more clearly understood that the technology contents of the present invention, spy are lifted following embodiment and are described in detail, purpose is only
It is to be best understood from the protection domain that present disclosure is not intended to limit the present invention.Each component part in the structure of embodiment attached drawing
Normal rates are not pressed to scale, therefore do not represent the practical relative size of each structure in embodiment.Wherein described structure or face is upper
Face or upside, including intermediate also have other layer of the case where.
Embodiment 1
As is illustrated by figs. 11 and 12, a kind of chip-packaging structure for slowing down electromagnetic interference, including silicon substrate 1 and chip
2, the silicon substrate has first surface 101 and second surface 102 corresponding thereto, and at least one is formed on the first surface
A subsidence trough 103 towards second surface, the subsidence trough be preferably straight trough or side wall with bottom surface angle 80~120 it is oblique
Slot is not limited here.The present embodiment schematic diagram is straight trough shape.An at least chips 2 can be placed in the subsidence trough, this
To placed a chips in embodiment, and the chip front side is close to the first surface；Specifically, the chip back is logical
It crosses and coheres the attachment of glue 3 to the slot bottom of the subsidence trough, realize the attachment of chip, with better fixed chip, prevent chip inclined
It moves.The chip front side includes weld pad 201；Between the chip side and the subsidence trough side wall, the chip front side
And the first insulating layer 4 is formed on the first surface；It is formed with the first metal on first insulating layer and reroutes 501, the
One inductance connects up the 502, first capacitance wiring 503, and first metal is rerouted through described in first insulating layer electrical connection
The weld pad of chip, first metal reroutes, first inductance connects up, second is formed on first capacitance wiring absolutely
Edge layer 7 is formed with the second metal in the second insulating layer and reroutes the wiring 802 of the 801, second inductance and the second capacitance wiring
803, second metal is rerouted is electrically connected the first metal rewiring, first inductance through the second insulating layer
Between each circuit of wiring, between each circuit of second inductance wiring, the circuit of first inductance wiring and described the
It is continuously detoured by broken line mode between the circuit of two inductance wiring and is connected up at inductance, and is parallel between each circuit or close to parallel,
Referring between the first capacitance wiring described in Figure 12 and second capacitance wiring be equipped with dielectric layer；First inductance wiring and second
Inductance wiring constitutes inductance wiring, the first capacitance wiring and the second capacitance wiring and constitutes capacitance wiring；Inductance wiring, capacitance
Wiring and the weld pad of chip are electrically connected；Second metal reroutes, second inductance connects up, second capacitance wiring
On be covered with protective layer 10, an at least circuit extends to the silicon substrate outside the chip area during second metal reroutes
In plate surface；Second metal reroutes the soldered ball/salient point 11 being connected with through the protective layer.
Preferably, the first capacitance wiring and the second capacitance wiring are the identical metal derby of size.
Preferably, the distance between the side wall of the subsidence trough and the chip are more than 1 micron, to facilitate chip to be put into
The slot bottom of subsidence trough.
Preferably, the distance between the slot bottom of the subsidence trough and the second surface of the silicon substrate are more than 1 micron, with
Support conducive to silicon substrate to chip.
Preferably, first insulating layer and the material of the second insulating layer are polymer latex.To improve packaging body
Reliability, addition of vacuum coating makes to fill the full polymer latex in subsidence trough the gap in, with fixed chip, while ensure absolutely
Edge performance.
Preferably, the glue that coheres is non-conductive polymer glue or film, and adhering chip ensures in the slot bottom of subsidence trough
In next technique, chip position does not shift, and in order to obtain preferable alignment precision, acquisition is thinner to be connected up again
Lines.Polymer latex can be by preparing in chip die backsize mode, and film can be by pressing at the chip die back side
It is prepared by film mode.
Optionally, between the wiring of the first inductance and the first capacitance wiring or the wiring of the second inductance and the second capacitance wiring, root
It can connect or be not connected to according to encapsulated circuit design.
As a kind of preferred embodiment, as shown in figure 12, for the wiring of the first inductance and the wiring of the second inductance it is upper and lower it is parallel around
Row, and extend in parallel in the horizontal direction.In other embodiment, as long as the wiring of the first inductance and the second inductance connect up to unroll
Row, when electric current changes in inductance wiring, the magnetic field of surrounding also generates respective change.
The present embodiment is the assembled package structure of the inductance wiring and the capacitance wiring of vertical arrangement of vertical arrangement, can be compared with
Good is applied to the larger application scenario of inductance, capacitance.
As a kind of preferred embodiment, for slow down electromagnetic interference chip-packaging structure manufacturing method as follows
Implement：
Step 1. provides a 102 silicon substrate disc of second surface with first surface 101 and corresponding thereto referring to Fig. 1,
At least one subsidence trough 103 towards second surface is formed on the first surface, 2 back side of at least one chip is pasted downward
It is attached to the slot bottom of the subsidence trough, the chip front side is concordant with the silicon substrate first surface or close concordant, the core
Piece front includes weld pad 201；
Optionally, the chip is cohered with the subsidence trough slot bottom by cohering glue 3 or dry film.More preferably, glue is cohered
Or dry film is non-conductive polymer glue or film, adhering chip and subsidence trough bottom surface.
Preferably, the shape of the subsidence trough can be trapezoidal, rectangle or other geometries.
Step 2. is referring to Fig. 2, by coating or press mold technique, forms one layer of covering chip side wall and the sinking is recessed
The first surface in gap, the silicon substrate disk between slot and the first insulating layer 4 of the chip front side, and described first
Correspond at the pad locations of chip the first insulating layer openings 401 of making on insulating layer, the positive weld pad of exposed chip 201；
Optionally, the material of first insulating layer is one kind in silica, silicon nitride, insulating material of polymer.
Preferably, the preparation of first insulating layer is deposited using low temperature chemical vapor or polymer sprays or polymer rotation
The method of painting.
Optionally, it is one kind in etching, cutting to allow the mode that the weld pad of chip exposes, when the material of the first insulating layer
When matter is photoactive material, the weld pad of chip can be made to be exposed by photoetching process, photoetching process includes mainly photoresist
Coating, exposure, the operations such as development.In the present embodiment, the weld pad of chip is set to be exposed by exposure imaging.
Step 3. forms the first metal on first insulating layer and reroutes the 501, first inductance wiring 502 and the first electricity
Hold wiring 503, first metal reroutes the weld pad that the chip is electrically connected through first insulating layer.
Specifically, as shown in figure 3, whole face deposits the side that the first seed layer 5 forms the first seed layer on the first insulating layer
Formula can be physical vapor deposition.The material of first seed layer can be in Ni/Au, CrW/Cu, Ti/W/Cu/Ni/Au, Ti/Cu
One kind.
As shown in figure 4, the coating photoresist 6 in the first seed layer, and preset first gold medal is exposed by photoetching process
Belong to rewiring, the first inductance connects up, the line pattern of the first capacitance wiring.Photoetching process includes mainly the coating of photoresist 6, exposes
The operations such as light, development.
As shown in figure 5, forming metallic circuit by being electroplated or changing plating mode on the line pattern exposed, finally remove
Seed layer outside line pattern forms the rewiring of the first metal, the wiring of the first inductance, the first capacitance wiring.
Optionally, the first metal reroute, the first inductance wiring, the first capacitance wiring, material type include titanium, chromium, tungsten,
One or more of copper, aluminium.
Preferably, the rewiring of the first metal is formed, the first inductance connects up, the method for the first capacitance wiring is vacuum evaporation
One kind in method, physical vaporous deposition.It has been laid with one layer in the present embodiment, has been physical vapour deposition (PVD) by the way of, then
It is formed using wet etching, other embodiment can be laid with multilayered structure.The material of every layer of structure be aluminium, nickel, nickel phosphorus, silver, copper,
One kind in cobalt, gold, palladium.More preferably, outermost metal is the metal for having anti-oxidation effect, such as one kind in silver, gold, palladium.
Preferably, the thickness that first metal reroutes is more than 0.2 micron.The thickness is that the first metal of enhancing reroutes
The preferred forms for the reliability being connect with weld pad, naturally it is also possible to be other thickness.
Step 4. is formed one layer of covering first metal and is rerouted, is described referring to Fig. 6 by coating or press mold technique
Second insulating layer 7 in the wiring of first inductance, first capacitance wiring, and in first metal rewiring, the first inductance
Second insulating layer opening is made at wiring.The material of the second insulating layer can be polymeric media material, and material can be with the
One insulating layer material is identical.
Preferably, the dielectric constant of the second insulating layer material is determined according to the inductance, the capacitance that are embedded to；
Preferably, the thickness of the second insulating layer is determined according to the capacitance of embedment, inductive nature and shape.
Step 5. forms the second metal in the second insulating layer and reroutes the 801, second inductance wiring 802 and the second electricity
Holding wiring 803, second metal, which is rerouted, to be electrically connected first metal through the second insulating layer and reroutes, and described the
The excessively described second insulating layer of partial line Reuter of two inductance wiring is electrically connected the part circuit of the first inductance wiring, makes first
Inductance wiring and the wiring of the second inductance constitute continuous detour and are connected up at inductance, and make at least one in the second metal rewiring
Circuit extends on the silicon substrate outside the chip area.Specifically, referring to Fig. 7, Fig. 8, Fig. 9 (with Fig. 3 to Fig. 5's
Making step is the same), as shown in fig. 7, making at least one layer of connection the first metal weight cloth on the second insulating layer
Second of sublayer 8 of line and the wiring of the first inductance；
As shown in figure 8, forming polymer latex in second of sublayer, and the second metal weight is formed by photoetching process
It connects up, the second inductance connects up, the line pattern of the second capacitance wiring.Photoetching process includes the coating of photoresist 9, is exposed, development
Deng operation.As shown in figure 9, being formed on line pattern, the second metal reroutes, the second inductance connects up and the second capacitance wiring.
Preferably, it is identical that the material that second metal reroutes can reroute material with the first metal.
Step 6. is referring to Figure 10 and Figure 11, the upper system on the rewiring of the second metal, the wiring of the second inductance, the second capacitance wiring
Make protective layer 10, and reserve the position formation protective layer opening 1001 done salient point or plant soldered ball on it, and is opened in the protective layer
Conductive structure (soldered ball or salient point) is formed at mouthful；
Optionally, the material of the protective layer is polymer latex, and material can be with the first insulating layer and second insulating layer material
Matter can be identical.
Step 7. carries out scribing to silicon substrate disc, forms the chip-packaging structure that monolithic is used to slow down electromagnetic interference.
Embodiment 2
As shown in Figure 13 and Figure 14, a kind of chip-packaging structure for slowing down electromagnetic interference, including silicon substrate 1 and chip
2, silicon substrate has first surface 101 and second surface 102 corresponding thereto, and at least one direction the is formed on first surface
The subsidence trough 103 on two surfaces, at least one chip back mount the slot bottom to the subsidence trough downward, and chip front side includes
There is weld pad 201；The first insulating layer 4 is formed between chip side and subsidence trough side wall, on chip front side and first surface；The
It is formed with that the first metal reroutes 501, the first inductance for continuously detouring wiring 502, middle ware is separated with dielectric on one insulating layer
At least two first capacitance wirings 503 of layer, the first metal reroutes, the wiring of the first inductance and the first capacitance wiring penetrate first
Insulating layer is electrically connected the weld pad of chip；First metal reroutes, the first inductance connects up, is covered with protective layer on the first capacitance wiring
10, an at least circuit extends on the silicon substrate outside chip area during the first metal reroutes；First metal
Soldered ball/salient point 11 through the protective layer is connected in rewiring.
Optionally, the wiring of the first inductance and the first capacitance wiring can be connected or are not connected to according to encapsulated circuit design.
The present embodiment is the assembled package structure of the inductance wiring and the capacitance wiring of horizontal arrangement of horizontal arrangement, can be compared with
Good is applied to the smaller application scenario of inductance, capacitance.
In other embodiments, the inductance wiring of chip surface and capacitance wiring can also be vertical structure and horizontal structure
Combination, for example, the wiring of vertical inductance and horizontal capacitance wiring assembled package, or the wiring of horizontal inductance and vertical electricity
Hold wiring combination encapsulation.
To sum up, the present invention is used to slow down the chip-packaging structure and its packaging method of electromagnetic interference, by a silicon substrate
Subsidence trough is made, and chip front side weld pad is embedded to subsidence trough upward, in this way, encapsulated space is saved, and silicon substrate can
To make forming fine wiring, by being formed with horizontal arrangement or the inductance of vertical arrangement in chip front side and silicon substrate first surface
Wiring, and is formed with horizontal arrangement or the capacitance wiring of vertical arrangement on first insulating layer, the first metal reroutes or the
Two metals reroute and soldered ball extends on silicon substrate, realize chip pad electrically fanning out to silicon substrate, carry
High package reliability, simple process and low cost；Horizontal arrangement or the wiring of the inductance of vertical arrangement constitute inductance, and horizontal row
The capacitance wiring of cloth or vertical arrangement and therebetween dielectric layer constitute capacitance, and inductance and capacitance with filtering characteristic can slow down
The crosstalk of signal between chip interior circuit, filters out unwanted electric signal, enhances the reliability and performance of encapsulating products, simultaneously
Reduce cost.
Above example is with reference to attached drawing, to a preferred embodiment of the present invention will be described in detail.Those skilled in the art
Member by above-described embodiment carry out various forms on modification or change, but without departing substantially from the present invention essence in the case of, all
It falls within the scope and spirit of the invention.
Claims (10)
1. a kind of chip-packaging structure for slowing down electromagnetic interference, which is characterized in that including silicon substrate (1) and chip (2), institute
The second surface (102) of silicon substrate with first surface (101) and corresponding thereto is stated, at least one is formed on the first surface
A subsidence trough (103) towards second surface, at least one chip back mount the slot to the subsidence trough downward
Bottom, the chip front side include weld pad (201)；Between the chip side and the subsidence trough side wall, the chip just
The first insulating layer (4) is formed on face and the first surface；It is formed with horizontal arrangement or vertical row on first insulating layer
The inductance of cloth connects up, and horizontal arrangement or the capacitance wiring of vertical arrangement are formed on first insulating layer, and described first absolutely
Be also formed in edge layer and reroute the electrically derived metal of the chip pad, the inductance wiring, the capacitance wiring with
The weld pad of the chip is electrically connected.
2. the chip-packaging structure according to claim 1 for slowing down electromagnetic interference, it is characterised in that：Described first absolutely
Be formed in edge layer the first metal reroute (501), the first inductance wiring (502), the first capacitance wiring (503), described first
Metal reroutes the weld pad that the chip is electrically connected through first insulating layer, the first metal rewiring, described first
It is formed with second insulating layer (7) in inductance wiring, first capacitance wiring, the second metal is formed in the second insulating layer
Reroute (801), the second inductance wiring (802) and the second capacitance wiring (803), second metal reroutes transmission described the
Two insulating layers are electrically connected first metal and reroute, between each circuit of the first inductance wiring, the second inductance cloth
Pass through broken line mode between each circuit of line, between the circuit of first inductance wiring and the circuit of second inductance wiring
Continuous detour connects up at inductance, and parallel between each circuit or close to parallel, first capacitance wiring and the second capacitance cloth
Dielectric layer is equipped between line；Second metal reroutes, second inductance connects up, is covered on second capacitance wiring
Matcoveredn (10), an at least circuit extends to the silicon substrate table outside the chip area during second metal reroutes
On face.
3. the chip-packaging structure according to claim 1 for slowing down electromagnetic interference, it is characterised in that：Described first absolutely
It is formed with that the first metal reroutes (501), the first inductance wiring (502), the middle ware that continuously detour are separated with dielectric in edge layer
At least two first capacitance wirings (503) of layer, first metal reroutes, the wiring of the first inductance and the first capacitance wiring are saturating
Cross the weld pad that first insulating layer is electrically connected the chip；First metal reroutes, first inductance connects up, is described
Protective layer (10) is covered on first capacitance wiring, an at least circuit extends to the core during first metal reroutes
On silicon substrate outside panel region.
4. the chip-packaging structure according to claim 2 for slowing down electromagnetic interference, it is characterised in that：First electricity
Hold wiring and the second capacitance wiring for the identical metal derby of size.
5. the chip-packaging structure according to claim 2 for slowing down electromagnetic interference, which is characterized in that described first absolutely
The material of edge layer and the second insulating layer is polymer latex.
6. the chip-packaging structure according to claim 2 for slowing down electromagnetic interference, which is characterized in that second gold medal
Belong to the soldered ball/salient point (11) being connected on rerouting through the protective layer.
7. the chip-packaging structure according to claim 1 for slowing down electromagnetic interference, which is characterized in that the chip back of the body
Face is by cohering glue (3) attachment to the slot bottom of the subsidence trough, and the thickness for cohering glue is less than 50 microns, more than 1 micron.
8. the chip-packaging structure according to claim 1 for slowing down electromagnetic interference, which is characterized in that embedment is the same as once
The number of chips of heavy groove is more than or equal to 2.
9. the chip-packaging structure according to claim 2 for slowing down electromagnetic interference, which is characterized in that first gold medal
Belong to the thickness rerouted and is more than 0.2 micron.
10. a kind of packaging method for slowing down the chip-packaging structure of electromagnetic interference, which is characterized in that include the following steps：
A. provide one with first surface and second surface silicon substrate disc corresponding thereto, be formed on the first surface to
A few subsidence trough towards second surface, at least one chip back mount the slot bottom to the subsidence trough, institute downward
It is concordant with the silicon substrate first surface or close concordant to state chip front side, the chip front side includes weld pad；
B. it is laid with one between the chip side and the subsidence trough side wall, on the chip front side and the first surface
The first insulating layer of layer (4)；
C. the first metal is formed on first insulating layer reroutes (501), the first inductance wiring (502) and the first capacitance cloth
Line (503), first metal reroute the weld pad that the chip is electrically connected through first insulating layer；
D. it is laid with one layer second absolutely on first metal rewiring, first inductance wiring, first capacitance wiring
Edge layer (7)；
E. the second metal is formed in the second insulating layer reroutes (801), the second inductance wiring (802) and the second capacitance cloth
Line (803), second metal is rerouted to reroute through second insulating layer electrical connection first metal, and described second
The excessively described second insulating layer of partial line Reuter of inductance wiring is electrically connected the part circuit of first inductance wiring, makes described the
One inductance connects up and second inductance wiring constitutes the inductance wiring continuously detoured, and makes in the second metal rewiring extremely
A rare circuit extends on the silicon substrate outside the chip area；
F. layer protective layer is covered on second metal rewiring, second inductance wiring, second capacitance wiring
(10)；
G. the position formation protective layer opening done salient point or plant soldered ball is reserved in second metal rewiring, and in the protection
Layer opening forms soldered ball or salient point；
H. scribing is carried out to silicon substrate disc, forms the chip-packaging structure that monolithic is used to slow down electromagnetic interference.
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| CN107845653B (en) * | 2017-11-29 | 2023-07-14 | 苏州晶方半导体科技股份有限公司 | Packaging structure and packaging method of image sensing chip |
| US11315891B2 (en) | 2018-03-23 | 2022-04-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming semiconductor packages having a die with an encapsulant |
| CN111200351A (en) * | 2018-10-31 | 2020-05-26 | 圣邦微电子（北京）股份有限公司 | Power module and packaging integration method thereof |
| CN109994462B (en) * | 2019-03-29 | 2021-09-17 | 上海天马微电子有限公司 | Chip packaging structure and packaging method thereof |
| CN112017974B (en) * | 2019-05-28 | 2023-01-13 | 开元通信技术（厦门）有限公司 | Chip packaging structure and packaging method |
| CN111199926B (en) * | 2019-10-29 | 2021-08-17 | 浙江大学 | Semiconductor packaging structure with micro-separation cavity |
| CN113078148B (en) * | 2021-03-12 | 2024-03-26 | 上海易卜半导体有限公司 | Semiconductor packaging structure, method, device and electronic product |
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| CN102054821A (en) * | 2009-10-30 | 2011-05-11 | 日月光半导体制造股份有限公司 | Packaging structure with internal shield and manufacturing method thereof |
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