CN106160731A - Drive circuit - Google Patents
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- CN106160731A CN106160731A CN201510142095.5A CN201510142095A CN106160731A CN 106160731 A CN106160731 A CN 106160731A CN 201510142095 A CN201510142095 A CN 201510142095A CN 106160731 A CN106160731 A CN 106160731A
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Abstract
The invention discloses a kind of drive circuit.Wherein, this drive circuit includes: logic gates, for output drive signal；Signal transmission line, is connected to the outfan of logic gates, is used for transmitting driving signal；And signal optimization component, in parallel with signal transmission line, for optimizing the driving signal of logic gates output, the output signal after being optimized.By the present invention, reach the effect of the performance of the output signal improving logic gates.
Description
Technical field
The present invention relates to circuit field, in particular to a kind of drive circuit.
Background technology
In the integrated circuit of nanoscaled process, when carrying out Long line transmission (i.e. loading the biggest transmission), the most then
The output signal degradation of phase inverter can be caused, especially show the transmission time (Transition Time) of output signal
With on voltage magnitude, wherein, transmission time (Transition Time) may produce delay, and voltage magnitude is
Big value and minima then may reduce.
As it is shown in figure 1, be connected to can being equivalent in figure for carrying out the circuit of Long line transmission of the outfan of phase inverter
π-RC circuit structure in square frame.Wherein, when the RC in equivalent circuit is bigger, it appeared that output signal
Transmission time (Transition Time) and voltage magnitude occur in that relatively large deviation, as shown in Figure 2.
In order to improve the performance of the output signal of phase inverter, in the related, below scheme is typically used:
Scheme one: improved the performance of output signal by breadth length ratio W/L of regulation phase inverter self, though this scheme
So can improve the performance of output signal to a certain extent, but when W/L reaches certain value, in any case regulation
All will be unable to be effectively improved further the performance of output signal.
Scheme two: as it is shown on figure 3, Buffer insertion in equivalent circuit as shown in Figure 1, that is, be used for into
Buffer insertion in the circuit of row Long line transmission, this scheme is compared with scheme one, although can change to a greater extent
The performance of kind output signal, but this scheme can introduce delay gate, and the time delay that can increase circuit two ends at the whole story is inclined
Difference.
For the problems referred to above present in correlation technique, effective solution is the most not yet proposed.
Summary of the invention
Present invention is primarily targeted at a kind of drive circuit of offer, so that solve cannot be further present in correlation technique
The problem being effectively improved the performance of output signal.
To achieve these goals, according to an aspect of the invention, it is provided a kind of drive circuit.This drive circuit
Including: logic gates, for output drive signal；Signal transmission line, is connected to the defeated of above-mentioned logic gates
Go out end, be used for transmitting above-mentioned driving signal；And signal optimization component, in parallel with above-mentioned signal transmission line, it is used for
Optimize the driving signal of above-mentioned logic gates output, the output signal after being optimized.
Further, the equivalent circuit of above-mentioned signal transmission line is π-RC equivalent circuit.
Further, above-mentioned signal transmission line is provided with the first Preset Transfer point and the second Preset Transfer point, above-mentioned
Signal optimization component includes that a signal optimizes unit, and wherein, said one signal optimizes unit and is connected to above-mentioned first
Between Preset Transfer point and above-mentioned second Preset Transfer point.
Further, above-mentioned signal optimizes unit and includes: rising edge signal optimizes unit, at above-mentioned gate electricity
The rising edge driving signal of road output is triggered, and the driving signal exporting above-mentioned logic gates is optimized place
Reason；And/or trailing edge signal optimizes unit, touched for the trailing edge driving signal exported in above-mentioned logic gates
Send out, and the driving signal exporting above-mentioned logic gates is optimized process.
Further, when above-mentioned signal optimization unit includes that above-mentioned rising edge signal optimizes unit, above-mentioned rising edge is believed
Number optimize unit include: the first time-delay structure, the first sampling structure and the first PMOS and the second PMOS, its
In, above-mentioned first time-delay structure is connected between the grid of above-mentioned first sampling structure and above-mentioned first PMOS, on
State between the grid that the first sampling structure is connected to above-mentioned first time-delay structure and above-mentioned second PMOS, above-mentioned first
The drain electrode of PMOS connects power supply, and the source electrode of above-mentioned first PMOS is connected to the drain electrode of above-mentioned second PMOS,
The source electrode of above-mentioned second PMOS connects load.
Further, when above-mentioned signal optimization unit includes that above-mentioned trailing edge signal optimizes unit, above-mentioned trailing edge is believed
Number optimize unit include: the second time-delay structure, the second sampling structure and the first NMOS tube and the second NMOS tube,
Wherein, above-mentioned second time-delay structure is connected between the grid of above-mentioned second sampling structure and above-mentioned first NMOS tube,
Above-mentioned second sampling structure is connected between the grid of above-mentioned second time-delay structure and above-mentioned second NMOS tube, and above-mentioned
The grounded drain of one NMOS tube, the source electrode of above-mentioned first NMOS tube is connected to the drain electrode of above-mentioned second NMOS tube,
The source electrode of above-mentioned second NMOS tube connects load.
Further, optimize unit at above-mentioned signal and include that above-mentioned rising edge signal optimizes unit and above-mentioned trailing edge signal
When optimizing unit, above-mentioned rising edge signal optimizes unit and includes: the first time-delay structure, the first sampling structure and first
PMOS and the second PMOS；Above-mentioned trailing edge signal optimizes unit and includes: the second time-delay structure, the second sampling
Structure and the first NMOS tube and the second NMOS tube, wherein, above-mentioned first time-delay structure is connected to above-mentioned first and adopts
Between the grid of spline structure and above-mentioned first PMOS, above-mentioned first sampling structure is connected to above-mentioned first time-delay structure
With between the grid of above-mentioned second PMOS, the drain electrode of above-mentioned first PMOS meets power supply, an above-mentioned PMOS
The source electrode of pipe is connected to the drain electrode of above-mentioned second PMOS, and the source electrode of above-mentioned second PMOS connects load, and above-mentioned
Two time-delay structures are connected between the grid of above-mentioned second sampling structure and above-mentioned first NMOS tube, above-mentioned second sampling
Structure is connected between the grid of above-mentioned second time-delay structure and above-mentioned second NMOS tube, above-mentioned first NMOS tube
Grounded drain, the source electrode of above-mentioned first NMOS tube is connected to the drain electrode of above-mentioned second NMOS tube, above-mentioned second
The source electrode of NMOS tube connects above-mentioned load.
Further, above-mentioned first time-delay structure includes that even number of inverters, above-mentioned second time-delay structure include even number
Phase inverter.
Further, above-mentioned signal transmission line is provided with the 3rd Preset Transfer point, the 4th Preset Transfer point, the 5th
Preset Transfer point and the 6th Preset Transfer point, wherein, above-mentioned signal optimization component includes: the first signal optimizes unit,
It is connected between above-mentioned 3rd Preset Transfer point and above-mentioned 4th Preset Transfer point；And secondary signal optimizes unit, even
It is connected between above-mentioned 5th Preset Transfer point and above-mentioned 6th Preset Transfer point.
Further, above-mentioned signal optimization component includes: multiple signals optimize unit, and above-mentioned multiple signals optimize unit
Enable the most successively.
By the present invention, use logic gates, for output drive signal；Signal transmission line, is connected to logic
The outfan of gate circuit, is used for transmitting driving signal；And signal optimization component, in parallel with signal transmission line, use
In optimizing the driving signal that logic gates exports, the output signal after being optimized, solve in correlation technique and exist
The problem of the performance that cannot be effectively improved output signal further, and then reached more effectively to improve the defeated of phase inverter
Go out the effect of the performance of signal.
Accompanying drawing explanation
The accompanying drawing of the part constituting the application is used for providing a further understanding of the present invention, and the present invention's is schematic real
Execute example and illustrate for explaining the present invention, being not intended that inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the schematic diagram of the equivalent circuit of the drive circuit according to correlation technique；
Fig. 2 is the oscillogram of the drive circuit output signal according to correlation technique；
Fig. 3 is the schematic diagram of the equivalent circuit of the drive circuit of the improvement according to correlation technique；
Fig. 4 is the schematic diagram of drive circuit according to embodiments of the present invention；
Fig. 5 is the schematic diagram of Train driver structure according to embodiments of the present invention；And
Fig. 6 is the oscillogram of simulation result according to embodiments of the present invention.
Detailed description of the invention
It should be noted that in the case of not conflicting, the embodiment in the application and the feature in embodiment can phases
Combination mutually.Describe the present invention below with reference to the accompanying drawings and in conjunction with the embodiments in detail.
In order to make those skilled in the art be more fully understood that the application scheme, below in conjunction with in the embodiment of the present application
Accompanying drawing, is clearly and completely described the technical scheme in the embodiment of the present application, it is clear that described embodiment
It is only the embodiment of the application part rather than whole embodiments.Based on the embodiment in the application, ability
The every other embodiment that territory those of ordinary skill is obtained under not making creative work premise, all should belong to
The scope of the application protection.
It should be noted that term " first " in the description and claims of this application and above-mentioned accompanying drawing, "
Two " it is etc. for distinguishing similar object, without being used for describing specific order or precedence.Should be appreciated that this
The data that sample uses can be exchanged in the appropriate case, in order to embodiments herein described herein.Additionally, term
" include " and " having " and their any deformation, it is intended that cover non-exclusive comprising, such as, comprise
The process of series of steps or unit, method, system, product or equipment are not necessarily limited to those steps clearly listed
Rapid or unit, but can include that the most clearly list or intrinsic for these processes, method, product or equipment
Other step or unit.
According to embodiments of the invention, it is provided that a kind of drive circuit.
Fig. 4 is the schematic diagram of drive circuit according to embodiments of the present invention.As shown in Figure 4, drive circuit includes: patrol
Collect gate circuit 10, signal transmission line 20 and signal optimization component 30.
Logic gates 10 is for output drive signal, and wherein, the driving signal of output is used for driving loaded work piece.Tool
Body ground, when implementing, input logic gate circuit 10 can be with right and wrong door, phase inverter etc..Such as, in logic gates
10 when being phase inverter, and the input signal of input inverter produces driving signal, this driving after the reversion of phase inverter
Signal differs 180 degree with input signal in phase place.
Signal transmission line 20 is connected to the outfan of logic gates 10, is used for transmitting driving signal.Need explanation
, signal transmission line 20, according to the size of itself, can be divided into Long line transmission and short-term to transmit, wherein,
When the length of signal transmission line 20 is more than preset value, the signal on signal transmission line 20 is transmitted as Long line transmission；
Otherwise, then transmit for short-term.The present invention is adapted to but is not limited to be adapted to Long line transmission, and present invention below passes with long line
The present invention is elaborated as a example by defeated.It addition, as shown in Figure 4, signal transmission line 20 can be equivalent to π-RC etc.
Effect circuit, so, logic gates 10 output driving signal after π-RC circuit, Transition Time
Can produce delay, voltage magnitude can produce decay, causes the degradation driving signal finally exported.
Signal optimization component 30 is in parallel with signal transmission line 20, for optimizing the driving letter of logic gates 10 output
Number, the output signal after being optimized.When implementing, signal optimization component 30 is so that Transition Time
Postpone to reduce, and the decay of voltage magnitude is weakened, thus improve the performance driving signal of final output.
By the embodiment of the present invention, owing to signal optimization component 30 can improve the property driving signal of final output in time
Can, therefore reach the driving signal effect of degradation after Long line transmission preventing logic gates 10 from exporting
Really.
Preferably, in embodiments of the present invention, the equivalent circuit of signal transmission line is π-RC equivalent circuit, so,
Signal optimization component 30 and signal transmission line 20 can be determined according to the RC parameter value in π-RC equivalent circuit
Concrete parallel way and concrete position in parallel, as shown in Figure 4, signal optimization component 30 can be Train driver
The driver element of structure, each Train driver structure can be connected in parallel to the predeterminated position of signal transmission line 20.
It should be noted that above-mentioned signal optimization component can include one or more signal optimize unit, wherein,
Each signal optimizes unit can include one with signal optimization component individually below as a Train driver structure
Signal optimizes unit and signal optimization component includes that multiple signal elaborates the present invention as a example by optimizing unit.
Such as, when signal optimization component includes that a signal optimizes unit, transmission line is provided with first and presets biography
Defeated point and the second Preset Transfer point, wherein, the first Preset Transfer point can be the initiating terminal of transmission line, and second presets
Transmission point can be the clearing end of transmission line；Or, the first Preset Transfer point can be any point on transmission line,
Second Preset Transfer point can be any point on transmission line.In other words, this signal optimization unit can be with whole piece
Transmission line is in parallel, or with the part lines in parallel on whole transmission line road, wherein, in parallel,
This signal optimizes unit and is all connected between the first Preset Transfer point and the second Preset Transfer point.When implementing, permissible
The equivalent RC parameter etc. of the size of the load driven as required, transmission line determines the first Preset Transfer point and
The position of 2 Preset Transfer points.
Preferably, in embodiments of the present invention, each signal optimization unit may each comprise: rising edge signal optimizes single
Unit and/or trailing edge signal optimize unit.Rising edge signal optimizes unit and may be used for the driving in logic gates output
The rising edge of signal is triggered, and the driving signal of logic gates output is optimized process, that is, this
Under mode, in the driving signal of a logic gates output, only when rising edge occurs, rising edge signal is excellent
Change unit and just hold horizontal-drive signal optimization function；In like manner, trailing edge signal optimization unit may be used in logic gates
The trailing edge driving signal of output is triggered, and the driving signal of logic gates output is optimized process, also
I.e., in this manner, in the driving signal of a logic gates output, only when trailing edge occurs, under
Drop and just hold horizontal-drive signal optimization function along signal optimization unit.Signal optimizes unit and includes: rising edge signal optimizes single
Unit and trailing edge signal optimize unit, so, in the driving signal of a logic gates output, arrive at rising edge
When coming, rising edge signal optimizes unit and performs to optimize function, and when trailing edge arrives, trailing edge signal optimizes unit and holds
Row optimizes function, that is, in the driving signal of a logic gates output, can perform twice driving signal excellent
Change function.
When implementing, when signal optimization unit only includes rising edge signal optimization unit, rising edge signal optimizes unit
May include that the first time-delay structure, the first sampling structure and the first PMOS and the second PMOS, wherein,
One time-delay structure is connected between the grid of the first sampling structure and the first PMOS, and the first sampling structure is connected to
Between the grid of one time-delay structure and the second PMOS, the drain electrode of the first PMOS connects power supply, a PMOS
The source electrode of pipe is connected to the drain electrode of the second PMOS, and the source electrode of the second PMOS connects load.
When implementing, when signal optimization unit only includes trailing edge signal optimization unit, trailing edge signal optimizes unit
May include that the second time-delay structure, the second sampling structure and the first NMOS tube and the second NMOS tube, wherein,
Second time-delay structure is connected between the grid of the second sampling structure and the first NMOS tube, and the second sampling structure is connected to
Between the grid of the second time-delay structure and the second NMOS tube, the grounded drain of the first NMOS tube, a NMOS
The source electrode of pipe is connected to the drain electrode of the second NMOS tube, and the source electrode of the second PMOS connects load.
When implementing, as it is shown in figure 5, signal optimize unit can include rising edge signal optimize unit 502 and under
Drop along signal optimize both unit 504 time, rising edge signal optimize unit 502 may include that the first time-delay structure D1,
First sampling structure D2 and the first PMOS PMOS1 and the second PMOS PMOS2；Further, trailing edge letter
Number optimize unit 504 may include that the second time-delay structure D3, the second sampling structure D4 and the first NMOS tube
NMOS1 and the second NMOS tube NMOS2, wherein, the first time-delay structure D1 is connected to the first sampling structure D2
And first PMOS PMOS1 grid between, the first sampling structure D2 is connected to the first time-delay structure D1 and
Between the grid of two PMOS PMOS2, the drain electrode of the first PMOS PMOS1 meets power supply VCC, a PMOS
The source electrode of pipe PMOS1 is connected to the drain electrode of the second PMOS PMOS2, the source of the second PMOS PMOS2
Pole loads, and the second time-delay structure D3 is connected to the second sampling structure D4 and the grid of the first NMOS tube NMOS1
Between, the second sampling structure D4 be connected to the second time-delay structure D3 and the second NMOS tube NMOS2 grid it
Between, the drain electrode of the first NMOS tube NMOS1 connects power supply VCC, namely ground connection, the first NMOS tube NMOS1
Source electrode be connected to the drain electrode of the second NMOS tube NMOS2, the source electrode of the second NMOS tube NMOS2 connects load.
It should be noted that the first sampling structure and the second sampling structure can only include a phase inverter, so,
The quick upset of signal can be realized.
Preferably, in embodiments of the present invention, the first time-delay structure can include even number of inverters, in like manner, second
Time-delay structure can also include even number of inverters, in this manner it is ensured that the input signal of the first time-delay structure and output
Signal is in-phase signal.Concrete, anti-phase in the number of the phase inverter in the first time-delay structure and the second time-delay structure
The number of device can be determined according to concrete optimization rank.
The most such as, when signal optimization component includes that multiple signal optimizes unit, include that two signals optimize unit with it
As a example by, signal transmission line is provided with the 3rd Preset Transfer point, the 4th Preset Transfer point, the 5th Preset Transfer point and
6th Preset Transfer point, wherein, signal optimization component includes: the first signal optimizes unit and secondary signal optimizes unit.
First signal optimizes unit and is connected between the 3rd Preset Transfer point and the 4th Preset Transfer point；And secondary signal optimization
Unit, is connected between the 5th Preset Transfer point and the 6th Preset Transfer point.It should be noted that the 3rd Preset Transfer
Point, the 4th Preset Transfer point, the 5th Preset Transfer point and the 6th Preset Transfer point on transmission line arrange rule with
Aforesaid first Preset Transfer point and the second Preset Transfer point arrange rule, do not repeat them here.
It should be noted that in embodiments of the present invention, when signal optimization component includes that multiple signal optimizes unit,
Multiple signals optimize unit and can enable the most successively, for example, it is possible to optimize unit according to each signal to be connected in parallel on biography
Physical location on lines enables successively.
When implementing, in order to reach to improve the purpose of the performance of output signal, driving can be added the most step by step single
Unit, i.e. Train driver structure, that is, signal optimizes unit.Wherein, the progression added and Train Driver
The size of structure or part-structure, be required to the tool of the size according to concrete driver and the load driven
Body situation determines, every grade of Train Driver enables successively, and then improves the performance of output signal.
In the equivalent circuit of transmission line, add Train Driver structure step by step, improve the performance of output signal step by step,
Concrete work process is as follows: first, adds first order Train Driver, and during beginning, Train driver can be by conduct
Load, causes a certain degree of time delay, but is as Train Driver and is triggered, and signal will overturn, and makes
Train driver is become driving effect from the effect of load, thus drive output signal, improve the partial properties of output signal；
Then, if the driving limited use of first order Train Driver structure, then need to add second level Train Driver again
Structure, in like manner drive output signal, and improve the performance of output signal.As such, it is possible to reach the most step by step
Improve the effect of the performance of output signal.Wherein, the number of phase inverter in Train Driver structure, can be according to being driven
The size of the size of dynamic load and logic gates (e.g., phase inverter) is adjusted, that is, this kind of structure
In middle Train Driver structure, in chain of inverters, the number of phase inverter is not changeless, but can want according to output
Changes persuing.
It should be noted that in embodiments of the present invention, above-mentioned Train Driver structure is mainly adapted to Long line transmission,
The global line that i.e. duty factor is bigger, and it is not suitable for short-term transmission, otherwise can be because adding load and increasing circuit
Time delay.It addition, discounting for the factor of waste area, above-mentioned Train Driver structure is adapted to most of electricity
Lu Zhong, is not limited to a certain technological level, more efficient for low nanometer technology, such as, and the lowest nanometer technology
The Global signal that in circuit, duty factor is bigger.It addition, the present invention is applicable not only to SRAM circuit, it is equally applicable to
Other have the circuit signal of this demand, in this no limit.
Carrying out emulation testing analysis as a example by 40nm process to understand, the drive circuit of the present invention, owing to the addition of train
Driver structure, although before train driver structure is triggered, can increase fraction of time delay, but once be touched
Sending out, train driver structure will be changed into driver element so that output waveform can be obviously improved, so that output
The performance of signal is obviously improved.As shown in Figure 6, the waveform 1 of transition time difference originally, is adding train driver
After structure, simulation result becomes waveform 2, it is clear that transition time is obviously improved；Original voltage amplitude and
Waveform 3 the poorest for transition time, after adding train driver structure, simulation result becomes waveform 4, it is clear that two
Person is all obviously improved.By simulation result, train driver structure can be obviously improved cannot be by adjusting
Joint logic gates (e.g., phase inverter) breadth length ratio W/L improve long line output signal Transition time and
Voltage magnitude.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for the skill of this area
For art personnel, the present invention can have various modifications and variations.All within the spirit and principles in the present invention, made
Any modification, equivalent substitution and improvement etc., should be included within the scope of the present invention.
Claims (10)
1. a drive circuit, it is characterised in that including:
Logic gates, for output drive signal；
Signal transmission line, is connected to the outfan of described logic gates, is used for transmitting described driving signal；
And
Signal optimization component, in parallel with described signal transmission line, for optimizing the output of described logic gates
Drive signal, the output signal after being optimized.
Drive circuit the most according to claim 1, it is characterised in that the equivalent circuit of described signal transmission line is
π-RC equivalent circuit.
Drive circuit the most according to claim 1, it is characterised in that be provided with first on described signal transmission line
Preset Transfer point and the second Preset Transfer point, described signal optimization component includes that a signal optimizes unit,
Wherein, one signal optimization unit is connected to described first Preset Transfer point and described second and presets biography
Between defeated point.
Drive circuit the most according to claim 3, it is characterised in that described signal optimizes unit and includes:
Rising edge signal optimizes unit, is touched for the rising edge driving signal exported in described logic gates
Send out, and the driving signal exporting described logic gates is optimized process；And/or
Trailing edge signal optimizes unit, is touched for the trailing edge driving signal exported in described logic gates
Send out, and the driving signal exporting described logic gates is optimized process.
Drive circuit the most according to claim 4, it is characterised in that optimize unit at described signal and include on described
When rising along signal optimization unit, described rising edge signal optimizes unit and includes: the first time-delay structure, the first sampling
Structure and the first PMOS and the second PMOS, wherein,
Described first time-delay structure be connected to described first sampling structure and described first PMOS grid it
Between, described first sampling structure is connected between the grid of described first time-delay structure and described second PMOS,
The drain electrode of described first PMOS connects power supply, and the source electrode of described first PMOS is connected to described second
The drain electrode of PMOS, the source electrode of described second PMOS connects load.
Drive circuit the most according to claim 4, it is characterised in that described signal optimize unit include described under
When dropping along signal optimization unit, described trailing edge signal optimizes unit and includes: the second time-delay structure, the second sampling
Structure and the first NMOS tube and the second NMOS tube, wherein,
Described second time-delay structure be connected to described second sampling structure and described first NMOS tube grid it
Between, described second sampling structure is connected between the grid of described second time-delay structure and described second NMOS tube,
The grounded drain of described first NMOS tube, the source electrode of described first NMOS tube is connected to described 2nd NMOS
The drain electrode of pipe, the source electrode of described second NMOS tube connects load.
Drive circuit the most according to claim 4, it is characterised in that optimize unit at described signal and include on described
When rising along signal optimization unit and described trailing edge signal optimization unit,
Described rising edge signal optimizes unit and includes: the first time-delay structure, the first sampling structure and a PMOS
Pipe and the second PMOS；
Described trailing edge signal optimizes unit and includes: the second time-delay structure, the second sampling structure and a NMOS
Pipe and the second NMOS tube,
Wherein, described first time-delay structure is connected to described first sampling structure and the grid of described first PMOS
Between pole, described first sampling structure is connected to described first time-delay structure and the grid of described second PMOS
Between, the drain electrode of described first PMOS connects power supply, and the source electrode of described first PMOS is connected to described
The drain electrode of two PMOS, the source electrode of described second PMOS connects load,
Described second time-delay structure be connected to described second sampling structure and described first NMOS tube grid it
Between, described second sampling structure is connected between the grid of described second time-delay structure and described second NMOS tube,
The grounded drain of described first NMOS tube, the source electrode of described first NMOS tube is connected to described 2nd NMOS
The drain electrode of pipe, the source electrode of described second NMOS tube connects described load.
Drive circuit the most according to claim 7, it is characterised in that described first time-delay structure includes that even number is anti-
Phase device, described second time-delay structure includes even number of inverters.
Drive circuit the most according to claim 1, it is characterised in that be provided with the 3rd on described signal transmission line
Preset Transfer point, the 4th Preset Transfer point, the 5th Preset Transfer point and the 6th Preset Transfer point, wherein, described
Signal optimization component includes:
First signal optimizes unit, is connected between described 3rd Preset Transfer point and described 4th Preset Transfer point；
And
Secondary signal optimizes unit, is connected between described 5th Preset Transfer point and described 6th Preset Transfer point.
Drive circuit the most according to claim 1, it is characterised in that described signal optimization component includes: Duo Gexin
Number optimize unit, the plurality of signal optimize unit enable the most successively.
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| CN101388676A (en) * | 2008-10-30 | 2009-03-18 | 北京航空航天大学 | Optimized matching design for small antenna wideband matching network and small antenna wideband matching network thereof |
| CN101431320A (en) * | 2007-11-08 | 2009-05-13 | 中芯国际集成电路制造(上海)有限公司 | High-stability D trigger structure |
| US20090185654A1 (en) * | 2008-01-21 | 2009-07-23 | Hynix Semiconductor Inc. | Shift circuit capable of reducing current consumption by controlling latch operation |
| CN103427781A (en) * | 2013-08-31 | 2013-12-04 | 西安电子科技大学 | Silicone substrate high-linearity low-phase-shift ultra-broad-band digital attenuator |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101431320A (en) * | 2007-11-08 | 2009-05-13 | 中芯国际集成电路制造(上海)有限公司 | High-stability D trigger structure |
| US20090185654A1 (en) * | 2008-01-21 | 2009-07-23 | Hynix Semiconductor Inc. | Shift circuit capable of reducing current consumption by controlling latch operation |
| CN101388676A (en) * | 2008-10-30 | 2009-03-18 | 北京航空航天大学 | Optimized matching design for small antenna wideband matching network and small antenna wideband matching network thereof |
| CN103427781A (en) * | 2013-08-31 | 2013-12-04 | 西安电子科技大学 | Silicone substrate high-linearity low-phase-shift ultra-broad-band digital attenuator |
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| CN106160731B (en) | 2019-06-04 |
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