CN106158661A - Groove-shaped VDMOS manufacture method - Google Patents
Groove-shaped VDMOS manufacture method Download PDFInfo
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- CN106158661A CN106158661A CN201510205792.0A CN201510205792A CN106158661A CN 106158661 A CN106158661 A CN 106158661A CN 201510205792 A CN201510205792 A CN 201510205792A CN 106158661 A CN106158661 A CN 106158661A
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Abstract
The invention provides a kind of groove-shaped VDMOS manufacture method.The method includes: the zone line in N-type epitaxy layer forms the first groove；Selective epitaxial growth process is used to form p-type ion district in the first groove；The second groove is formed respectively in the subregion of both sides, N-type epitaxy layer ZhongPXing ion district；Upper surface and the second grooved inner surface in N-type epitaxy layer form gate oxide；Deposit polycrystalline silicon layer on gate oxide in the second groove；Form the body district of groove-shaped VDMOS, source region, dielectric layer and metal level.It is effectively increased the breakdown voltage of groove-shaped VDMOS, ShiPXing ion district no longer horizontal proliferation simultaneously, it is ensured that the threshold voltage unchanged of groove-shaped VDMOS, makes the spacing between the groove of deposit polycrystalline silicon layer constant, and then maintain cellular density, it is ensured that the driving force of groove-shaped VDMOS.
Description
Technical field
The present embodiments relate to semiconductor device processing technology field, particularly relate to a kind of groove-shaped
VDMOS manufacture method.
Background technology
Trench vertical dmost (is called for short: be groove-shaped VDMOS) logical
Form longitudinal diffusion range difference after crossing source ion and body ion implanting and form raceway groove, and be widely used in switch
Power supply and synchronous rectification field.Comparing plane VDMOS, groove-shaped VDMOS is owing to eliminating JFET
District, so its internal resistance is the least.But due to corner's curvature of channel bottom in groove-shaped VDMOS
Radius is little, and the breakdown voltage making groove-shaped VDMOS is relatively low.
In prior art, in order to improve the breakdown voltage of groove-shaped VDMOS, mainly take to connect at metal
The method of the region implanting p-type ion of contact hole.As it is shown in figure 1, inject P in the region of metal contact hole
After type ion, p-type ion implanted region 15 has shared the field intensity bottom part the second groove 6, makes the second ditch
Field intensity bottom groove 6 weakens, and then improves breakdown voltage.Wherein, p-type ion implanted region 15
Bottom closer to the second groove 6 bottom, the field intensity shared is the most.Under optimal cases, as in figure 2 it is shown, P
The bottom of the bottom of type ion implanted region 15 and the second groove 6 when same level, the second groove 6
The field intensity of bottom is the most weak, and breakdown voltage reaches the highest.
But this kind is in the method for the region implanting p-type ion raising breakdown voltage of metal contact hole, in p-type
While the degree of depth of the bottom that the bottom of ion implanted region 15 pushes the second groove 6 to, p-type ion implanted region
15 also in horizontal proliferation, thus changes the ion concentration of channel region, makes the threshold voltage of VDMOS send out
Changing, and then make groove-shaped VDMOS cisco unity malfunction.
In order to prevent the generation of this situation, as it is shown on figure 3, the spacing of two the second grooves 6 is widened,
But this makes groove-shaped VDMOS cellular density reduce, and reduces the driving force of groove-shaped VDMOS.
Summary of the invention
The embodiment of the present invention provides a kind of groove-shaped VDMOS manufacture method, is effectively increased groove-shaped
The breakdown voltage of VDMOS, the simultaneously no longer horizontal proliferation of ShiPXing ion district, it is ensured that groove-shaped
The threshold voltage unchanged of VDMOS, makes the spacing between the groove of deposit polycrystalline silicon layer constant, Jin Erwei
Hold cellular density, it is ensured that the driving force of groove-shaped VDMOS.
The embodiment of the present invention provides a kind of groove-shaped VDMOS manufacture method, including:
Zone line in N-type epitaxy layer forms the first groove；
Selective epitaxial growth process is used to form p-type ion district in the first groove；
The second groove is formed respectively in the subregion of both sides, described N-type epitaxy layer ZhongPXing ion district；
Upper surface and described second grooved inner surface in described N-type epitaxy layer form gate oxide；
Deposit polycrystalline silicon layer on gate oxide in described second groove；
Form the body district of described groove-shaped VDMOS, source region, dielectric layer and metal level.
Further, method as above, described zone line in N-type epitaxy layer forms first
Groove specifically includes:
Described N-type epitaxy layer deposits hard mask layer；
Zone line in described hard mask layer is carried out photoetching, etching, forms the first trench openings district；
The underside area in described first trench openings district is performed etching, is formed in described N-type epitaxy layer
First groove.
Further, method as above, described in both sides, described N-type epitaxy layer ZhongPXing ion district
Subregion form the second groove respectively and specifically include:
Described N-type epitaxy layer deposits hard mask layer；
The subregion of the both sides, described p-type ion district in described hard mask layer is carried out photoetching, etching,
Form the second trench openings district；
The underside area in described second trench openings district is performed etching, is formed in described N-type epitaxy layer
Second groove.
Further, method as above, the degree of depth phase of described first groove and described second groove
With.
Further, method as above, described in described N-type epitaxy layer, form the second groove
After, also include:
The base angle of described second groove is carried out round and smooth process；
Remove described hard mask layer.
Further, method as above, the dopant ion of the p-type extension in described p-type ion district
For boron ion, the doping content of described p-type extension is 1E19-1E20 atomic number/cubic centimetre.
Further, method as above, heavy on described gate oxide in described second groove
After long-pending polysilicon layer, also include:
Carry out back described polysilicon layer processing quarter, so that the upper surface of described polysilicon layer, described P
The upper surface in type ion district is with the upper surface of described N-type epitaxy layer at grade.
Further, method as above, the thickness of described polysilicon layer is 6000-12000 angstrom, institute
The thickness stating gate oxide is 400-1000 angstrom.
The embodiment of the present invention provides a kind of groove-shaped VDMOS manufacture method, by N-type epitaxy layer
Zone line form the first groove；Selective epitaxial growth process is used to form p-type in the first groove
Ion district；The second groove is formed respectively in the subregion of both sides, N-type epitaxy layer ZhongPXing ion district；?
The upper surface of N-type epitaxy layer and the second grooved inner surface form gate oxide；Grid oxygen in the second groove
Change deposit polycrystalline silicon layer on layer；Form the body district of groove-shaped VDMOS, source region, dielectric layer and metal
Layer.Being effectively increased the breakdown voltage of groove-shaped VDMOS, ShiPXing ion district the most laterally expands simultaneously
Dissipate, it is ensured that the threshold voltage unchanged of groove-shaped VDMOS, make between the groove of deposit polycrystalline silicon layer
Spacing is constant, and then maintains cellular density, it is ensured that the driving force of groove-shaped VDMOS.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to reality
Execute the required accompanying drawing used in example or description of the prior art to be briefly described, it should be apparent that under,
Accompanying drawing during face describes is some embodiments of the present invention, for those of ordinary skill in the art,
On the premise of not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is first structural representation of groove-shaped VDMOS in prior art；
Fig. 2 is second structural representation of groove-shaped VDMOS in prior art；
Fig. 3 is the 3rd structural representation of groove-shaped VDMOS in prior art；
Fig. 4 is the flow chart of the present invention groove-shaped VDMOS manufacture method embodiment one；
In N-type epitaxy layer in the groove-shaped VDMOS manufacture method that Fig. 5 provides for the embodiment of the present invention one
In zone line form the structural representation after the first groove；
The groove-shaped VDMOS manufacture method that Fig. 6 provides for the embodiment of the present invention one uses outside selectivity
Growth process forms the structural representation behind p-type ion district in the first groove；
In N-type epitaxy layer in the groove-shaped VDMOS manufacture method that Fig. 7 provides for the embodiment of the present invention one
The subregion of both sides, ZhongPXing ion district forms the structural representation after the second groove respectively；
In N-type epitaxy layer in the groove-shaped VDMOS manufacture method that Fig. 8 provides for the embodiment of the present invention one
Upper surface and the second grooved inner surface form the structural representation after gate oxide；
In the groove-shaped VDMOS manufacture method that Fig. 9 provides for the embodiment of the present invention one in the second groove
Gate oxide on structural representation after deposit polycrystalline silicon layer；
The groove-shaped VDMOS manufacture method that Figure 10 provides for the embodiment of the present invention one is formed groove-shaped
The body district of VDMOS, source region, dielectric layer and the flow chart of metal level；
Groove-shaped in the groove-shaped VDMOS manufacture method that Figure 11 provides for the embodiment of the present invention one
The N-type epitaxy layer of VDMOS is formed the structural representation behind body district；
In the groove-shaped VDMOS manufacture method Zhong Ti district that Figure 12 provides for the embodiment of the present invention one second
The two side areas of groove forms the structural representation after source region；
In the groove-shaped VDMOS manufacture method that Figure 13 provides for the embodiment of the present invention one above source region
Gate oxide on dielectric layer the structural representation after removing gate oxide；
The groove-shaped VDMOS manufacture method that Figure 14 provides for the embodiment of the present invention one deposit groove-shaped
Structural representation after the metal level of VDMOS；
Figure 15 is the first pass figure of the present invention groove-shaped VDMOS manufacture method embodiment two；
Figure 16 is the second flow chart of the present invention groove-shaped VDMOS manufacture method embodiment two；
In N-type extension in the groove-shaped VDMOS manufacture method that Figure 17 provides for the embodiment of the present invention two
The structural representation after hard mask layer is deposited on layer；
To hard mask layer in the groove-shaped VDMOS manufacture method that Figure 18 provides for the embodiment of the present invention two
In zone line carry out photoetching, etching, form the structural representation behind the first trench openings district；
To the first groove window in the groove-shaped VDMOS manufacture method that Figure 19 provides for the embodiment of the present invention two
The underside area of mouth region performs etching, and forms the structural representation after the first groove in N-type epitaxy layer；
Figure 20 is the 3rd flow chart of the present invention groove-shaped VDMOS manufacture method embodiment two.
Reference:
1-N type substrate 2-N type epitaxial layer 3-hard mask layer
4-the first groove 5-P type extension 6-the second groove
7-gate oxide 8-polysilicon layer 9-body district
10-source region 11-dielectric layer 12-front metal layer
13-metal layer on back 14-the first trench openings district 15-P type ion implanted region
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with this
Accompanying drawing in bright embodiment, is clearly and completely described the technical scheme in the embodiment of the present invention,
Obviously, described embodiment is a part of embodiment of the present invention rather than whole embodiments.Based on
Embodiment in the present invention, those of ordinary skill in the art are obtained under not making creative work premise
The every other embodiment obtained, broadly falls into the scope of protection of the invention.
Embodiment one
Fig. 4 is the flow chart of the present invention groove-shaped VDMOS manufacture method embodiment one, as shown in Figure 4,
The groove-shaped VDMOS manufacture method that the present embodiment provides includes:
Step 101, the zone line in N-type epitaxy layer 2 forms the first groove 4.
In the present embodiment, N-type epitaxy layer 2 is grown in N-type substrate 1.Wherein, N-type substrate 1 is
Heavily doped N-type substrate, N-type epitaxy layer 2 is lightly doped n type epitaxial layer.Concrete N-type substrate 1
Doping content and the doping content of N-type epitaxy layer 2 identical with doping content of the prior art,
This repeats the most one by one.
In the present embodiment, in the groove-shaped VDMOS manufacture method that Fig. 5 provides for the embodiment of the present invention one
Zone line in N-type epitaxy layer forms the structural representation after the first groove, as it is shown in figure 5, N
Zone line in type epitaxial layer 2 forms the first groove 4, and the first groove 4 is for being used for forming p-type ion
The groove in district, the cross sectional shape of the first groove 4 is rectangle, and the degree of depth of this first groove 4 is less than outside N-type
Prolong the thickness of layer 2.
Specifically, the zone line in N-type epitaxy layer 2 form technique that the first groove 4 used can
Think photoetching, etching technics, it is also possible to for other technique, this is not limited by the present embodiment.
Step 102, uses selective epitaxial growth process to form p-type ion district in the first groove 4.
Specifically, outer epitaxial growth technology (the Selective Epitaxial silicon Growth of selectivity
Process, is called for short SEG) it is the epitaxially grown technique carried out in the restriction region of N-type epitaxy layer.
Limiting region as the first groove 4 in the present embodiment, the extension of growth is p-type extension 5, at growth P
After type extension 5, the first groove 4 and p-type extension 5 constitute p-type ion district.
Wherein, the dopant ion in p-type extension 5 can be boron ion.Fig. 6 is the embodiment of the present invention one
Selective epitaxial growth process shape in the first groove is provided in the groove-shaped VDMOS manufacture method provided
Structural representation behind ChengPXing ion district.
Step 103, forms second respectively in the subregion of both sides, N-type epitaxy layer 2 ZhongPXing ion district
Groove 6.
In the present embodiment, form respectively in the subregion of both sides, N-type epitaxy layer 2 ZhongPXing ion district
The technique used during two grooves 6 can be photoetching, etching technics, it is also possible to for other technique, this reality
Execute example this is not limited.
In the present embodiment, the second groove 6 is the groove for depositing polysilicon layer.Wherein, Fig. 7 is this
In N-type epitaxy layer ZhongPXing ion district in the groove-shaped VDMOS manufacture method that inventive embodiments one provides
The subregion of both sides forms the structural representation after the second groove respectively, as it is shown in fig. 7, the second groove
The cross sectional shape of 6 is rectangle, and the degree of depth of the second groove 6 is less than the thickness of N-type epitaxy layer 2.P-type from
Sub-district respectively and has spacing between the second groove 6.
Step 104, upper surface and the second groove 6 inner surface in N-type epitaxy layer 2 form gate oxide 7.
In the present embodiment, the upper surface of N-type epitaxy layer 2 is the N-type epitaxy layer 2 removing the second groove 6
Upper surface.The thickness of the gate oxide 7 in the present embodiment can be 400-1000 angstrom.Wherein, Fig. 8 is
At the upper surface of N-type epitaxy layer in the groove-shaped VDMOS manufacture method that the embodiment of the present invention one provides
And second grooved inner surface form the structural representation after gate oxide.
Step 105, deposit polycrystalline silicon layer 8 on the gate oxide 7 in the second groove 6.
In the present embodiment, the thickness of the polysilicon layer 8 of deposition on the gate oxide 7 in the second groove 6
It it is 6000～12000 angstroms.Wherein, the groove-shaped VDMOS that Fig. 9 provides for the embodiment of the present invention one manufactures
Structural representation after deposit polycrystalline silicon layer on gate oxide in the second groove in method.
Step 106, forms the body district 9 of groove-shaped VDMOS, source region 10, dielectric layer 11 and metal level.
Wherein, metal level includes front metal layer 12 and metal layer on back 13.
In the present embodiment, step 106 particularly may be divided into following four step and performs.
Step 106a, forms body district 9 in the N-type epitaxy layer 2 of groove-shaped VDMOS.
Specifically, when forming the body district 9 of groove-shaped VDMOS, use p-type ion implantation technology,
Forming body district 9, the p-type ion wherein injected can be boron ion, and dosage can be 1.0E13-1.0E15
Individual/square centimeter, energy can be 60-120KEV, then carries out high temperature and drives in, and temperature can be
900-1150 degree, the time of driving in can be 40～100 minutes.
In the present embodiment, in the groove-shaped VDMOS manufacture method that Figure 11 provides for the embodiment of the present invention one
The structural representation behind body district is formed in the N-type epitaxy layer of groove-shaped VDMOS, as shown in figure 11,
The body district 9 of groove-shaped VDMOS is formed in N-type epitaxy layer 2, and the thickness in body district 9 is less than N-type extension
The thickness of layer 2.
Step 106b, in body district 9, the two side areas of the second groove 6 forms source region 10.
In the present embodiment, defined the region of source region 10 by photoetching process, and use ion implanting work
Skill, injects N-type ion.The N-type ion wherein injected can be arsenic or phosphorus.The dosage injected is permissible
For 1.0E15-1.0E16/square centimeter, energy can be 50-120KEV.Then carry out ion-activated,
Ion-activated temperature can be 800～1000 degree, and the ion-activated time can be 20-60 minute.
In the present embodiment, the groove-shaped VDMOS manufacture method that Figure 12 provides for the embodiment of the present invention one
Structural representation after the two side areas of the second groove forms source region in Zhong Ti district.As shown in figure 12,
Source region 10 is formed at the two side areas of the second groove 6 in body district 9.
Step 106c, dielectric layer 11 on the gate oxide 7 above source region 10.
In the present embodiment, dielectric layer 11 can be silicon dioxide layer or doped with boron and the silicon dioxide of phosphorus
Layer.
In the present embodiment, the groove-shaped VDMOS manufacture method that Figure 13 provides for the embodiment of the present invention one
In dielectric layer the structural representation after removing gate oxide on gate oxide above source region
Figure.As shown in figure 13, on the gate oxide 7 above source region 10 after dielectric layer 11, carry out
Aperture layer photoetching and etching technics, concrete aperture layer photoetching and etching technics are prior art, at this no longer
Repeat one by one.
Step 106d, deposits the metal level of groove-shaped VDMOS.
In the present embodiment, metal level includes: front metal layer 12 and metal layer on back 13.Wherein front
Metal level 12 can be Al-Si-Cu alloy, forms source metal, and thickness can be 2-4 micron, the back side
Metal level 13 can be titanium nickeline composite bed, forms drain metal layer.Wherein, Figure 14 is that the present invention is real
Execute after the groove-shaped VDMOS manufacture method that example one provides deposits the metal level of groove-shaped VDMOS
Structural representation.
The groove-shaped VDMOS manufacture method that the present embodiment provides, by the centre in N-type epitaxy layer
Region forms the first groove；Selective epitaxial growth process is used to form p-type ion in the first groove
District；The second groove is formed respectively in the subregion of both sides, N-type epitaxy layer ZhongPXing ion district；In N-type
The upper surface of epitaxial layer and the second grooved inner surface form gate oxide；Gate oxide in the second groove
Upper deposit polycrystalline silicon layer；Form the body district of groove-shaped VDMOS, source region, dielectric layer and metal level.Have
Effect improves the breakdown voltage of groove-shaped VDMOS, simultaneously because have employed the growth of selective growth technique
P-type extension, ShiPXing ion district no longer horizontal proliferation, it is ensured that the threshold voltage of groove-shaped VDMOS
Constant, and keep the spacing between the first groove and the second groove, make deposit polycrystalline silicon layer groove it
Between spacing constant, and then maintain cellular density, it is ensured that the driving force of groove-shaped VDMOS.
Embodiment two
Figure 15 is the first pass figure of the present invention groove-shaped VDMOS manufacture method embodiment two, such as figure
Shown in 15, the groove-shaped VDMOS manufacture method that the present embodiment provides includes:
Step 201, the zone line in N-type epitaxy layer 2 forms the first groove 4.
Further, in the present embodiment, step 201 can be divided into three below step to perform, Tu16Wei
The second flow chart of the present invention groove-shaped VDMOS manufacture method embodiment two, as shown in Figure 6, step
201 include:
Step 201a, deposits hard mask layer 3 in N-type epitaxy layer 2.
In the present embodiment, in N-type epitaxy layer 2, the hard mask layer 3 of deposition can be silicon dioxide layer.Heavy
Long-pending technique can be low-pressure chemical vapor deposition.The thickness of the hard mask layer of deposition can be
4000-7000 angstrom.Wherein, the groove-shaped VDMOS manufacturer that Figure 17 provides for the embodiment of the present invention two
Method deposits in N-type epitaxy layer the structural representation after hard mask layer.
Step 201b, carries out photoetching, etching to the zone line in hard mask layer 3, forms the first ditch
Groove window region 14.
In the present embodiment, use photoetching, etching technics, etch away the hard mask layer 3 of zone line,
Define the first trench openings district 14.Wherein the first groove is the groove for forming p-type ion district.
First trench openings district 14 is the window region forming the first groove after performing etching.
Alternatively, in the present embodiment, etching technics can use dry etch process.Wherein, Figure 18 is this
To the mesozone in hard mask layer in the groove-shaped VDMOS manufacture method that inventive embodiments two provides
Territory carries out photoetching, etching, forms the structural representation behind the first trench openings district.
Step 201c, performs etching the underside area in the first trench openings district 14, in N-type epitaxy layer 2
Middle formation the first groove 4.
In the present embodiment, dry etch process can be used, the first trench openings district 14 underside area is entered
Row etching, forms the first groove 4 in N-type epitaxy layer 2, and wherein the cross sectional shape of the first groove 4 is
Rectangle, the degree of depth of the first groove 4 is less than the thickness of N-type epitaxy layer 2.Wherein, Figure 19 is the present invention
In the groove-shaped VDMOS manufacture method that embodiment two provides, the underside area to the first trench openings district is entered
Row etching, forms the structural representation after the first groove in N-type epitaxy layer.As shown in figure 19,
One groove 4 is positioned at the underface in the first trench openings district 14, the side of the first groove 4 and the first groove window
The side of mouth region 14 is in the same plane.
Step 202, uses selective epitaxial growth process to form p-type ion district in the first groove 4.
Preferably, the dopant ion of the p-type extension 5 in p-type ion district in the present embodiment is boron ion,
The doping content of p-type extension is 1E19-1E20 atomic number/cubic centimetre.
Other in step 202 technique and the present invention groove-shaped VDMOS manufacture method in the present embodiment
Identical in step 102 in embodiment one, this is no longer going to repeat them.
After step 202, use technique of the prior art, remove hard mask layer 3.
Step 203, forms the second ditch respectively in the subregion of both sides, N-type epitaxy layer 2 ZhongPXing ion district
Groove 6.
Further, the step 203 in the present embodiment can be divided into three below step to perform.Figure 20
For the 3rd flow chart of the present invention groove-shaped VDMOS manufacture method embodiment two, as shown in figure 20,
Step 203 includes:
Step 203a, deposits hard mask layer 3 in N-type epitaxy layer 2.
In the present embodiment, step 203a is identical with the technique of step 202a, and this is no longer going to repeat them.
Step 203b, carries out photoetching, quarter to the subregion of the both sides, p-type ion district in hard mask layer 3
Erosion, forms the second trench openings district.
In the present embodiment, use photoetching, etching technics, etch away and hard mask layer 3 is positioned at p-type ion
The hard mask layer of the subregion of both sides, district, defines the second trench openings district.Wherein the second groove is
For the groove of deposit polycrystalline silicon layer, the second trench openings district is second formed after performing etching
The window region of groove.
Alternatively, in the present embodiment, etching technics can use dry etch process.
In the present embodiment, the second groove 6 is positioned at the underface in the second trench openings district, the second groove 6
Side is in the same plane with the side in the second trench openings district.
Step 203c, performs etching the underside area in the second trench openings district, in N-type epitaxy layer 2
Middle formation the second groove 6.
In the present embodiment, dry etch process can be used, the underside area in the second trench openings district is entered
Row etching, forms the second groove 6 in 2 in N-type epitaxy layer.Wherein, the cross sectional shape of the second groove 6
For rectangle, the degree of depth of the second groove 6 is less than the thickness of N-type epitaxy layer 2.
Preferably, in the present embodiment, the first groove 4 is identical with the degree of depth of the second groove 6.
In the present embodiment, after forming p-type ion district, p-type ion district can share for second groove 6 end
The field intensity in portion, thus improve breakdown voltage, the bottom of the first groove 4 is closer to the end of the second groove 6
Portion, the field intensity shared is the most, when the first groove 4 is identical with the degree of depth of the second groove 6, the i.e. first groove
The bottom of bottom and the second groove when being positioned at same level, the field intensity of the second channel bottom is the most weak, hits
Wear voltage and reach the highest.
Step 204, carries out round and smooth process to the base angle of the second groove 6.
In the present embodiment, owing to the base angle of the second groove 6 is right angle, radius of curvature is little, causes breakdown potential
Press relatively low, so after the base angle of the second groove 6 is carried out round and smooth process, making the base angle of the second groove 6
Curvature increases, and further increases the breakdown voltage of this groove-shaped VDMOS.
In the present embodiment, after the base angle of the second groove 6 is carried out round and smooth process, use in prior art
Method remove hard mask layer 3.
Step 205, upper surface and the second groove 6 inner surface in N-type epitaxy layer 2 form gate oxide 7.
Step 206, deposit polycrystalline silicon layer 8 on the gate oxide 7 in the second groove 6.
In the present embodiment, step 205-step 206 is implemented with the present invention groove-shaped VDMOS manufacture method
Step 104-step 105 in example one is identical, and this is no longer going to repeat them.
Step 207, carries out back polysilicon layer 8 processing quarter.
In the present embodiment, polysilicon layer 8 is carried out back quarter process after, make polysilicon layer 8 upper surface,
The upper surface in p-type ion district is with the upper surface of N-type epitaxy layer 2 at grade.
Step 208, forms the body district 9 of groove-shaped VDMOS, source region 10, dielectric layer 11 and metal level.
In the present embodiment, in step 208 and the present invention groove-shaped VDMOS manufacture method embodiment one
Step 106 is identical, and this is no longer going to repeat them.
The groove-shaped VDMOS manufacture method provided in the present embodiment, the degree of depth of the first groove and second
The degree of depth of groove is identical, and the base angle of the second groove is carried out round and smooth process, can improve ditch further
The breakdown voltage of grooved VDMOS.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, rather than right
It limits；Although the present invention being described in detail with reference to foregoing embodiments, this area common
Skilled artisans appreciate that the technical scheme described in foregoing embodiments still can be repaiied by it
Change, or the most some or all of technical characteristic is carried out equivalent；And these are revised or replace
Change, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (8)
1. a groove-shaped VDMOS manufacture method, it is characterised in that including:
Zone line in N-type epitaxy layer forms the first groove；
Selective epitaxial growth process is used to form p-type ion district in the first groove；
The second groove is formed respectively in the subregion of both sides, described N-type epitaxy layer ZhongPXing ion district；
Upper surface and described second grooved inner surface in described N-type epitaxy layer form gate oxide；
Deposit polycrystalline silicon layer on gate oxide in described second groove；
Form the body district of described groove-shaped VDMOS, source region, dielectric layer and metal level.
Method the most according to claim 1, it is characterised in that described in N-type epitaxy layer
Zone line forms the first groove and specifically includes:
Described N-type epitaxy layer deposits hard mask layer；
Zone line in described hard mask layer is carried out photoetching, etching, forms the first trench openings district；
The underside area in described first trench openings district is performed etching, is formed in described N-type epitaxy layer
First groove.
Method the most according to claim 1 and 2, it is characterised in that described outside described N-type
The subregion of both sides, Yan CengzhongPXing ion district forms the second groove respectively and specifically includes:
Described N-type epitaxy layer deposits hard mask layer；
The subregion of the both sides, described p-type ion district in described hard mask layer is carried out photoetching, etching,
Form the second trench openings district；
The underside area in described second trench openings district is performed etching, is formed in described N-type epitaxy layer
Second groove.
Method the most according to claim 3, it is characterised in that described first groove and described the
The degree of depth of two grooves is identical.
Method the most according to claim 4, it is characterised in that described in described N-type epitaxy layer
After middle formation the second groove, also include:
The base angle of described second groove is carried out round and smooth process；
Remove described hard mask layer.
6. according to the method described in claim 4 or 5, it is characterised in that in described p-type ion district
The dopant ion of p-type extension is boron ion, and the doping content of described p-type extension is 1E19-1E20 atom
Number/cubic centimetre.
Method the most according to claim 6, it is characterised in that described in described second groove
Gate oxide on after deposit polycrystalline silicon layer, also include:
Carry out back described polysilicon layer processing quarter, so that the upper surface of described polysilicon layer, described P
The upper surface in type ion district is with the upper surface of described N-type epitaxy layer at grade.
Method the most according to claim 7, it is characterised in that the thickness of described polysilicon layer is
6000-12000 angstrom, the thickness of described gate oxide is 400-1000 angstrom.
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| CN201510205792.0A CN106158661A (en) | 2015-04-27 | 2015-04-27 | Groove-shaped VDMOS manufacture method |
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| CN109065603A (en) * | 2018-08-02 | 2018-12-21 | 深圳市福来过科技有限公司 | A kind of transistor and preparation method thereof |
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