CN106158660A - Groove-shaped VDMOS manufacture method - Google Patents
Groove-shaped VDMOS manufacture method Download PDFInfo
- Publication number
- CN106158660A CN106158660A CN201510205791.6A CN201510205791A CN106158660A CN 106158660 A CN106158660 A CN 106158660A CN 201510205791 A CN201510205791 A CN 201510205791A CN 106158660 A CN106158660 A CN 106158660A
- Authority
- CN
- China
- Prior art keywords
- groove
- district
- type
- layer
- hard mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a kind of groove-shaped VDMOS manufacture method.The method includes: deposit hard mask layer in N-type epitaxy layer；Zone line in hard mask layer is carried out photoetching, etching, forms the first trench openings district；The underside area in the first trench openings district is performed etching, N-type epitaxy layer is formed the first groove；Growing P-type extension in hard mask layer upper surface, the first trench openings district and the first groove；CMP process is used to remove the p-type extension of hard mask layer upper surface, the p-type extension in hard mask layer and the first trench openings district, so that the first groove is formed p-type ion district；The second groove is formed respectively in the subregion of both sides, N-type epitaxy layer ZhongPXing ion district；Upper surface and the second grooved inner surface in N-type epitaxy layer form gate oxide；Deposit polycrystalline silicon layer on gate oxide in the second groove；Form the body district of groove-shaped VDMOS, source region, dielectric layer and metal level.
Description
Technical field
The present embodiments relate to semiconductor device processing technology field, particularly relate to a kind of groove-shaped
VDMOS manufacture method.
Background technology
Trench vertical dmost (is called for short: be groove-shaped VDMOS) logical
Form longitudinal diffusion range difference after crossing source ion and body ion implanting and form raceway groove, and be widely used in switch
Power supply and synchronous rectification field.Comparing plane VDMOS, groove-shaped VDMOS is owing to eliminating JFET
District, so its internal resistance is the least.But due to corner's curvature of channel bottom in groove-shaped VDMOS
Radius is little, and the breakdown voltage making groove-shaped VDMOS is relatively low.
In prior art, in order to improve the breakdown voltage of groove-shaped VDMOS, mainly take to connect at metal
The method of the region implanting p-type ion of contact hole.As it is shown in figure 1, inject P in the region of metal contact hole
After type ion, p-type ion implanted region 15 has shared the field intensity bottom part the second groove 7, makes the second ditch
Field intensity bottom groove 7 weakens, and then improves breakdown voltage.Wherein, the end of p-type ion implanted region 15
Portion closer to the second groove 7 bottom, the field intensity shared is the most.Under optimal cases, as in figure 2 it is shown, P
The bottom of the bottom of type ion implanted region 15 and the second groove 7 when same level, the second groove 7
The field intensity of bottom is the most weak, and breakdown voltage reaches the highest.
But this kind is in the method for the region implanting p-type ion raising breakdown voltage of metal contact hole, in p-type
While the degree of depth of the bottom that the bottom of ion implanted region 15 pushes the second groove 7 to, p-type ion implanted region
15 also in horizontal proliferation, thus changes the ion concentration of channel region, makes the threshold voltage of VDMOS send out
Changing, and then make groove-shaped VDMOS cisco unity malfunction.
In order to prevent the generation of this situation, as it is shown on figure 3, the spacing of two the second grooves 7 is widened,
But this makes groove-shaped VDMOS cellular density reduce, and reduces the driving force of groove-shaped VDMOS.
Summary of the invention
The embodiment of the present invention provides a kind of groove-shaped VDMOS manufacture method, is effectively increased groove-shaped
The breakdown voltage of VDMOS, the simultaneously no longer horizontal proliferation of ShiPXing ion district, it is ensured that groove-shaped
The threshold voltage unchanged of VDMOS, makes the spacing between the groove of deposit polycrystalline silicon layer constant, Jin Erwei
Hold cellular density, it is ensured that the driving force of groove-shaped VDMOS.
The embodiment of the present invention provides a kind of groove-shaped VDMOS manufacture method, including:
Described N-type epitaxy layer deposits hard mask layer；
Zone line in described hard mask layer is carried out photoetching, etching, forms the first trench openings district；
The underside area in described first trench openings district is performed etching, is formed in described N-type epitaxy layer
First groove；
P is grown in described hard mask layer upper surface, described first trench openings district and described first groove
Type extension；
Use CMP process to remove the p-type extension of described hard mask layer upper surface, described firmly cover
P-type extension in film floor and described first trench openings district so that in described first groove formed p-type from
Sub-district；
The second groove is formed respectively in the subregion of both sides, described N-type epitaxy layer ZhongPXing ion district；
Upper surface and described second grooved inner surface in described N-type epitaxy layer form gate oxide；
Deposit polycrystalline silicon layer on gate oxide in described second groove；
Form the body district of described groove-shaped VDMOS, source region, dielectric layer and metal level.
Further, method as above, described in both sides, described N-type epitaxy layer ZhongPXing ion district
Subregion form the second groove respectively and specifically include:
Described N-type epitaxy layer deposits hard mask layer；
The subregion of the both sides, described p-type ion district in described hard mask layer is carried out photoetching, etching,
Form the second trench openings district；
The underside area in described second trench openings district is performed etching, is formed in described N-type epitaxy layer
Second groove.
Further, method as above, the degree of depth phase of described first groove and described second groove
With.
Further, method as above, described in described N-type epitaxy layer, form the second groove
After, also include:
The base angle of described second groove is carried out round and smooth process；
Remove described hard mask layer.
Further, method as above, the dopant ion of the p-type extension in described p-type ion district
For boron ion, the doping content of described p-type extension is 1E19-1E20 atomic number/cubic centimetre.
Further, method as above, heavy on described gate oxide in described second groove
After long-pending polysilicon layer, also include:
Carry out back described polysilicon layer processing quarter, so that the upper surface of described polysilicon layer, described P
The upper surface in type ion district is with the upper surface of described N-type epitaxy layer at grade.
Further, method as above, the thickness of described polysilicon layer is 6000-12000 angstrom, institute
The thickness stating gate oxide is 400-1000 angstrom.
The embodiment of the present invention provides a kind of groove-shaped VDMOS manufacture method, by N-type epitaxy layer
Deposition hard mask layer；Zone line in hard mask layer is carried out photoetching, etching, forms the first groove window
Mouth region；The underside area in the first trench openings district is performed etching, N-type epitaxy layer is formed the first ditch
Groove；Growing P-type extension in hard mask layer upper surface, the first trench openings district and the first groove；Use
CMP process removes the p-type extension of hard mask layer upper surface, hard mask layer and the first groove window
P-type extension in mouth region, so that forming p-type ion district in the first groove；P-type in N-type epitaxy layer
The subregion of both sides, ion district forms the second groove respectively；Upper surface and the second ditch in N-type epitaxy layer
Groove inner surface forms gate oxide；Deposit polycrystalline silicon layer on gate oxide in the second groove；Form ditch
The body district of grooved VDMOS, source region, dielectric layer and metal level.It is effectively increased groove-shaped VDMOS
Breakdown voltage, ShiPXing ion district no longer horizontal proliferation simultaneously, it is ensured that the threshold of groove-shaped VDMOS
Threshold voltage is constant, makes the spacing between the groove of deposit polycrystalline silicon layer constant, and then it is close to maintain cellular
Degree, it is ensured that the driving force of groove-shaped VDMOS.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to reality
Execute the required accompanying drawing used in example or description of the prior art to be briefly described, it should be apparent that under,
Accompanying drawing during face describes is some embodiments of the present invention, for those of ordinary skill in the art,
On the premise of not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is first structural representation of groove-shaped VDMOS in prior art；
Fig. 2 is second structural representation of groove-shaped VDMOS in prior art；
Fig. 3 is the 3rd structural representation of groove-shaped VDMOS in prior art；
Fig. 4 is the flow chart of the present invention groove-shaped VDMOS manufacture method embodiment one；
In N-type epitaxy layer in the groove-shaped VDMOS manufacture method that Fig. 5 provides for the embodiment of the present invention one
Structural representation after upper deposition hard mask layer；
To in hard mask layer in the groove-shaped VDMOS manufacture method that Fig. 6 provides for the embodiment of the present invention one
Zone line carry out photoetching, etching, form the structural representation behind the first trench openings district；
To the first groove window in the groove-shaped VDMOS manufacture method that Fig. 7 provides for the embodiment of the present invention one
The underside area of mouth region performs etching, and forms the structural representation after the first groove in N-type epitaxy layer；
In the groove-shaped VDMOS manufacture method that Fig. 8 provides for the embodiment of the present invention one on hard mask layer
Surface, the structural representation delayed outside growing P-type in the first trench openings district and the first groove；
The groove-shaped VDMOS manufacture method that Fig. 9 provides for the embodiment of the present invention one uses chemical machinery
Glossing removes the p-type extension of hard mask layer upper surface, in hard mask layer and the first trench openings district
P-type extension, so that forming the structural representation behind p-type ion district in the first groove；
In N-type extension in the groove-shaped VDMOS manufacture method that Figure 10 provides for the embodiment of the present invention one
The subregion of both sides, Ceng ZhongPXing ion district forms the structural representation after the second groove respectively；
In N-type extension in the groove-shaped VDMOS manufacture method that Figure 11 provides for the embodiment of the present invention one
The upper surface of layer and the second grooved inner surface form the structural representation after gate oxide；
In the groove-shaped VDMOS manufacture method that Figure 12 provides for the embodiment of the present invention one in the second groove
Gate oxide on structural representation after deposit polycrystalline silicon layer；
The groove-shaped VDMOS manufacture method that Figure 13 provides for the embodiment of the present invention one is formed groove-shaped
The body district of VDMOS, source region, dielectric layer and the flow chart of metal level；
Groove-shaped in the groove-shaped VDMOS manufacture method that Figure 14 provides for the embodiment of the present invention one
The N-type epitaxy layer of VDMOS is formed the structural representation behind body district；
In the groove-shaped VDMOS manufacture method Zhong Ti district that Figure 15 provides for the embodiment of the present invention one second
The two side areas of groove forms the structural representation after source region；
In the groove-shaped VDMOS manufacture method that Figure 16 provides for the embodiment of the present invention one above source region
Gate oxide on dielectric layer the structural representation after removing gate oxide；
The groove-shaped VDMOS manufacture method that Figure 17 provides for the embodiment of the present invention one deposit groove-shaped
Structural representation after the metal level of VDMOS；
Figure 18 is the first pass figure of the present invention groove-shaped VDMOS manufacture method embodiment two；
Figure 19 is the second flow chart of the present invention groove-shaped VDMOS manufacture method embodiment two.
Reference:
1-N type substrate 2-N type epitaxial layer 3-hard mask layer
4-the first trench openings district 5-the first groove 6-P type extension
7-the second groove 8-gate oxide 9-polysilicon layer
10-body district 11-source region 12-dielectric layer
13-front metal layer 14-metal layer on back 15-P type ion implanted region
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with this
Accompanying drawing in bright embodiment, is clearly and completely described the technical scheme in the embodiment of the present invention,
Obviously, described embodiment is a part of embodiment of the present invention rather than whole embodiments.Based on
Embodiment in the present invention, those of ordinary skill in the art are obtained under not making creative work premise
The every other embodiment obtained, broadly falls into the scope of protection of the invention.
Embodiment one
Fig. 4 is the flow chart of the present invention groove-shaped VDMOS manufacture method embodiment one, as shown in Figure 4,
The groove-shaped VDMOS manufacture method that the present embodiment provides includes:
Step 101, deposits hard mask layer 3 in N-type epitaxy layer 2.
In the present embodiment, N-type epitaxy layer 2 is grown in N-type substrate 1.Wherein, N-type substrate 1 is
Heavily doped N-type substrate, N-type epitaxy layer 2 is lightly doped n type epitaxial layer.Concrete N-type substrate 1
Doping content and the doping content of N-type epitaxy layer 2 identical with doping content of the prior art,
This repeats the most one by one.
In the present embodiment, in N-type epitaxy layer 2, the hard mask layer 3 of deposition can be silicon dioxide layer.Heavy
Long-pending technique can be low-pressure chemical vapor deposition.The thickness of the hard mask layer of deposition can be
4000-7000 angstrom.Wherein, the groove-shaped VDMOS manufacture method that Fig. 5 provides for the embodiment of the present invention one
In in N-type epitaxy layer, deposit the structural representation after hard mask layer.
Step 102, carries out photoetching, etching to the zone line in hard mask layer 3, forms the first groove
Window region 4.
In the present embodiment, use photoetching, etching technics, etch away the hard mask layer 3 of zone line,
Define the first trench openings district 4.Wherein the first groove 5 is the groove for forming p-type ion district.
First trench openings district 4 is the window region of the first groove formed after performing etching.Fig. 6 is this
Zone line in hard mask layer is entered by the groove-shaped VDMOS manufacture method that bright embodiment one provides
Row photoetching, etching, form the structural representation behind the first trench openings district, as shown in Figure 6, first
The cross section in trench openings district 4 is rectangle.
Alternatively, in the present embodiment, etching technics can use dry etch process.
Step 103, performs etching, in N-type epitaxy layer the underside area in the first trench openings district 4
Form the first groove 5.
In the present embodiment, dry etch process can be used, the first trench openings district 4 underside area is carried out
Etching, forms the first groove 5 in N-type epitaxy layer 2.Wherein, the cross sectional shape of the first groove 5 is
Rectangle, the degree of depth of the first groove 4 is less than the thickness of N-type epitaxy layer 2.Wherein, Fig. 7 is that the present invention is real
Execute in the groove-shaped VDMOS manufacture method that example one provides and the underside area in the first trench openings district is carried out
Etching, forms the structural representation after the first groove in N-type epitaxy layer.As it is shown in fig. 7, the first ditch
Groove 5 is positioned at the underface in the first trench openings district 4, the side of the first groove 5 and the first trench openings district
The side of 4 is in the same plane.
Step 104, raw in hard mask layer 3 upper surface, the first trench openings district 4 and the first groove 5
Long p-type extension 6.
In the present embodiment, use epitaxial growth technology in hard mask layer 3 upper surface, the first trench openings district
4 and first growing P-type extensions 6 in groove 5.Wherein, the dopant ion in p-type extension 6 can be boron
Ion.Wherein, firmly in the groove-shaped VDMOS manufacture method that Fig. 8 provides for the embodiment of the present invention one
Mask layer upper surface, the structural representation delayed outside growing P-type in the first trench openings district and the first groove,
As shown in Figure 8, in the present embodiment, p-type extension 6 is filled with the first trench openings district 4 and the first groove 5.
Step 105, uses CMP process to remove the p-type extension 6 of hard mask layer 3 upper surface,
P-type extension 6 in hard mask layer 3 and the first trench openings district 4, so that forming P in the first groove 5
Type ion district.
In the present embodiment, (Chemical Mechanical Polishing is called for short CMP process
CMP) it is the course of processing being obtained smooth surface by chemistry and mechanical force, in the present embodiment, uses chemistry
Glossing removes the p-type extension 6 of hard mask layer 3 upper surface, hard mask layer 3 and the first trench openings
P-type extension 6 in district 4, so that forming p-type ion district in the first groove 5, substantially increases polishing
Precision and polishing velocity, improve the quality of polishing, reduce production cost.
In the present embodiment, the first groove 5 and p-type extension 6 constitute p-type ion district.Wherein, Fig. 9
For the groove-shaped VDMOS manufacture method that the embodiment of the present invention one provides uses CMP process
The p-type extension of removal hard mask layer upper surface, the p-type extension in hard mask layer and the first trench openings district,
So that the first groove is formed the structural representation behind p-type ion district.
Step 106, forms second respectively in the subregion of both sides, N-type epitaxy layer 2 ZhongPXing ion district
Groove 7.
In the present embodiment, form respectively in the subregion of both sides, N-type epitaxy layer 2 ZhongPXing ion district
The technique used during two grooves 7 can be photoetching, etching technics, it is also possible to for other technique, this reality
Execute example this is not limited.
In the present embodiment, the second groove 7 is the groove for depositing polysilicon layer.Wherein, Figure 10 is this
In N-type epitaxy layer ZhongPXing ion district in the groove-shaped VDMOS manufacture method that inventive embodiments one provides
The subregion of both sides forms the structural representation after the second groove, as shown in Figure 10, the second groove respectively
The cross sectional shape of 7 is rectangle, and the degree of depth of the second groove 7 is less than the thickness of N-type epitaxy layer 2.P-type from
Sub-district respectively and has spacing between the second groove 7.
Step 107, upper surface and the second groove 7 inner surface in N-type epitaxy layer 2 form gate oxide 8.
In the present embodiment, the upper surface of N-type epitaxy layer 2 is the N-type epitaxy layer 2 removing the second groove 7
Upper surface.The thickness of the gate oxide 8 in the present embodiment can be 400-1000 angstrom.Wherein, Figure 11
For in the groove-shaped VDMOS manufacture method that the embodiment of the present invention one provides at the upper table of N-type epitaxy layer
Face and the second grooved inner surface form the structural representation after gate oxide.
Step 108, deposit polycrystalline silicon layer 9 on the gate oxide 8 in the second groove 7.
In the present embodiment, the thickness of the polysilicon layer 9 of deposition on the gate oxide 8 in the second groove 7
It it is 6000～12000 angstroms.Wherein, the groove-shaped VDMOS that Figure 12 provides for the embodiment of the present invention one manufactures
Structural representation after deposit polycrystalline silicon layer on gate oxide in the second groove in method.
Step 109, forms the body district 10 of groove-shaped VDMOS, source region 11, dielectric layer 12 and metal level.
Wherein, metal level includes front metal layer 13 and metal layer on back 14.
In the present embodiment, the groove-shaped VDMOS manufacture method that Figure 13 provides for the embodiment of the present invention one
The body district of the groove-shaped VDMOS of middle formation, source region, dielectric layer and the flow chart of metal level, such as Figure 13
Shown in, step 109 particularly may be divided into following four step and performs.
Step 109a, forms body district 10 in the N-type epitaxy layer 2 of groove-shaped VDMOS.
Specifically, when forming the body district 10 of groove-shaped VDMOS, use p-type ion implantation technology,
Forming body district 10, the p-type ion wherein injected can be boron ion, and dosage can be 1.0E13-1.0E15
Individual/square centimeter, energy can be 60-120KEV, then carries out high temperature and drives in, and temperature can be
900-1150 degree, the time of driving in can be 40～100 minutes.
In the present embodiment, in the groove-shaped VDMOS manufacture method that Figure 14 provides for the embodiment of the present invention one
The structural representation behind body district is formed in the N-type epitaxy layer of groove-shaped VDMOS, as shown in figure 14,
The body district 10 of groove-shaped VDMOS is formed in N-type epitaxy layer 2, and the thickness in body district 10 is less than outside N-type
Prolong the thickness of layer 2.
Step 109b, in body district 10, the two side areas of the second groove 7 forms source region 11.
In the present embodiment, defined the region of source region 11 by photoetching process, and use ion implanting work
Skill, injects N-type ion.The N-type ion wherein injected can be arsenic or phosphorus.The dosage injected is permissible
For 1.0E15-1.0E16/square centimeter, energy can be 50-120KEV.Then carry out ion-activated,
Ion-activated temperature can be 800～1000 degree, and the ion-activated time can be 20-60 minute.
In the present embodiment, the groove-shaped VDMOS manufacture method that Figure 15 provides for the embodiment of the present invention one
Structural representation after the two side areas of the second groove forms source region in Zhong Ti district.As shown in figure 15,
Source region 11 is formed at the two side areas of the second groove 7 in body district 10.
Step 109c, dielectric layer 12 on the gate oxide 8 above source region 11.
In the present embodiment, dielectric layer 12 can be silicon dioxide layer or doped with boron and the silicon dioxide of phosphorus
Layer.
In the present embodiment, the groove-shaped VDMOS manufacture method that Figure 16 provides for the embodiment of the present invention one
In dielectric layer the structural representation after removing gate oxide on gate oxide above source region
Figure.As shown in figure 16, on the gate oxide 8 above source region 11 after dielectric layer 12, carry out
Aperture layer photoetching and etching technics, concrete aperture layer photoetching and etching technics are prior art, at this no longer
Repeat one by one.
Step 109d, deposits the metal level of groove-shaped VDMOS.
In the present embodiment, metal level includes: front metal layer 13 and metal layer on back 14.Wherein, just
Face metal level 13 can be Al-Si-Cu alloy, forms source metal, and thickness can be 2-4 micron, the back of the body
Face metal level 14 can be titanium nickeline composite bed, forms drain metal layer.Wherein, Figure 17 is the present invention
After the groove-shaped VDMOS manufacture method that embodiment one provides deposits the metal level of groove-shaped VDMOS
Structural representation.
The groove-shaped VDMOS manufacture method that the present embodiment provides, hard by deposition in N-type epitaxy layer
Mask layer；Zone line in hard mask layer is carried out photoetching, etching, forms the first trench openings district；
The underside area in the first trench openings district is performed etching, N-type epitaxy layer is formed the first groove；?
Hard mask layer upper surface, growing P-type extension in the first trench openings district and the first groove；Use chemistry machine
Tool glossing removes the p-type extension of hard mask layer upper surface, in hard mask layer and the first trench openings district
P-type extension so that in the first groove formed p-type ion district；In N-type epitaxy layer ZhongPXing ion district
The subregion of both sides forms the second groove respectively；Table in the upper surface and the second groove of N-type epitaxy layer
Face forms gate oxide；Deposit polycrystalline silicon layer on gate oxide in the second groove；Formed groove-shaped
The body district of VDMOS, source region, dielectric layer and metal level.It is effectively increased hitting of groove-shaped VDMOS
Wear voltage, simultaneously because have employed outside the p-type that CMP process removes hard mask layer upper surface
Prolong, the p-type extension in hard mask layer and the first trench openings district so that in the first groove formed p-type from
Sub-district, ShiPXing ion district no longer horizontal proliferation, it is ensured that the threshold voltage unchanged of groove-shaped VDMOS,
And keep the spacing between the first groove and the second groove, between making between the groove of deposit polycrystalline silicon layer
Away from constant, and then maintain cellular density, it is ensured that the driving force of groove-shaped VDMOS.
Embodiment two
Figure 18 is the first pass figure of the present invention groove-shaped VDMOS manufacture method embodiment two, such as figure
Shown in 18, the groove-shaped VDMOS manufacture method that the present embodiment provides includes:
Step 201, deposits hard mask layer 3 in N-type epitaxy layer 2.
Step 202, carries out photoetching, etching to the zone line in hard mask layer 3, forms the first groove
Window region 4.
Step 203, performs etching, in N-type epitaxy layer the underside area in the first trench openings district 4
Form the first groove 5.
Step 204, grows in hard mask layer 3 upper surface, the first trench openings district 4 and the first groove 5
P-type extension 6.
Step 205, uses CMP process to remove the p-type extension 6 of hard mask layer 3 upper surface,
P-type extension 6 in hard mask layer 3 and the first trench openings district 4 so that in the first groove 5 formed p-type from
Sub-district.
Preferably, the dopant ion of the p-type extension 6 in p-type ion district in the present embodiment is boron ion,
The doping content of p-type extension is 1E19-1E20 atomic number/cubic centimetre.
In the present embodiment, step 201-step 205 is identical, at this with step 101-step 105 of the present invention
Repeat the most one by one.
Step 206, forms the second ditch respectively in the subregion of both sides, N-type epitaxy layer 2 ZhongPXing ion district
Groove 7.
Further, the step 206 in the present embodiment can be divided into three below step to perform.Figure 19
For the second flow chart of the present invention groove-shaped VDMOS manufacture method embodiment two, as shown in figure 19,
Step 206 includes:
Step 206a, deposits hard mask layer 3 in N-type epitaxy layer 2.
In the present embodiment, step 206a is identical with the technique of step 201, and this is no longer going to repeat them.
Step 206b, carries out photoetching, quarter to the subregion of the both sides, p-type ion district in hard mask layer 3
Erosion, forms the second trench openings district.
In the present embodiment, use photoetching, etching technics, etch away and hard mask layer 3 is positioned at p-type ion
The hard mask layer 3 of the subregion of both sides, district, defines the second trench openings district.Wherein the second groove 7
For the groove for deposit polycrystalline silicon layer, the second trench openings district is the formed after performing etching
The window region of two grooves.
Alternatively, in the present embodiment, etching technics can use dry etch process.
In the present embodiment, the second groove 7 is positioned at the underface in the second trench openings district, the second groove 7
Side is in the same plane with the side in the second trench openings district.
Step 206c, performs etching the underside area in the second trench openings district, in N-type epitaxy layer 2
Middle formation the second groove 7.
In the present embodiment, dry etch process can be used, the underside area in the second trench openings district is entered
Row etching, forms the second groove 7 in 2 in N-type epitaxy layer.Wherein, the cross sectional shape of the second groove 7
For rectangle, the degree of depth of the second groove 7 is less than the thickness of N-type epitaxy layer 2.
Preferably, in the present embodiment, the first groove 5 is identical with the degree of depth of the second groove 7.
In the present embodiment, after forming p-type ion district, p-type ion district can share for second groove 7 end
The field intensity in portion, thus improve breakdown voltage, the bottom of the first groove 5 is closer to the end of the second groove 7
Portion, the field intensity shared is the most, when the first groove 5 is identical with the degree of depth of the second groove 7, the i.e. first groove
The bottom of bottom and the second groove when being positioned at same level, the field intensity of the second channel bottom is the most weak, hits
Wear voltage and reach the highest.
Step 207, carries out round and smooth process to the base angle of the second groove 7.
In the present embodiment, owing to the base angle of the second groove 7 is right angle, radius of curvature is little, causes breakdown potential
Press relatively low, so after the base angle of the second groove 7 is carried out round and smooth process, making the base angle of the second groove 7
Curvature increases, and further increases the breakdown voltage of this groove-shaped VDMOS.
In the present embodiment, after the base angle of the second groove 7 is carried out round and smooth process, use in prior art
Method remove hard mask layer 3.
Step 208, upper surface and the second groove 7 inner surface in N-type epitaxy layer 2 form gate oxide 8.
Step 209, deposit polycrystalline silicon layer 9 on the gate oxide 8 in the second groove 7.
In the present embodiment, step 208-step 209 is implemented with the present invention groove-shaped VDMOS manufacture method
Step 107-step 108 in example one is identical, and this is no longer going to repeat them.
Step 210, carries out back polysilicon layer 9 processing quarter.
In the present embodiment, polysilicon layer 9 is carried out back quarter process after, make polysilicon layer 9 upper surface,
The upper surface in p-type ion district is with the upper surface of N-type epitaxy layer 2 at grade.
Step 211, forms the body district 10 of groove-shaped VDMOS, source region 11, dielectric layer 12 and metal level.
In the present embodiment, in step 211 and the present invention groove-shaped VDMOS manufacture method embodiment one
Step 109 is identical, and this is no longer going to repeat them.
The groove-shaped VDMOS manufacture method provided in the present embodiment, the degree of depth of the first groove and second
The degree of depth of groove is identical, and the base angle of the second groove is carried out round and smooth process, can improve ditch further
The breakdown voltage of grooved VDMOS.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, rather than right
It limits；Although the present invention being described in detail with reference to foregoing embodiments, this area common
Skilled artisans appreciate that the technical scheme described in foregoing embodiments still can be repaiied by it
Change, or the most some or all of technical characteristic is carried out equivalent；And these are revised or replace
Change, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (7)
1. a groove-shaped VDMOS manufacture method, it is characterised in that including:
Described N-type epitaxy layer deposits hard mask layer；
Zone line in described hard mask layer is carried out photoetching, etching, forms the first trench openings district；
The underside area in described first trench openings district is performed etching, is formed in described N-type epitaxy layer
First groove；
P is grown in described hard mask layer upper surface, described first trench openings district and described first groove
Type extension；
Use CMP process to remove the p-type extension of described hard mask layer upper surface, described firmly cover
P-type extension in film floor and described first trench openings district so that in described first groove formed p-type from
Sub-district；
The second groove is formed respectively in the subregion of both sides, described N-type epitaxy layer ZhongPXing ion district；
Upper surface and described second grooved inner surface in described N-type epitaxy layer form gate oxide；
Deposit polycrystalline silicon layer on gate oxide in described second groove；
Form the body district of described groove-shaped VDMOS, source region, dielectric layer and metal level.
Method the most according to claim 1, it is characterised in that described in described N-type epitaxy layer
The subregion of both sides, ZhongPXing ion district forms the second groove respectively and specifically includes:
Described N-type epitaxy layer deposits hard mask layer；
The subregion of the both sides, described p-type ion district in described hard mask layer is carried out photoetching, etching,
Form the second trench openings district；
The underside area in described second trench openings district is performed etching, is formed in described N-type epitaxy layer
Second groove.
Method the most according to claim 2, it is characterised in that described first groove and described the
The degree of depth of two grooves is identical.
Method the most according to claim 3, it is characterised in that described in described N-type epitaxy layer
After middle formation the second groove, also include:
The base angle of described second groove is carried out round and smooth process；
Remove described hard mask layer.
5. according to the method described in claim 3 or 4, it is characterised in that in described p-type ion district
The dopant ion of p-type extension is boron ion, and the doping content of described p-type extension is 1E19-1E20 atom
Number/cubic centimetre.
Method the most according to claim 5, it is characterised in that described in described second groove
Gate oxide on after deposit polycrystalline silicon layer, also include:
Carry out back described polysilicon layer processing quarter, so that the upper surface of described polysilicon layer, described P
The upper surface in type ion district is with the upper surface of described N-type epitaxy layer at grade.
Method the most according to claim 6, it is characterised in that the thickness of described polysilicon layer is
6000-12000 angstrom, the thickness of described gate oxide is 400-1000 angstrom.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510205791.6A CN106158660A (en) | 2015-04-27 | 2015-04-27 | Groove-shaped VDMOS manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510205791.6A CN106158660A (en) | 2015-04-27 | 2015-04-27 | Groove-shaped VDMOS manufacture method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106158660A true CN106158660A (en) | 2016-11-23 |
Family
ID=57347424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510205791.6A Pending CN106158660A (en) | 2015-04-27 | 2015-04-27 | Groove-shaped VDMOS manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106158660A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109037074A (en) * | 2018-08-02 | 2018-12-18 | 深圳市诚朗科技有限公司 | A kind of production method of transistor |
| CN109037073A (en) * | 2018-08-02 | 2018-12-18 | 深圳市诚朗科技有限公司 | A kind of transistor and preparation method thereof |
| CN109065603A (en) * | 2018-08-02 | 2018-12-21 | 深圳市福来过科技有限公司 | A kind of transistor and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08222735A (en) * | 1995-02-17 | 1996-08-30 | Fuji Electric Co Ltd | Vertical trench misfet and manufacturing method thereof |
| KR20000016383A (en) * | 1996-06-06 | 2000-03-25 | 크리 리서치, 인코포레이티드 | Carbonized silicon metal-oxide-semiconductor field effect transistor |
| EP1359624A2 (en) * | 2002-04-30 | 2003-11-05 | NEC Electronics Corporation | Vertical type MOSFET and manufacturing method thereof |
| CN101120439A (en) * | 2004-09-08 | 2008-02-06 | 皇家飞利浦电子股份有限公司 | Semiconductor devices and methods of manufacture thereof |
| CN103123898A (en) * | 2011-11-21 | 2013-05-29 | 上海华虹Nec电子有限公司 | Manufacturing method for super junction double diffusion metal-oxide semiconductor device |
-
2015
- 2015-04-27 CN CN201510205791.6A patent/CN106158660A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08222735A (en) * | 1995-02-17 | 1996-08-30 | Fuji Electric Co Ltd | Vertical trench misfet and manufacturing method thereof |
| KR20000016383A (en) * | 1996-06-06 | 2000-03-25 | 크리 리서치, 인코포레이티드 | Carbonized silicon metal-oxide-semiconductor field effect transistor |
| EP1359624A2 (en) * | 2002-04-30 | 2003-11-05 | NEC Electronics Corporation | Vertical type MOSFET and manufacturing method thereof |
| CN101120439A (en) * | 2004-09-08 | 2008-02-06 | 皇家飞利浦电子股份有限公司 | Semiconductor devices and methods of manufacture thereof |
| CN103123898A (en) * | 2011-11-21 | 2013-05-29 | 上海华虹Nec电子有限公司 | Manufacturing method for super junction double diffusion metal-oxide semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109037074A (en) * | 2018-08-02 | 2018-12-18 | 深圳市诚朗科技有限公司 | A kind of production method of transistor |
| CN109037073A (en) * | 2018-08-02 | 2018-12-18 | 深圳市诚朗科技有限公司 | A kind of transistor and preparation method thereof |
| CN109065603A (en) * | 2018-08-02 | 2018-12-21 | 深圳市福来过科技有限公司 | A kind of transistor and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4939760B2 (en) | Semiconductor device | |
| CN102420133B (en) | Method for manufacturing insulated gate bipolar transistor (IGBT) device | |
| US7629616B2 (en) | Silicon carbide self-aligned epitaxial MOSFET for high powered device applications | |
| CN104637821B (en) | The manufacturing method of super-junction device | |
| JP2020507211A (en) | Gate structure of semiconductor device and manufacturing method | |
| US11545545B2 (en) | Superjunction device with oxygen inserted Si-layers | |
| CN104078364A (en) | Method of manufacturing a super-junciton semiconductor device | |
| CN101924130A (en) | Grooved MOSFET with grooved contact hole and preparation method thereof | |
| CN112103186B (en) | Process method for improving cell density of trench MOSFET and trench MOSFET structure | |
| WO2014178094A1 (en) | Semiconductor device and method for manufacturing same | |
| CN106158660A (en) | Groove-shaped VDMOS manufacture method | |
| CN114784110A (en) | Shielding gate trench MOSFET and manufacturing method thereof | |
| CN113488389B (en) | Trench gate double-layer super-junction VDMOSFET semiconductor device and preparation method thereof | |
| CN102157377B (en) | Super-junction VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) device and manufacturing method thereof | |
| KR101386132B1 (en) | Sic mosfet with trench strructures and their fabrication method | |
| CN101924103A (en) | Groove type power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and manufacturing method thereof | |
| JP4048856B2 (en) | Manufacturing method of semiconductor device | |
| CN112103187B (en) | Process method for improving cell density of trench MOSFET and trench MOSFET structure | |
| CN106158661A (en) | Groove-shaped VDMOS manufacture method | |
| CN108231886B (en) | Method of manufacturing semiconductor device and semiconductor device | |
| CN107342224B (en) | Manufacturing method of VDMOS device | |
| CN103839823B (en) | The forming method of transistor | |
| CN106328532B (en) | Manufacturing method and structure of super junction device epitaxial wafer | |
| CN116564895B (en) | Semiconductor device manufacturing method and semiconductor device | |
| CN116190241B (en) | LDMOS field effect transistor and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20161123 |
|
| RJ01 | Rejection of invention patent application after publication |