CN106155947B - A kind of implementation method of data memory module - Google Patents
A kind of implementation method of data memory module Download PDFInfo
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- CN106155947B CN106155947B CN201510158753.XA CN201510158753A CN106155947B CN 106155947 B CN106155947 B CN 106155947B CN 201510158753 A CN201510158753 A CN 201510158753A CN 106155947 B CN106155947 B CN 106155947B
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Abstract
The invention discloses a kind of implementation methods of data memory module, it is based on the memory module that the STM32F407 of STMicw Electronics and Samsung K9MDG08U5M are constituted, NAND FLASH chip selection signal is enabled by ARM first and judges status signal, the data that peripheral equipment transmits are received by serial ports interrupt mode, eventually pass through deposit NAND FLASH after L2 cache.The present invention solves the problems, such as that FSMC(can be changed static storage controller by customized choosing) in the choosing of NAND FLASH piece it is insufficient, guarantee that large capacity NAND FLASH can be used sufficiently；By the definition maximum tolerance time to determine whether the data of lack of fill one page, solve the problems, such as that NAND FLASH deficiency page of data can not store；And passes through real-time update and store NAND FLASH operation address to guarantee to continue after memory module re-powers to store.
Description
Technical field
The present invention relates to field of data storage, specifically a kind of ARM carries large capacity NAND FLASH and constitutes memory module
Implementation method.
Background technique
Storage system is widely used in various kinds of equipment, and most widely used memory is NAND FLASH, but is not had inside it
There is independent control structure, so to realize entire storage system, must just rely on other control chips, main design scheme
Have: based on ARM, based on DSP and based on FGPA.Wherein DSP power consumption is larger, and FPGA development cost is higher, and ARM has by comparison
The features such as high-performance, low-power consumption, low price, occupies the very big market share.Similar to this large capacity NAND of K9MDG08U5M
FLASH, chip selection signal have 4, and the most situation of chip selection signal at present.ARM for different model includes either ARM
For the SoC of kernel, the FSMC module for being related to NAND FLASH only has 2 chip select pins, therefore can not directly provide great Rong
4 chip selection signals needed for measuring NAND FLASH.
The operation of NAND FLASH mainly includes erasing, programming and reading, and the most key is programming operation, guarantees data
Reliability and integrality be realize store function most basic requirement.The characteristics of due to internal physical structure, NAND FLASH
Read-write as unit of page, and wipe then in blocks.When programming operation, the slow of one page size is generally opened up in the controller
It deposits, is transmitted further to NAND FLASH after the data collection in cache is full and is stored.In practical applications, data collected
It is difficult Accurate Prediction, it is more difficult to guarantee that data volume is exactly equal to the integral multiple of page capacity, thus inevitably cause last
The data of inadequate one page can not be stored in NAND FLASH, to cause loss of data.
Summary of the invention
The purpose of the present invention is to provide a kind of implementation method of data memory module, the present invention selects ARM to carry great Rong
It measures NAND FLASH and constitutes memory module, solve NAND in FSMC (variable static storage controller) by customized choosing
The problem that the choosing of FLASH piece is insufficient, ensure that large capacity NAND FLASH can be used sufficiently；By define the maximum tolerance time come
The data for judging whether lack of fill one page solve the problems, such as that NAND FLASH deficiency page of data can not store；And it is logical
It crosses real-time update and stores NAND FLASH operation address to guarantee to continue after system re-powers to store.
The technical solution for realizing the aim of the invention is as follows: a kind of implementation method of data memory module,
Step 1: NAND FLASH (2) chip selection signal on arm processor (1) is set with the corresponding pin being connected of status signal
It is set to output and input pattern, by exporting enabled NAND FLASH (2), the state of (2) NAND FLASH is judged by inputting；
Step 2:ARM processor (1) receives the data of peripheral equipment acquisition, first order data buffer storage is stored in, when deposit
When one page less than NAND FLASH (2) of data volume, first order data buffer storage is filled to one page size；
Step 3: after data storage capacity expires one page size of NAND FLASH (2), all data being transferred to the second level
Data buffer storage；
Step 4: address caching is read in address memory space (8) by variable static storage controller FSMC (7)
Data in the data buffer storage of the second level are stored according to operation address by FSMC (7) by the operation address of NAND FLASH (2)
The data space of NAND FLASH (2), and update the operation address；After the completion of address updates, it is deposited into address storage
Space (8).
In the step 2, when the one page of the data volume of deposit less than NAND FLASH (2), by first order data buffer storage
To one page size, specific step is as follows for filling:
Step 1: setting maximum tolerance time, the time are greater than the maximum time interval of peripheral equipment transmission data；
Step 2: setting timer, timer initial value are greater than the maximum tolerance time；
Step 3: when data input, timer zero,
Step 4: when timer；
Step 5: judge whether timer value reaches the maximum tolerance time, if reaching, filling data to NAND FLASH (2)
One page size；If not up to, return step 4.
In the step 4, real-time update NAND FLASH (2) operation address in address caching (6), specific steps are such as
Under:
Step 1: page address adds one；
Step 2: judging whether page address reaches block size, if reaching, page address zero, block address adds one；If not reaching
It arrives, then return step 1；
Step 3: judging whether block address reaches piece size, if reaching, block address zero, piece numerical selection adds one；If not reaching
It arrives, then return step 1；
Step 4: judging whether piece numerical selection reaches most large stretch of numerical selection, if reaching, prompt to go beyond the scope and report an error；If not reaching
It arrives, then return step 1.
The NAND FLASH (2) selects the NAND FLASH of four pieces choosing.
Compared with prior art, the present invention its remarkable advantage: 1, the present invention is made by oneself by abandoning ARM pin multiplexing function
Adopted FLASH status signal, the problem that very good solution piece choosing is insufficient；2, by the customized maximum tolerance time, and to deficiency
The data of one page are filled to one page, ensure that the data of insufficient one page can also be stored；3, operatively to NAND FLASH
Location real-time update, and operation address is stored, address is read after re-powering continues to operate.
Detailed description of the invention
Fig. 1 is general structure schematic diagram of the invention.
Fig. 2 is that STM32F407 of the invention connects block diagram with K9MDG08U5M.
Fig. 3 is secondary data caching operation schematic diagram.
Fig. 4 is that address updates flow chart.
Fig. 5 is data filling flow chart.
Specific embodiment
The memory module that the present invention is constituted using the STM32F407 of STMicw Electronics and Samsung K9MDG08U5M is base
Plinth, enables NAND FLASH chip selection signal by ARM first and judges status signal, and the data that peripheral equipment transmits are passed through string
Mouth interrupt mode receives, and eventually passes through deposit NAND FLASH after L2 cache.
The data memory module realized using the method for the present invention, including arm processor and NAND FLASH, arm processor
Including data buffer storage, address caching, FSMC and FLASH state, NAND FLASH includes address memory space, data space
And state).Data buffer storage and address caching are respectively used to temporal data information and address information.Arm processor by FSMC with
NAND FLASH carries out data transmitting, is controlled by FLASH state NAND FLASH.Address memory space and data are deposited
The data of NAND FLASH operation address and peripheral equipment acquisition are stored respectively in storage space.Peripheral equipment is controlled by arm processor
Input and NAND FLASH storage.
Above-mentioned ARM selects the STM32F407 of STMicw Electronics, this microprocessor has needed for NAND FLASH
FSMC.NAND FLASH selects the biggish K9MDG08U5M of capacity, this NAND FLASH is 8 storage cores of Samsung
Piece, capacity are up to 16G Bytes.It include 4 inside K9MDG08U5M, every has 8192 pieces, and every piece has page 128, stores with page
For unit.
Above-mentioned arm processor includes two groups of APB buses: APB1 and APB2, receives peripheral equipment by APB bus and is acquired
Data.Collected data are temporarily stored in data buffer storage through ahb bus again by arm processor.By FSMC data buffer storage
In data be stored in NAND FLASH.L2 cache is defined in data buffer storage, first order caching directly receives the number of peripheral equipment
According to the NAND FLASH page size that size is 2 times；Second level caching receives the data of first order caching, size NAND
FLASH pages of size.Situation is transmitted according to peripheral equipment and defines the maximum tolerance time, when interval reaches maximum tolerance time, data
When insufficient one page, data buffer storage is filled to one page size, is finally stored by NAND FLASH.
The part that above-mentioned NAND FLASH is connected with FSMC includes: I/O mouthfuls, latch signal and state.State includesWithFor chip selection signal,For mode bit, high level indicates that NAND FLASH is idle,
Low level indicates that NAND FLASH is busy.Address caching is defined in arm processor, is used to real-time update NAND FLASH operatively
Location.In order to continue to update address caching to the next address function of NAND FLASH after re-powering system
In the address caching region that also deposit NAND FLASH is fixed in time of address, and address is read before operating.
The implementation method of data memory module of the present invention realizes that steps are as follows:
Step 1, arm processor pin all have the function of substantially multiplexing, redefine the FLASH shape of NAND FLASH
State abandons defined good multiplexing function.By NAND FLASH'sWithIt is connected to the free time of arm processor
The multiplexing function of pin, the i.e. pin does not use, and corresponding pin is defined as output mode and input pattern respectively.To realize
Control of the arm processor to NAND FLASH；
Collected data are first sent to the caching of the first order in data buffer storage by step 2, peripheral equipment, slow to the first order
Data in depositing reach one page size of NAND FLASH, i.e. 4K Bytes and then pass data to second level caching.It is logical
It crosses FLASH state and enables the piece choosing that NAND FLASH needs to operate, when mode bit indicates idle, deposit the second level is data cached
Enter the data space of NAND FLASH.For the maximum time interval of peripheral data transmission, a maximum appearance is defined
Bear the time, timer is zeroed and starts timing while a frame data receive, and when next frame data receiver is zeroed again.If
Timer reaches the maximum tolerance time, then it is assumed that data acquisition terminates, and fills out to the data of data buffer storage deficiency one page size
It fills, carries out next operation after the completion of filling again；
Step 3, in order to enable NAND FLASH continuous work, address caching is all right after each NAND FLASH work
Current address is updated, and will be in the address memory space of the address of update deposit NAND FLASH.In NAND next time
Before FLASH work, then address read, as the operation address of this task.In this form, not only guarantee NAND
FLASH can be with continuous work, while after re-powering, and operation address can be again from the address memory space of NAND FLASH
It reads, to work on.
Present invention is further described in detail with reference to the accompanying drawing.
In conjunction with Fig. 1, system is mainly made of arm processor, NAND FLASH and peripheral equipment.The number of peripheral equipment acquisition
Pass through FSMC according to first keeping in data space, after page of data amount to be collected into and be transmitted to NAND FLASH data and deposits
In storage area.NAND FLASH is controlled by FSMC and FLASH state, completes storage operation.Address storage area is used to store NAND
Operation address before FLASH can be read to the address caching of ARM and complete address update.After re-powering, ARM can be incited somebody to action
Address is read from address storage area, is obtained operation address again, is continued to store.
STM32F407 and K9MDG08U5M specifically connects such as Fig. 2.ALE and CLE is respectively that address latch and order are latched,
Because all communications between FSMC and NAND FLASH are all by 8 I/O mouthfuls of progress, in order to distinguish the specific interior of communication
Hold, needs to judge the state of ALE and CLE.Indicate that Content of Communication is address information, the table when CLE high level when ALE high level
Show that Content of Communication for order, then indicates that Content of Communication is data when being both low level.RE and WE is respectively read-write protection,
Low level is effective.Due to chip selection signal and status signal lazy weight that FSMC is carried, so these signals are respectively connected to
In software configuration output is made in piece apolegamy by idle GPIO mouth, and state is configured to input, by exporting enabled counterpiece
Choosing, input judge the working condition of current NAND FLASH.
As shown in figure 3, the data of peripheral equipment acquisition are first temporarily stored in data buffer storage, stored according to NAND FLASH by page
The characteristics of, when in caching data collection to one page when finally stored again.In order to avoid start position data is new in caching
Data cover, first order caching is defined as the sizes of page two, and after first page is filled with, data are transferred to the second level and cache and then be sent to
NAND FLASH.Freshly harvested data continue to be collected into second page, are filled with one page backpointer and skip back to the first beginning of the page, data are same
Sample caches deposit NAND FLASH through the second level.
In conjunction with Fig. 4, when in use, after the capacity of piece choosing is filled with, need to automatically switch to next choosing, into
And it works on.Corresponding operation address, i.e. page address, block address and piece choosing are directed to each operation of NAND FLASH
Number (being operated since beginning of the page, do not consider address in page).After the completion of once-through operation, it should update operation address and carry out corresponding
Judgement.It include 4 inside K9MDG08U5M, every includes 8192 pieces, and every piece is constituted by page 128, therefore block size is 128, piece
Size 8192, size of devices 4, initial address are all since 0.When address updates, page address, block address and piece are successively updated
Numerical selection, when an address reaches maximum value, high order address adds one to address zero simultaneously.
Timer can be used in order to guarantee that the data of insufficient one page can also normally be stored in NAND FLASH in conjunction with Fig. 5
Judged, reached the maximum tolerance time when the time, that is, is thought there is no data entrance, caching filling 0xFF is big to one page
It is small.The initial value of timer is simultaneously not equal to zero, but is defined as greater than the value of maximum tolerance time.Since it is considered that program starts it
Peripheral equipment not necessarily just generates data at once afterwards, is also filled when entering in order to avoid initially not data, so meter
When device selection since it is biggish value timing.Peripheral equipment receives data, when there is data to enter, generates interruption, program executes
Service function is interrupted, while timer is zeroed.When next frame data enter, generation interruption, timer are zeroed again again.If
Enter in certain time without data, the value of timer reaches the maximum tolerance time, that is, thinks that data receiving finishes, if caching is not
Enough one page sizes then fill data to one page.
Claims (4)
1. a kind of implementation method of data memory module, it is characterised in that specific step is as follows:
Step 1: setting NAND FLASH (2) chip selection signal on arm processor (1) to the corresponding pin being connected of status signal
Output and input pattern judge the state of (2) NAND FLASH by inputting by exporting enabled NAND FLASH (2)；
Step 2:ARM processor (1) receives the data of peripheral equipment acquisition, first order data buffer storage is stored in, when the data of deposit
When measuring one page less than NAND FLASH (2), first order data buffer storage is filled to one page size；
Step 3: after data storage capacity expires one page size of NAND FLASH (2), all data being transferred to second level data
Caching；
Step 4: address caching is by can be changed the NAND in static storage controller FSMC (7) reading address memory space (8)
Data in the data buffer storage of the second level are stored in NAND by FSMC (7) according to operation address by the operation address of FLASH (2)
The data space of FLASH (2), and update the operation address；After the completion of address updates, it is deposited into address memory space
(8)。
2. the implementation method of data memory module according to claim 1, it is characterised in that: in the step 2, work as deposit
One page less than NAND FLASH (2) of data volume when, by first order data buffer storage fill to one page size specific steps such as
Under:
Step 2.1: setting maximum tolerance time, the time are greater than the maximum time interval of peripheral equipment transmission data；
Step 2.2: setting timer, timer initial value are greater than the maximum tolerance time；
Step 2.3: when data input, timer zero,
Step 2.4: when timer；
Step 2.5: judging whether timer value reaches the maximum tolerance time, if reaching, fill data to NAND FLASH's (2)
One page size；If not up to, return step 4.
3. the implementation method of data memory module according to claim 1, it is characterised in that: in the step 4, in address
Cache real-time update NAND FLASH (2) operation address in (6), the specific steps are as follows:
Step 4.1: page address adds one；
Step 4.2: judging whether page address reaches block size, if reaching, page address zero, block address adds one；If not up to,
Then return step 1；
Step 4.3: judging whether block address reaches piece size, if reaching, block address zero, piece numerical selection adds one；If not up to,
Then return step 1；
Step 4.4: judging whether piece numerical selection reaches most large stretch of numerical selection, if reaching, prompt to go beyond the scope and report an error；If not reaching
It arrives, then return step 1.
4. the implementation method of data memory module according to claim 1, it is characterised in that: the NAND FLASH (2)
The NAND FLASH for selecting four pieces to select.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102543215A (en) * | 2010-12-20 | 2012-07-04 | 西安奇维测控科技有限公司 | Nand FLASH intelligent detection method based on ARM controller |
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| KR20130096881A (en) * | 2012-02-23 | 2013-09-02 | 삼성전자주식회사 | Flash memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102543215A (en) * | 2010-12-20 | 2012-07-04 | 西安奇维测控科技有限公司 | Nand FLASH intelligent detection method based on ARM controller |
Non-Patent Citations (2)
| Title |
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| NAND FLASH在大容量存储技术中的应用;陈国等;《航空计算技术》;20090331;第39卷(第2期);第113-116页 |
| 基于ARM的NAND Flash数据存储***的设计与实现;黄培花;《滨州学院学报》;20120630;第28卷(第3期);第100-103页 |
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