CN106125439B - A kind of LTPS display panel and peripheral circuit and test method - Google Patents
A kind of LTPS display panel and peripheral circuit and test method Download PDFInfo
- Publication number
- CN106125439B CN106125439B CN201610805547.8A CN201610805547A CN106125439B CN 106125439 B CN106125439 B CN 106125439B CN 201610805547 A CN201610805547 A CN 201610805547A CN 106125439 B CN106125439 B CN 106125439B
- Authority
- CN
- China
- Prior art keywords
- type transistor
- data line
- control signal
- grid
- pixel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136254—Checking; Testing
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
A kind of LTPS display panel and peripheral circuit and test method, the peripheral circuit includes: in tail end one N-type transistor of setting of every data line and a P-type transistor, the source-drain electrode of N-type transistor and P-type transistor is correspondingly connected with, wherein, N-type transistor connects data line with one end that the source-drain electrode of P-type transistor is correspondingly connected with, other end connection signal transmission line, the grid of N-type transistor and the grid of P-type transistor are separately connected corresponding control signal wire, and the signal transmssion line and the control signal wire are shorted ground wire.The present invention can save panel periphery space, realize product narrow frame design.
Description
Technical field
The invention belongs to liquid crystal display control technology fields, specifically, more particularly to a kind of LTPS display panel and outer
Enclose circuit and test method.
Background technique
Panel itself, which accumulates excessive electrostatic, in order to prevent causes route to damage, traditional LTPS (Low temperature
Poly-silicon, low temperature polycrystalline silicon) display panel is often both provided with electrostatic ESD protection structure.
The process that LTPS display panel generates electrostatic is concentrated mainly on array substrate dry etching processing procedure.Therefore, in panel
When design, can all design in every a data wire tail end has ESD structure, to protect the electrostatic generated in array substrate processing procedure.Battle array
After the completion of column basal plate making process, peripheral ESD structure is still stored in the tail end of panel, can occupy frame inner space, is unfavorable for showing
Panel narrow frame design.
Summary of the invention
In order to solve the above problem, it the present invention provides a kind of LTPS display panel and peripheral circuit and test method, is used for
Panel periphery space is saved, realizes product narrow frame design.
According to an aspect of the invention, there is provided a kind of LTPS display panel peripheral circuit, comprising:
In the tail end of every data line, one N-type transistor and a P-type transistor, the N-type transistor and the p-type are set
The source-drain electrode of transistor is correspondingly connected with,
Wherein, the N-type transistor connects data line with one end that the source-drain electrode of the P-type transistor is correspondingly connected with, separately
The grid of one end connection signal transmission line, the grid of the N-type transistor and the P-type transistor is separately connected corresponding control
Signal wire, the signal transmssion line and the control signal wire are shorted ground wire.
According to one embodiment of present invention, it is arranged between the signal transmssion line and the control signal wire and ground wire
There is cutting line, to cut off the company between the signal transmssion line and the control signal wire and ground wire according to the cutting line
It connects.
According to one embodiment of present invention,
The signal transmssion line includes three, wherein first with the N-type transistor of the data line tail end of the red pixel of driving
It is connected with P-type transistor, Article 2 is connect with the N-type transistor of the data line tail end of driving green pixel and P-type transistor, third
Item is connect with the N-type transistor of the data line tail end of the blue pixel of driving and P-type transistor.
According to one embodiment of present invention,
The control signal wire includes two, wherein first with the grid of P-type transistor all in circuit company
It connects, Article 2 is connect with the grid of N-type transistor all in the circuit.
According to one embodiment of present invention,
The signal transmssion line includes two, wherein first respectively in a pixel unit for driving RGB
The N-type transistor of three data line tail ends of three-color pixel is connected with P-type transistor, Article 2 respectively with an adjacent pixel list
For driving the N-type transistor of three data line tail ends of redgreenblue pixel to connect with P-type transistor in first.
According to one embodiment of present invention,
The control signal wire includes six, wherein first interior for driving the number of red pixel with all pixels unit
According to the grid connection of the N-type transistor of line tail end, it is used to drive the data line tail of red pixel in Article 2 and all pixels unit
The grid of the P-type transistor at end connects, for driving the N-type of the data line tail end of green pixel in Article 3 and all pixels unit
The grid of transistor connects, for driving the P-type transistor of the data line tail end of green pixel in Article 4 and all pixels unit
Grid connection, for driving the grid of the N-type transistor of the data line tail end of blue pixel in Article 5 and all pixels unit
Connection, Article 6 are connect with the grid of the P-type transistor of the data line tail end in all pixels unit for driving blue pixel.
According to one embodiment of present invention, the N-type transistor and the P-type transistor are thin film transistor (TFT).
According to another aspect of the present invention, a kind of LTPS display panel using circuit described above is additionally provided, it is special
Sign is that same color pixel longitudinal direction same column is arranged in the panel, and lateral separation two arranges the arrangement of other colored pixels.
According to a further aspect of the invention, a kind of test method for display panel described above is additionally provided, is wrapped
It includes:
Connection between shutoff signal transmission line and control signal wire and ground wire；
Control signal is exported by control signal wire, is opened with controlling all P-type transistors and all N-type transistors
It opens；
Test signal is exported by signal transmssion line to test panel.
According to a further aspect of the invention, a kind of test method for display panel described above is additionally provided, is wrapped
It includes:
Connection between shutoff signal transmission line and control signal wire and ground wire；
Control signal is exported by control signal wire, is closed with controlling all P-type transistors and all N-type transistors
It closes；
Test signal is exported by data line to test panel.
Beneficial effects of the present invention:
The present invention merges Cell test structure with ESD structure, in array substrate process stage, the knot of the merging
Structure plays the role of protection circuit as ESD electrostatic protection apparatus；In the panel Cell lighting stage, the structure and energy of the merging
Normal test function is played, and does not influence panel later period mould group and normally shows.The structure merged in this way can effectively save face
Plate peripheral space realizes narrow frame design.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention can be by specification, right
Specifically noted structure is achieved and obtained in claim and attached drawing.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, required in being described below to embodiment
Attached drawing does simple introduction:
Fig. 1 is a kind of LTPS panel circuit structural schematic diagram in the prior art；
Fig. 2 is DE-Mux time diagram of the Fig. 1 in the Cell lighting stage；
Fig. 3 is LTPS panel circuit design circuit diagram according to an embodiment of the invention；
Fig. 4 is LTPS panel circuit design circuit diagram according to another embodiment of the invention.
Specific embodiment
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and examples, how to apply to the present invention whereby
Technological means solves technical problem, and the realization process for reaching technical effect can fully understand and implement.It needs to illustrate
As long as not constituting conflict, each feature in each embodiment and each embodiment in the present invention can be combined with each other,
It is within the scope of the present invention to be formed by technical solution.
It is as shown in Figure 1 a kind of tradition LTPS panel circuit structural schematic diagram in the prior art, peripheral circuit includes ESD
Structure and test circuit.As shown in Figure 1, ESD structure is commonly designed in the opposite side of data line driving multiplex electronics DE-mux.
In array substrate process stage, when current potential is excessively high on data line, the P-type transistor P-TFT of ESD structure middle and upper part point is opened,
The positive charge export that will build up on；If on data line when hypopotenia, the N-type transistor N-TFT of ESD structure middle-lower part is opened
It opens, the negative electrical charge export that will build up on.
In the Cell lighting stage, there is no accumulation of static electricity, ESD structure no longer plays a role, and DE-Mux starts normal work
Make.DE-Mux passes through odd number column data line ODD, even number column data line EVEN output signal, the normal display of Lai Shixian panel.Such as
Fig. 2 show the driver' s timing figure of Cell lighting stage DE-Mux in traditional design.When panel is normally shown, CK01 is in height
During level, ckx01, ckx02, ckx03 are successively opened, and control RGB data line output signal.In the peripheral circuit of entire panel
In structure, the measurement circuit for Cell lighting test occupies panel major part space, is unfavorable for the narrow frame design of panel.
In order to solve the above problem, the present invention provides a kind of novel LTPS display panel peripheral circuit, Cell is tested
Structure is merged with ESD structure.In array substrate process stage, the structure of the merging rises as ESD electrostatic protection apparatus
To the effect of protection circuit；In the panel Cell lighting stage, the structure of the merging can play normal test function again, and not
Panel later period mould group is influenced normally to show.The structure merged in this way can effectively save panel periphery space, realize narrow frame design.
The LTPS display panel peripheral circuit includes brilliant in tail end one N-type transistor of setting of every data line and a p-type
The source-drain electrode of body pipe, N-type transistor and P-type transistor is correspondingly connected with, N-type transistor and P-type crystal as shown in Figure 3 and Figure 4
Pipe connecting structure.Wherein, N-type transistor connects data line with one end that the source-drain electrode of P-type transistor is correspondingly connected with, and the other end connects
Signal transmssion line is connect, the grid of N-type transistor and the grid of P-type transistor are separately connected corresponding control signal wire, and signal passes
Defeated line and control signal wire are shorted ground wire.
In array substrate process stage, when the current potential on data line is excessively high, P-type transistor is opened, by product on data line
Tired positive charge imports ground wire；When the hypopotenia on data line, N-type transistor is opened, the negative electricity that will be accumulated on data line
Lotus imports ground wire.In the Cell lighting stage, connection between cut-off signal transmission line and control signal wire and ground wire passes through control
The opening and closing of signal line traffic control N-type transistor and P-type transistor are believed by signal transmssion line or DE-Mux output driving
Number, to test panel.In this way, Cell test structure is merged with ESD structure, it has been effectively saved outside panel
Confining space can be realized the narrow frame design of product.
In one embodiment of the invention, cutting is provided between signal transmssion line and control signal wire and ground wire
Line, to according to the connection between the cutting line shutoff signal transmission line and control signal wire and ground wire.Specifically, such as Fig. 3 and
Dotted line Cut line in Fig. 4.Signal is transmitted along cutting line by cutting or edging processing procedure in Cell process stage
Line and control signal wire are short-circuited with the connecting line between ground wire and remove, thus disconnect each signal transmssion line and each control signal wire it
Between connection.
In one embodiment of the invention, which includes three, wherein first with the red pixel of driving
The N-type transistor of data line tail end is connected with P-type transistor, the N-type crystal of the data line tail end of Article 2 and driving green pixel
Pipe is connected with P-type transistor, and Article 3 is connect with the N-type transistor of the data line tail end of the blue pixel of driving and P-type transistor.Tool
Body, as shown in figure 3, the N-type transistor and P-type transistor of signal transmssion line CT-R and the data line tail end of the red pixel of driving connect
It connects, signal transmssion line CT-G is connect with the N-type transistor of the data line tail end of driving green pixel and P-type transistor, signal transmission
Line CT-B is connect with the N-type transistor of the data line tail end of the blue pixel of driving and P-type transistor.Also, pass through 3 bars of setting
Transmission line carrys out the pixel transmission signal to different colours respectively, can to different colours pixel corresponding line connection carry out respectively
Test.
In one embodiment of the invention, control signal wire include two, wherein first with P all in circuit
The grid of transistor npn npn connects, and Article 2 is connect with the grid of N-type transistor all in circuit.Specifically, as shown in figure 3,
Control signal wire xck-1 is connect with the grid of N-type transistor all in circuit, for controlling the unlatching of all N-type transistors
And closing, control signal wire xck-2 are connect with the grid of P-type transistor all in circuit, for controlling all P-type transistors
Opening and closing.
In array substrate processing procedure, peripheral circuit structure as shown in Figure 3 is such as used, if data line current potential is excessively high,
The P-type transistor of right half is opened, and positive charge is exported.If when data line hypopotenia, the N-type transistor of left half is opened
It opens, negative electrical charge is exported.The effect of ESD protection can thus be played.
In Cell process stage, peripheral circuit structure as shown in Figure 3 is such as used, passes through cutting or edging processing procedure, edge
Cut line directly removes the line of short circuit, so that signal transmssion line CT-R, CT-G, CT-B and control signal wire xck-1,
Xck-2 is disconnected between each other and between ground wire.In Cell lighting, control signal wire xck-1, xck-2 control crystal
Pipe is opened, by CT-R, CT-G, CT-B to plane transport signal.In mould group Module lighting, control signal wire xck-1,
Xck-2 controls transistor and closes, and is normally shown by Fanout route and DE-Mux route driving panel.In this way, without in face
Plate periphery additional designs Cell tests structure, and by Cell test structure in conjunction with the ESD structure of tail end, panel is greatly saved
Design space is conducive to narrow frame design.
In one embodiment of the invention, signal transmssion line include two, wherein first respectively with a pixel list
For driving the N-type transistor of three data line tail ends of redgreenblue pixel to connect with P-type transistor in first, Article 2 point
Not in an adjacent pixel unit for drive redgreenblue pixel three data line tail ends N-type transistor and p-type
Transistor connection.Specifically, as shown in figure 4, the first bars transmission line CT-DO respectively in left pixel unit for driving
The N-type transistor of three data line tail ends of redgreenblue pixel is connected with P-type transistor, Article 2 signal transmssion line CT-
DE respectively in right pixel unit for drive redgreenblue pixel three data line tail ends N-type transistor and p-type
Transistor connection.
In one embodiment of the invention, control signal wire include six, wherein first with all pixels unit in
The grid of the N-type transistor of the data line tail end of red pixel is driven to connect, the red pixel of driving in Article 2 and all pixels unit
Data line tail end P-type transistor grid connection, the data line tail of driving green pixel in Article 3 and all pixels unit
The grid of the N-type transistor at end connects, the P-type crystal of the data line tail end of driving green pixel in Article 4 and all pixels unit
The grid of pipe connects, and the grid of the N-type transistor of the data line tail end of blue pixel is driven to connect in Article 5 and all pixels unit
It connects, Article 6 is connect with the grid of the P-type transistor for the data line tail end for driving blue pixel in all pixels unit.
Specifically, as shown in figure 4, for driving red pixel in first control signal wire xck-1 and all pixels unit
Data line tail end N-type transistor grid connection, be used to drive in Article 2 control signal wire xck-2 and all pixels unit
Move the grid connection of the P-type transistor of the data line tail end of red pixel, Article 3 control signal wire xck-3 and all pixels unit
The grid connection of the N-type transistor of the interior data line tail end for driving green pixel, Article 4 control signal wire xck-4 and all
For driving the grid connection of the P-type transistor of the data line tail end of green pixel, Article 5 control signal wire in pixel unit
Xck-5 is connect with the grid of the N-type transistor of the data line tail end in all pixels unit for driving blue pixel, Article 6 control
Signal wire xck-6 processed is connect with the grid of the P-type transistor of the data line tail end in all pixels unit for driving blue pixel.
In this way, by six bars control lines of setting, and it is divided into one group two-by-two, 3 groups of control signal wires are formed altogether.This 3 groups of control signals
Line controls the N-type transistor and P-type transistor for driving the data line tail end of different colours pixel respectively, can control realization
The connection of different colours pixel corresponding line is tested.
In array substrate processing procedure, peripheral circuit structure as shown in Figure 4 is such as used, if data line current potential is excessively high,
The P-type transistor of right half is opened, and positive charge is exported.If when data line hypopotenia, the N-type transistor of left half is opened
It opens, negative electrical charge is exported.The effect of ESD protection can thus be played.
In Cell process stage, peripheral circuit structure as shown in Figure 4 is such as used, passes through cutting or edging processing procedure, edge
Cut line directly removes the line of short circuit, so that signal transmssion line CT-DO, CT-DE and control signal wire xck-1, xck-
2, xck-3, xck-4, xck-5, xck-6 signal wire disconnect between each other and between ground wire.In Cell lighting, control
Signal wire xck-1, xck-2, xck-3, xck-4, xck-5, xck-6 control transistor and open, by signal transmssion line CT-DO,
CT-DE is to plane transport signal.In Module lighting, control signal wire xck-1, xck-2, xck-3, xck-4, xck-5,
Xck-6 controls transistor and closes, and is normally shown by Fanout route and DE-Mux route driving panel.In this way, without in face
Plate periphery additional designs Cell tests structure, and by Cell test structure in conjunction with the ESD structure of tail end, panel is greatly saved
Design space is conducive to narrow frame design.
In one embodiment of the invention, N-type transistor and P-type transistor are thin film transistor (TFT) TFT.
According to another aspect of the present invention, a kind of LTPS using the above LTPS display panel peripheral circuit is additionally provided
Display panel, same color pixel longitudinal direction same column arrangement in the panel, lateral separation two arrange the arrangement of other colored pixels.Pixel row
Cloth is as shown in Figure 3 and Figure 4.
According to another aspect of the present invention, a kind of test method for the above LTPS display panel is additionally provided, is wrapped
It includes: the connection between shutoff signal transmission line and control signal wire and ground wire；Control signal is exported by control signal wire, with control
It makes all P-type transistors and all N-type transistors is opened；Test signal is exported by signal transmssion line to carry out to panel
Test.
According to a further aspect of the invention, another test method for being used for the above LTPS display panel is additionally provided,
It include: the connection between shutoff signal transmission line and control signal wire and ground wire；Control signal is exported by control signal wire, with
It controls all P-type transistors and all N-type transistors is closed；Test signal is exported by data line to survey to panel
Examination.
While it is disclosed that embodiment content as above but described only to facilitate understanding the present invention and adopting
Embodiment is not intended to limit the invention.Any those skilled in the art to which this invention pertains are not departing from this
Under the premise of the disclosed spirit and scope of invention, any modification and change can be made in the implementing form and in details,
But scope of patent protection of the invention, still should be subject to the scope of the claims as defined in the appended claims.
Claims (9)
1. a kind of LTPS display panel peripheral circuit, comprising:
In the tail end of every data line, one N-type transistor and a P-type transistor, the N-type transistor and the P-type crystal are set
The source-drain electrode of pipe is correspondingly connected with,
Wherein, the N-type transistor connects data line, the other end with one end that the source-drain electrode of the P-type transistor is correspondingly connected with
The grid of connection signal transmission line, the grid of the N-type transistor and the P-type transistor is separately connected corresponding control signal
Line, the signal transmssion line and the control signal wire are shorted ground wire, the signal transmssion line and the control signal wire with
Cutting line is provided between ground wire, to cut off the signal transmssion line and the control signal wire and ground according to the cutting line
Connection between line.
2. circuit according to claim 1, which is characterized in that
The signal transmssion line includes three, wherein first with the N-type transistor and P of the data line tail end of the red pixel of driving
Transistor npn npn connection, Article 2 are connect with the N-type transistor of the data line tail end of driving green pixel and P-type transistor, Article 3
It is connect with the N-type transistor of the data line tail end of the blue pixel of driving and P-type transistor.
3. circuit according to claim 2, which is characterized in that
The control signal wire includes two, wherein and first connect with the grid of P-type transistor all in the circuit,
Article 2 is connect with the grid of N-type transistor all in the circuit.
4. circuit according to claim 1, which is characterized in that
The signal transmssion line includes two, wherein first respectively in a pixel unit for driving redgreenblue
The N-type transistor of three data line tail ends of pixel is connected with P-type transistor, and Article 2 is respectively and in an adjacent pixel unit
For driving the N-type transistor of three data line tail ends of redgreenblue pixel to connect with P-type transistor.
5. circuit according to claim 4, which is characterized in that
The control signal wire includes six, wherein first interior for driving the data line of red pixel with all pixels unit
The grid of the N-type transistor of tail end connects, for driving the P of the data line tail end of red pixel in Article 2 and all pixels unit
The grid of transistor npn npn connects, for driving the N-type crystal of the data line tail end of green pixel in Article 3 and all pixels unit
The grid of pipe connects, for driving the grid of the P-type transistor of the data line tail end of green pixel in Article 4 and all pixels unit
Pole connection, Article 5 are connect with the grid of the N-type transistor of the data line tail end in all pixels unit for driving blue pixel,
Article 6 is connect with the grid of the P-type transistor of the data line tail end in all pixels unit for driving blue pixel.
6. circuit according to claim 1, which is characterized in that the N-type transistor and the P-type transistor are brilliant for film
Body pipe.
7. a kind of LTPS display panel using circuit described in any one of above claim 1-6, which is characterized in that the face
Same color pixel longitudinal direction same column is arranged in plate, and lateral separation two arranges the arrangement of other colored pixels.
8. a kind of test method for LTPS display panel described in claim 7, comprising:
Connection between shutoff signal transmission line and control signal wire and ground wire；
Control signal is exported by control signal wire, is opened with controlling all P-type transistors and all N-type transistors；
Test signal is exported by signal transmssion line to test panel.
9. a kind of test method for LTPS display panel described in claim 7, comprising:
Connection between shutoff signal transmission line and control signal wire and ground wire；
Control signal is exported by control signal wire, is closed with controlling all P-type transistors and all N-type transistors；
Test signal is exported by data line to test panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610805547.8A CN106125439B (en) | 2016-09-07 | 2016-09-07 | A kind of LTPS display panel and peripheral circuit and test method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610805547.8A CN106125439B (en) | 2016-09-07 | 2016-09-07 | A kind of LTPS display panel and peripheral circuit and test method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106125439A CN106125439A (en) | 2016-11-16 |
| CN106125439B true CN106125439B (en) | 2019-05-03 |
Family
ID=57271752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610805547.8A Active CN106125439B (en) | 2016-09-07 | 2016-09-07 | A kind of LTPS display panel and peripheral circuit and test method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106125439B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107024785B (en) * | 2017-04-21 | 2020-06-05 | 武汉华星光电技术有限公司 | Lighting fixture and lighting test method for display panel |
| CN108182895B (en) * | 2017-12-12 | 2020-06-30 | 武汉华星光电技术有限公司 | Circuit and method for detecting pixel potential in display panel and display panel |
| CN110491328B (en) * | 2019-09-02 | 2022-12-23 | 京东方科技集团股份有限公司 | Display panel, display device and driving method |
| CN110927997B (en) * | 2019-11-21 | 2022-07-12 | 武汉华星光电半导体显示技术有限公司 | Display panel test circuit and test method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002372955A (en) * | 2001-06-14 | 2002-12-26 | Hitachi Ltd | Liquid crystal display and information equipment |
| CN103676345A (en) * | 2012-09-20 | 2014-03-26 | 上海中航光电子有限公司 | Anti-static display panel |
| CN105070239A (en) * | 2015-08-27 | 2015-11-18 | 武汉华星光电技术有限公司 | Liquid crystal display panel |
| CN105185332A (en) * | 2015-09-08 | 2015-12-23 | 深圳市华星光电技术有限公司 | Liquid crystal display panel, driving circuit thereof and manufacturing method thereof |
| CN105467707A (en) * | 2016-01-29 | 2016-04-06 | 京东方科技集团股份有限公司 | Discharge circuit, array substrate, liquid crystal display panel and display device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4804926B2 (en) * | 2006-01-12 | 2011-11-02 | 富士通セミコンダクター株式会社 | Semiconductor integrated circuit |
-
2016
- 2016-09-07 CN CN201610805547.8A patent/CN106125439B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002372955A (en) * | 2001-06-14 | 2002-12-26 | Hitachi Ltd | Liquid crystal display and information equipment |
| CN103676345A (en) * | 2012-09-20 | 2014-03-26 | 上海中航光电子有限公司 | Anti-static display panel |
| CN105070239A (en) * | 2015-08-27 | 2015-11-18 | 武汉华星光电技术有限公司 | Liquid crystal display panel |
| CN105185332A (en) * | 2015-09-08 | 2015-12-23 | 深圳市华星光电技术有限公司 | Liquid crystal display panel, driving circuit thereof and manufacturing method thereof |
| CN105467707A (en) * | 2016-01-29 | 2016-04-06 | 京东方科技集团股份有限公司 | Discharge circuit, array substrate, liquid crystal display panel and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106125439A (en) | 2016-11-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106125439B (en) | A kind of LTPS display panel and peripheral circuit and test method | |
| CN105185332B (en) | Liquid crystal display panel and its drive circuit, manufacture method | |
| CN109037242A (en) | Array substrate and its manufacturing method, display panel | |
| CN103698953B (en) | A kind of array base palte, display floater and display device | |
| CN202285072U (en) | Color filter substrate, array substrate, liquid crystal display panel and display device | |
| CN103257497B (en) | There is the display pixel of the oxide thin film transistor (TFT) of the load of reduction | |
| CN102549487B (en) | Liquid crystal display panel | |
| CN107680550A (en) | A kind of array base palte, display panel and its driving method | |
| CN106448564B (en) | A kind of OLED pixel circuit and its driving method, display device | |
| CN104465675A (en) | Thin film transistor array substrate, liquid crystal panel and liquid crystal display | |
| CN106875896A (en) | A kind of source drive IC, display device and its driving method | |
| CN103399422B (en) | Signal wire and repair line method for detecting short circuit | |
| US10181275B2 (en) | Display device | |
| US20190025619A1 (en) | Test circuit for display panel and display device | |
| CN106502019A (en) | Array base palte, display device and its driving method | |
| CN108037605A (en) | A kind of liquid crystal display die set | |
| CN104635395A (en) | Panel display device | |
| CN103943082B (en) | A kind of display device and driving method thereof | |
| CN104407481A (en) | Array substrate, detection method of failure of signal line, display panel and display device | |
| CN104483795A (en) | Array substrate, array substrate detection method, display panel and display device | |
| CN104297991A (en) | Color film substrate and display device | |
| CN104620154A (en) | Display panel, display apparatus, and manufacturing method | |
| CN205539813U (en) | Display device | |
| CN104867452A (en) | Signal separator and AMOLED display device | |
| CN106531745A (en) | Thin film transistor array substrate and liquid crystal panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |