CN103676345A - Anti-static display panel - Google Patents
Anti-static display panel Download PDFInfo
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- CN103676345A CN103676345A CN201210356191.6A CN201210356191A CN103676345A CN 103676345 A CN103676345 A CN 103676345A CN 201210356191 A CN201210356191 A CN 201210356191A CN 103676345 A CN103676345 A CN 103676345A
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Abstract
The invention discloses an anti-static display panel. The anti-static display panel comprises a thin film transistor base plate which comprises at least one display area, common electrodes arranged around the at least one display area of the thin film transistor base plate and an electronic static discharge (ESD) device, wherein one end of the ESD device is connected with the common electrodes, and the other end of the ESD device is grounded. The invention further discloses a grounded protection loop circuit which is arranged on the periphery of the at least one display area of the thin film transistor base plate. One end of the ESD device is connected with the common electrodes, and the other end of the ESD device is connected with the grounded protection loop circuit. The anti-static display panel can release static electricity on the common electrodes, and avoids the problem that a driver chip can not normally display due to self protection.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly a kind of electrostatic discharge protection circuit.
Background technology
In recent years, be in information communication device or common electric equipment, all generally to adopt various display panels.
As a kind of flat-panel display device, liquid crystal display generally includes the liquid crystal layer between upper substrate, infrabasal plate and two plate bases.Conventionally, infrabasal plate is integrated with some data lines and sweep trace, and their vertical interlaceds form some unit areas, and these unit areas are defined as pixel cell.Each pixel cell mainly comprises the parts such as pixel electrode, memory capacitance and thin film transistor (TFT) (TFT).By driving circuit, to sweep trace, provide driving signal, can control the duty of thin film transistor (TFT), thus the driving signal writing pixel electrode in time data line being provided.In addition, on upper substrate, be integrated with black matrix", colored light filter membrane layer (CF) and common electrode layer.Black matrix" is used for blocking the light transmitting from the non-pixel electrode district of infrabasal plate.Colored light filter membrane layer is corresponding with the pixel region of infrabasal plate.Common electrode layer and pixel electrode and liquid crystal layer form liquid crystal capacitance.This structure has larger transmittance and the higher remarkable characteristics such as aperture opening ratio.
But, because this flat-panel monitor has poor viewing angle characteristic, thereby, new being used for overcome visual angle defect utilization be that in-plane changes horizontal component of electric field in (IPS) pattern as LCD drive method.
The LCD of IPS pattern comprises the liquid crystal layer between upper substrate, infrabasal plate and two plate bases.Infrabasal plate comprises thin film transistor (TFT) (TFT), pixel electrode and public electrode.Upper substrate comprises black matrix" and color filter.Described liquid crystal layer is driven by the horizontal component of electric field between public electrode and pixel electrode.
In the manufacturing process of display panel, easily there is the accumulation of static, if can not well solve electrostatic problem, easily product is caused to serious destruction.
In the liquid crystal display panel of thin film transistor design process of IPS pattern, conventionally in TFT side, be provided for the conductive plate (pad) of electrostatic prevention, be connected conducting with the nesa coating (ITO) of colored light filter membrane layer (CF) upper surface, when there is large electric current on CF surface, will carry out static release by this pad.Traditional is designed with two kinds, and a kind of is this pad to be connected to the public electrode (Com electrode) of periphery, viewing area, sees Fig. 1, and another kind is to be connected to earthing potential (GND current potential), sees Fig. 2.
In Fig. 1,101 represent the public electrode (com bus) of periphery, panel viewing area, and 102 represent the conductive plate (pad) for electrostatic prevention.103 for driving chip.When there is a large amount of accumulation on CF surface, the path that electric charge can be connected to public electrode 101 by conductive plate 102 carries out static release.Meanwhile, the static on thin film transistor base plate also carries out static release by public electrode 101.So when having static, CF surface electrostatic is discharged into public electrode 101 by conductive plate, current potential moment of public electrode 101 is drawn high, and easily occurs driving the self-protection of chip 103, cannot normally show.
In Fig. 2,202 represent conductive plate, and its current potential is earthing potential (GND current potential).The current potential of the current potential of conductive plate 202 and public electrode 201 is independent, and CF side static is discharged into the earth by conductive plate 202, and the static on thin film transistor base plate discharges by public electrode 201.The method has reduced the variation of public electrode current potential when having static, but the static of thin film transistor base plate self still cannot effectively be discharged.
Summary of the invention
The invention provides a kind of electrostatic prevention display panel, solve the static release And Spread of Solute of public electrode.
For this reason, the invention provides a kind of electrostatic prevention display panel, comprising:
Thin film transistor base plate is provided, and this substrate at least comprises a viewing area;
The public electrode arranging around the viewing area of described thin film transistor base plate;
One ESD device is set;
One end of described ESD device is connected with described public electrode;
The other end ground connection of described ESD device.
Preferably, described ESD device is one-level, the two poles of the earth or multipole.
Preferably, described ESD device is one-level or two-stage.
The invention provides a kind of electrostatic prevention display panel, comprising:
Thin film transistor base plate is provided, and this substrate at least comprises a viewing area;
The public electrode arranging around the viewing area of described thin film transistor base plate;
One ESD device is set;
One end of described ESD device is connected with described public electrode;
Be arranged on the protection loop of a ground connection of the periphery, viewing area of described thin film transistor base plate;
The other end of described ESD device is connected with described protection loop.
Preferably, described ESD device is one-level, the two poles of the earth or multipole.
Preferably, described ESD device is one-level or two-stage.
Preferably, the material of described protection loop is metal.
Preferably, described protection loop current potential is provided by peripheral drive circuit.
Preferably, described protection loop two-terminal-grounding.
Preferably, a colored filter is set on described thin film transistor base plate, described colored filter and described thin film transistor (TFT) arrange in opposite directions, in described colored filter inner side, one ITO conductive layer are set.
Preferably, on described protection loop, a conductive plate is set, described conductive plate is communicated with the ITO conductive layer in described colored filter outside.
Compared with prior art, the present invention has the following advantages:
In above-mentioned electrostatic prevention display panel, the public electrode in non-display area is connected with ESD device, then by ESD device, static is discharged.So, with respect to traditional electrostatic prevention display panel structure, the static on public electrode can bleed off by immediate release, avoids driving chip because self-protection causes the problem that cannot normally show.
Accompanying drawing explanation
Fig. 1 is the schematic diagram that in prior art, CF side static discharges by public electrode;
Fig. 2 is the schematic diagram that in prior art, CF side static discharges by grounded circuit;
Fig. 3 is the schematic diagram that in the present invention, the static of public electrode discharges by ESD;
Fig. 4 is the schematic diagram of one-level ESD in the present invention;
Fig. 5 is the schematic diagram of secondary ESD in the present invention;
Fig. 6 is the figure schematic diagram that in the present invention, ESD is connected with electrostatic prevention loop;
Fig. 7 (a) and Fig. 7 (b) be in the present invention IPS-LCD display panels produce and test process in CF side static and TFT static all pass through the schematic diagram of electrostatic prevention loop release electrostatic.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Embodiment mono-:
As shown in Figure 3, a kind of liquid crystal display panel of thin film transistor that the embodiment of the present invention one provides, comprise: TFT substrate 304, CF substrate 305, be arranged on the liquid crystal between described TFT substrate and CF substrate, described display panels comprises viewing area and non-display area, and described non-display area arranges around described viewing area, at described non-display area, be provided with the public electrode 301 around described viewing area.
Also comprise: electrostatic protection device (ESD device) 306, one end connects public electrode 301, other end ground connection.
Preferably, described electrostatic protection device 306 is one-level or two-stage.
Fig. 4 and Fig. 5 are the circuit diagram of the electrostatic protection device of one-level and two-stage.Electrostatic protection device shown in Fig. 4 is comprised of two thin film transistor (TFT)s; Electrostatic protection device shown in Fig. 5 is comprised of four thin film transistor (TFT)s.
As shown in Figure 4, one-level electrostatic protection device comprises: the first transistor 401, has first grid G41, the first drain D 41 and the first source S 41; And transistor seconds 402, there is second grid G42, the second drain D 42 and the second source S 42.
First grid G41 connects public electrode; The first drain D 41 connects the current potential of public electrode 301, i.e. common potential; The first drain D 41 is connected with the second drain D 42; The first source S 41 is connected with the second source S 42; The second source S 42 ground connection; Second grid G42 ground connection.While having a large amount of electric charge on public electrode; public electrode relatively has voltage; when this voltage is when opening the first transistor 401 and transistor seconds 402; the first drain D 41 and the first source S 41 are just in conducting state; the second drain D 42 and the second source S 42 are also in conducting state; thereby the electric charge on public electrode can be carried out to ground connection release, reach the object of electrostatic defending, avoid the excessive self-protection that causes driving chip of potential change of public electrode.As shown in Figure 5, secondary electrostatic protection device comprises: the first transistor 501, has first grid G51, the first drain D 51 and the first source S 51; Transistor seconds 502, has second grid G52, the second drain D 52 and the second source S 52; The 3rd transistor 503, has the 3rd grid G 53, the 3rd drain D 53 and the 3rd source S 53; The 4th transistor 504, has the 4th grid G 54, the 4th drain D 54 and the second source S 54.
First grid G51 connects public electrode; The first drain D 51 connects public electrode; The first drain D 51 is connected with the second drain D 52; The first source S 51 is connected with the 3rd source S 53; The 3rd grid G 53 ground connection; The 3rd drain D 53 ground connection; The second source S 52 is connected with the 4th source S 54; Second grid G52 is connected with the 4th grid G 54; The 4th drain D 54 ground connection.While having a large amount of electric charge on public electrode, public electrode relatively has voltage, when this voltage is even as big as opening the first transistor 501, transistor seconds 502, when the 3rd transistor 503 and the 4th transistor 504, the first drain D 51 and the first source S 51 are just in conducting state, the second drain D 52 and the second source S 52 are in conducting state, the 3rd drain D 53 and the second source S 53 are in conducting state, the 4th drain D 54 and the 4th source S 54 are all in conducting state, thereby the electric charge on public electrode can be carried out to ground connection release, reach the object of electrostatic defending, avoid the excessive self-protection that causes driving chip of public electrode potential change.
Embodiment bis-:
As shown in Figure 6, the thin film transistor base plate that second embodiment of the invention provides, at least comprises a viewing area AA, and around the non-display area of described viewing area AA; , at non-display area, be provided with around the public electrode 601 of described thin film transistor base plate viewing area; At non-display area, be also provided with an ESD device 606; Described public electrode 601 is connected with one end of described ESD device 606; At non-display area, be also provided with one around the protection loop 607 of the ground connection of described thin film transistor base plate viewing area; Described ESD device 606 other ends are connected with described protection loop 607.
The material of described protection loop 607 is metal.
The described protection loop current potential of described protection loop 607 is provided by peripheral drive circuit.
Described protection loop 607 is two-terminal-grounding at least.
In the above-mentioned liquid crystal display panel of thin film transistor that the embodiment of the present invention two provides; on the public electrode 601 of thin film transistor base plate electrostatic accumulation make to a certain extent the ESD device being connected with public electrode 601 open; thereby the static on thin film transistor base plate is discharged on protection loop 607 by public electrode 601; and then be discharged into the earth; make the static of thin film transistor base plate obtain effective release; reduced the fluctuation of the public electrode current potential that causes because of static, the demonstration that has prevented to drive chip 603 self-protections to cause is abnormal.
Embodiment tri-:
As shown in Figure 7 (a), the embodiment of the present invention three provides a kind of IPS-LCD display panel, comprising: TFT substrate 704, CF substrate 705, is arranged on the liquid crystal between described TFT substrate and CF substrate.One transparency conducting layer 708 is set on CF substrate.
As shown in Figure 7 (b) shows, described TFT substrate 704, comprises viewing area AA and non-display area, and described non-display area is around described viewing area AA.
The transparency conducting layer that conductive layer can 708 be made for ITO layer or other transparent conductive material.
In the liquid crystal display panel of thin film transistor that the embodiment of the present invention three provides, the electric charge on CF substrate 705 can accumulate on conductive layer 708, is connected to protection loop 707 and carries out static release, thereby can reach the object of ESD protection by conductive plate 702.Meanwhile, the static on thin film transistor base plate 704 can make the ESD device between public electrode 701 and protection loop 707 open, and the static on thin film transistor base plate 704 is discharged on protection loop 707 by public electrode 701, and then is discharged into ground.On discharging CF, in static, the static on TFT is effectively discharged.
The above, be only preferred embodiment of the present invention, not the present invention done to any pro forma restriction.Although the present invention discloses as above with preferred embodiment, yet not in order to limit the present invention.Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (11)
1. an electrostatic prevention display panel, comprising:
Thin film transistor base plate is provided, and this substrate at least comprises a viewing area;
The public electrode arranging around described thin film transistor base plate viewing area;
One ESD device is set;
One end of described ESD device is connected with described public electrode;
The other end ground connection of described ESD device.
2. electrostatic prevention display panel as claimed in claim 1, is characterized in that, described ESD device is one-level, the two poles of the earth or multipole.
3. electrostatic prevention display panel as claimed in claim 2, is characterized in that, described ESD device is one-level or two-stage.
4. an electrostatic prevention display panel, comprising:
Thin film transistor base plate is provided, and this substrate at least comprises a viewing area;
The public electrode arranging around described thin film transistor base plate viewing area;
One ESD device is set;
One end of described ESD device is connected with described public electrode;
Be arranged on the protection loop of a ground connection of the periphery, viewing area of described thin film transistor base plate;
The other end of described ESD device is connected with described protection loop.
5. electrostatic prevention display panel as claimed in claim 4, is characterized in that, described ESD device is one-level, the two poles of the earth or multipole.
6. electrostatic prevention display panel as claimed in claim 4, is characterized in that, described ESD device is one-level or two-stage.
7. electrostatic prevention display panel as claimed in claim 1, is characterized in that, the material of described protection loop is metal.
8. electrostatic prevention display panel as claimed in claim 1, is characterized in that, described protection loop current potential is provided by peripheral drive circuit.
9. electrostatic prevention display panel as claimed in claim 1, is characterized in that, described protection loop two-terminal-grounding.
10. electrostatic prevention display panel as claimed in claim 4, is characterized in that, a colored filter is set on described thin film transistor base plate, and described colored filter and described thin film transistor (TFT) arrange in opposite directions, in described colored filter inner side, one ITO conductive layer is set.
11. electrostatic prevention display panels as claimed in claim 10, is characterized in that, on described protection loop, a conductive plate are set, and described conductive plate is communicated with the ITO conductive layer in described colored filter outside.
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| CN201710188121.7A CN106773381B (en) | 2012-09-20 | 2012-09-20 | Anti-static display panel |
| CN201210356191.6A CN103676345B (en) | 2012-09-20 | 2012-09-20 | A kind of Anti-static display panel |
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| CN201210356191.6A CN103676345B (en) | 2012-09-20 | 2012-09-20 | A kind of Anti-static display panel |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN106773381B (en) | 2020-06-09 |
| CN106773381A (en) | 2017-05-31 |
| CN103676345B (en) | 2017-06-27 |
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