CN106098710A - A kind of array base palte and preparation method thereof, display device - Google Patents
A kind of array base palte and preparation method thereof, display device Download PDFInfo
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- CN106098710A CN106098710A CN201610763438.4A CN201610763438A CN106098710A CN 106098710 A CN106098710 A CN 106098710A CN 201610763438 A CN201610763438 A CN 201610763438A CN 106098710 A CN106098710 A CN 106098710A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The embodiment of the present invention provides a kind of array base palte and preparation method thereof, display device, relate to Display Technique field, when electrode is connected with drain electrode by via in array base palte, it is possible to reduce the drop of via area, reduce electrode and the probability that loose contact occurs that drains in this via area.This array base palte includes the thin film transistor (TFT) being arranged on underlay substrate, and be successively set on thin film transistor (TFT) the first insulating barrier, the second insulating barrier, the first electrode, at the drain electrode position of thin film transistor (TFT), first insulating barrier has the first via, second insulating barrier has the second via, this array base palte also includes: the conductive pattern between the first insulating barrier and the second insulating barrier, conductive pattern cover the first via and and drain contact, the first electrode covers the second via and contacts with conductive pattern.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of array base palte and preparation method thereof, display device.
Background technology
Along with improving constantly of Display Technique, people are also improving constantly for the requirement of display device, in various displays
In technology, with TFT (Thin Film Transistor, thin film transistor (TFT)) for controlling element, collect the integrated electricity of large-scale semiconductive
Road and flat board light source technology, in the O-E Products of one, such as TFT thin film transistor monitor, with low-power consumption, are convenient for carrying, make
Wide by scope, the advantage such as high-quality becomes the main flow display product of a new generation.
With TFT-LCD (Thin Film Transistor Liquid Crystal Display, tft liquid crystal
Display) as a example by, as it is shown in figure 1, the array base palte in this display includes the thin film transistor (TFT) being arranged on underlay substrate 10
100, public electrode 20 and pixel electrode 30, wherein, pixel electrode 30 relative to public electrode 20 away from thin film transistor (TFT)
100, and pixel electrode 30 is connected with the drain electrode 101 of thin film transistor (TFT) 100 by via 40.
But, as it is shown in figure 1, due to pixel electrode 30 with drain electrode 101 distances on vertical substrates substrate 10 direction relatively
Greatly, so that the drop height H of via 40 is relatively big, the gradient of via 40 side is relatively steep, and thin due to pixel electrode 30
Film layer its thickness is relatively thin, therefore when the thin layer of pixel deposition electrode 30, easy at this via 40 side and bottom surface
The phenomenon that deposition is uneven occurs, is easily caused the problem that loose contact occurs between pixel electrode 30 and drain electrode 101, particularly
When this array base palte is applied to bending or Flexible Displays product, during bending, film layer uneven at via 40
The phenomenons such as fracture easily occur, causes display bad.
Summary of the invention
Embodiments of the invention provide a kind of array base palte and preparation method thereof, display device, and in array base palte, electrode leads to
When via is connected with drain electrode, it is possible to reduce the drop of via area, reduces electrode and occur connecing in this via area with drain electrode
Touch bad probability.
For reaching above-mentioned purpose, embodiments of the invention adopt the following technical scheme that
On the one hand the embodiment of the present invention provides a kind of array base palte, including: the thin film transistor (TFT) being arranged on underlay substrate,
And be successively set on described thin film transistor (TFT) the first insulating barrier, the second insulating barrier, the first electrode, at described film crystal
At the drain electrode position of pipe, described first insulating barrier has the first via, and described second insulating barrier has the second via；Described
Array base palte also includes: the conductive pattern between described first insulating barrier and described second insulating barrier, described conductive pattern
Cover described first via and with described drain contact, described first electrode cover described second via and with described conductive pattern
Case contacts.
Further, described array base palte also includes the second electricity between described second insulating barrier and the first insulating barrier
Pole, in subpixel regions, described first electrode is oppositely arranged along the vertical direction of described underlay substrate with described second electrode.
Further, described array base palte also includes touch control electrode between described second insulating barrier and the first insulating barrier
Line, described touch control electrode line contacts with the surface of described second electrode.
Further, described touch control electrode line is positioned at described second electrode and deviates from the surface of described underlay substrate side.
Further, the thickness of described touch control electrode line is more than the thickness of described second electrode.
Further, described touch control electrode line is made up of metal material.
Further, described conductive pattern and described second electrode are with the same material of layer；Or, described conductive pattern is with described
Touch control electrode line is with the same material of layer；Or, described conductive pattern includes that the first conduction sub pattern and second that stacking is arranged is conducted electricity
Sub pattern, described first conduction sub pattern is touched with described with the same material of layer, described second conduction sub pattern with described second electrode
Control electrode wires is with the same material of layer.
On the other hand the embodiment of the present invention also provides for a kind of display device, including any one array base of preceding claim
Plate.
Further, in the case of described array base palte includes the first electrode and the second electrode: described display device is
Liquid crystal indicator, described first electrode is pixel electrode, and described second electrode is public electrode；Or, described display device
For organic light-emitting display device, described first electrode is anode, and described second electrode is negative electrode；Or, described first electrode is
Negative electrode, described second electrode is anode.
Embodiment of the present invention another further aspect also provides for the preparation method of a kind of array base palte, including: shape on underlay substrate
Become thin film transistor (TFT)；The underlay substrate being formed with described thin film transistor (TFT) is formed the first insulating barrier, described first insulating barrier
In the position of the drain electrode of corresponding described thin film transistor (TFT), there is the first via；At the substrate base being formed with described first insulating barrier
Form the first conductive film on plate, and described first conductive film composition is formed the first conductive layer, described first conductive layer bag
Include the conductive pattern covering described first via；The underlay substrate being formed with described first conductive layer is formed the second insulation
Layer, described second insulating barrier has the second via in the position of corresponding described conductive pattern；It is being formed with described second insulation
Form the first electrode on the underlay substrate of layer, and described first electrode covers described second via and connects with described conductive pattern
Touch.
The embodiment of the present invention provides a kind of array base palte and preparation method thereof, display device, and this array base palte includes arranging
Thin film transistor (TFT) on underlay substrate, and be successively set on thin film transistor (TFT) the first insulating barrier, the second insulating barrier,
One electrode, at the drain electrode position of thin film transistor (TFT), the first insulating barrier has the first via, and the second insulating barrier has second
Via；This array base palte also includes the conductive pattern between the first insulating barrier and the second insulating barrier, and conductive pattern covers the
One via and and drain contact, the first electrode covers the second via and contacts with conductive pattern.
Owing to the first via in the first insulating barrier and the second via in the second insulating barrier are respectively positioned on thin film transistor (TFT)
At drain electrode position, when the first electrode covers the second via, this first electrode can be with the conductive pattern covering the first via
Contact, is connected with drain electrode by conductive pattern, and so, relative in prior art, the first electrode is at vertical substrates base
For needing the overall drop height striding across the first via and the second via to be connected with drain electrode on plate direction, in the present invention, the
One electrode is connected with drain electrode by conductive pattern, has certain thickness owing to covering the conductive pattern self of the first via,
So that the drop height that the first electrode strides across in via area reduces, and then reduce the first electrode in via area appearance
The probability of the phenomenons such as fracture, reduces the probability occurring loose contact with drain electrode when the first electrode is connected.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
In having technology to describe, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to
Other accompanying drawing is obtained according to these accompanying drawings.
The structural representation of a kind of array base palte that Fig. 1 provides for prior art；
The structural representation of a kind of array base palte that Fig. 2 provides for the embodiment of the present invention；
The structural representation of the another kind of array base palte that Fig. 3 provides for the embodiment of the present invention；
The structural representation of another array base palte that Fig. 4 provides for the embodiment of the present invention；
The structural representation of another array base palte that Fig. 5 provides for the embodiment of the present invention；
The structural representation of another array base palte that Fig. 6 provides for the embodiment of the present invention；
The structural representation of another array base palte that Fig. 7 provides for the embodiment of the present invention；
The preparation method flow chart of a kind of array base palte that Fig. 8 provides for the embodiment of the present invention；
One of a kind of structural representation preparing array base palte that Fig. 9 a provides for the embodiment of the present invention；
One of a kind of structural representation preparing array base palte that Fig. 9 b provides for the embodiment of the present invention；
One of a kind of structural representation preparing array base palte that Fig. 9 c provides for the embodiment of the present invention；
One of a kind of structural representation preparing array base palte that Fig. 9 d provides for the embodiment of the present invention.
Reference:
01-array base palte；10-underlay substrate；20-public electrode；30-pixel electrode；40-via；41-the first via；
42-the second via；50-touch control electrode；100-thin film transistor (TFT)；101-drains；110-the first insulating barrier；120-second insulate
Layer；201-the first electrode；202-the second electrode；300-conductive pattern；301-first conducts electricity sub pattern；302-second conducts electricity subgraph
Case.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments wholely.Based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under not making creative work premise
Embodiment, broadly falls into the scope of protection of the invention.
The embodiment of the present invention provides a kind of array base palte, as in figure 2 it is shown, this array base palte 01 includes: be arranged at substrate base
Thin film transistor (TFT) 100 on plate 10, and first insulating barrier the 110, second insulating barrier being successively set on thin film transistor (TFT)
120, the first electrode 201, at drain electrode 101 position of thin film transistor (TFT) 100, the first insulating barrier 110 has the first via
41, the second insulating barrier 120 has the second via 42, in the case, due to above-mentioned first via 41 and the position of the second via 42
Put to correspondence so that the total drop height of the first via 41 and the second via 42 is H1 be the first via 41 drop height with
Second via 42 drop height sum.
On this basis, as in figure 2 it is shown, this array base palte 01 also includes: be positioned at the first insulating barrier 110 and the second insulating barrier
Conductive pattern 300 between 120, this conductive pattern 300 covers the first via 41 and contacts, due to above-mentioned covering with drain electrode 101
The conductive pattern 300 of the first via 41 self has certain thickness, and now, the drop height H2 of via area is the first via
41 and second the total drop height H1 of via 42 deduct the thickness of conductive pattern 300, in the case, the first electrode 201 covers
Second via 42 also contacts with conductive pattern 300.
So, relative in prior art, the first electrode stride across on vertical substrates orientation substrate the first via and
For the overall drop height of the second via is connected with drain electrode, in the present invention, the first electrode covers the second via, and with conduction
Pattern contacts, owing to the drop height H2 of via area is less than total drop height H1, thus reduces the first electrode in via area
There is the probability of the phenomenons such as fracture in territory, and then reduces the probability occurring loose contact with drain electrode when the first electrode electrically connects.
Herein it should be noted that the second insulating barrier 110 and the first insulating barrier set gradually in above-mentioned array base palte 01
Between two insulating barriers of 120, other light shield layer, holding wire, electrode etc. are typically set.
Concrete, such as, as it is shown on figure 3, be provided with the second electricity between the second insulating barrier 120 and the first insulating barrier 110
Pole 202, in subpixel regions, the first electrode 201 is oppositely arranged along the vertical direction of underlay substrate 10 with the second electrode 202.
Below to including that the array base palte 01 of above-mentioned the first electrode 201 being oppositely arranged and the second electrode 202 is at display dress
Application in putting is described further.
Such as, as it is shown on figure 3, this array base palte 01 can be LCD (Liquid Crystal Display, liquid crystal display
Device) in ADS (Advanced-Super Dimensional Switching, senior super dimension field switch) type array base palte,
Wherein, the first electrode 201 is pixel electrode, and includes multiple strip sub-electrode, and the second electrode 202 is public electrode.First is exhausted
Edge layer 110 and the second insulating barrier 120 are passivation layer.
The most such as, as shown in Figure 4, this array base palte 01 can also be OLED (Organic Light Emitting
Diode, organic light-emitting display device) in array base palte, wherein, the first electrode 201 is anode, and the second electrode 202 is negative electrode,
Or, the first electrode 201 is negative electrode, and the second electrode 202 is anode.First insulating barrier 110 is passivation layer, the second insulating barrier 120
Layer is defined for pixel.
Following example are all that the present invention will be further described as a example by array base palte 01 is for ADS type array base palte.
So that above-mentioned array base palte 01 is while having the function of array base palte self, have touch controllable function concurrently, as
Shown in Fig. 5, this array base palte 01 also includes touch control electrode line 50 between the second insulating barrier 120 and the first insulating barrier 110, should
Touch control electrode line 50 contacts with the surface of the second electrode 202 (i.e. public electrode 20).
It should be noted that touch control electrode line 50 includes being arranged at the part that the surface of public electrode 20 contacts, also wrap
Include the trace portions being arranged on array substrate peripheral region, carried out input and the output of touching signals by the cabling of this part.
In the case, the second electrode 202 display the stage as public electrode, in the touch-control stage as touch control electrode, so,
When this array base palte is applied to display device, in display stage (such as 0.01s) with the touch-control stage (such as 0.005s) alternately
Touch display function it is capable of during carrying out.
It addition, touch control electrode line 50 typically uses metal material to make, owing to the resistance of metal is less, so, touch
It is less that the part contacted with the surface of public electrode 20 in control electrode wires 50 is equivalent in parallel on public electrode 20 one
Resistance such that it is able to reduce the resistance of public electrode 20, and then reduce the load of whole array base palte.
Also needing to explanation, above-mentioned touch control electrode line 50 contacts with the surface of the second electrode 202, can be touch-control herein
Electrode wires 50 and the upper surface of the second electrode 202, the most as shown in Figure 5, touch control electrode line 50 is positioned at the second electrode 202 and carries on the back
Side from underlay substrate 10；It is, of course, also possible to be that touch control electrode line 50 contacts with the lower surface of the second electrode 202, i.e. touch-control
Electrode wires 50 is positioned at the second electrode 202 near the side of underlay substrate 10.
On this basis, during due to the upper surface of touch control electrode line 50 and the second electrode 202, touch control electrode line 50 with
Second electrode 202 directly contacts, and the surface of touch control electrode line 50 is compared little, such that it is able to pass through with the second electrode 201 surface
Half-exposure masking process forms touch control electrode line 50 and the second electrode 202 by a composition.And when touch control electrode line 50 and the
When the lower surface of two electrodes 202 contacts, it is necessary to form touch control electrode line 50 and the second electrode respectively by twice patterning processes
202。
Further, since touch control electrode line more than 50 uses metal to make, the second electrode 202 as public electrode mostly is transparent
Conductive material, and the thickness of the touch control electrode line 50 of metal material is more than the thickness of the public electrode 20 of electrically conducting transparent material, this
Sample one, if touch control electrode line 50 is positioned at the lower surface of public electrode 20, then easily at the marginal position of touch control electrode line 50,
Make the transparent conductive film constituting public electrode 20 that fracture easily occur；And control electrode wires 50 is positioned at the upper of public electrode 20
Surface does not then have above-mentioned drawback.
In sum, currently preferred, the thickness of touch control electrode line 50 is more than the thickness of the second electrode 202；Touch-control electricity
Polar curve 50 is positioned on the surface of the first electrode 201 away from substrate substrate 10 side.
Hereinafter the form that specifically arranges of above-mentioned conductive pattern 300 is described further.
For example, it is possible to as it is shown in figure 5, this conductive pattern 300 and the second electrode 202 are arranged with material with layer, realizing fall
While low via area drop height, conductive pattern 300 and the second electrode 202 can be formed by a patterning processes, enter
And reach Simplified flowsheet, reduce the purpose of cost of manufacture.
Again for example, it is possible to as shown in Figure 6, this conductive pattern 300 and touch control electrode line 50, with the same material of layer, are realizing reduction
While via area drop height, conductive pattern 300 can be formed by a patterning processes with touch control electrode line 50, and then
Reach Simplified flowsheet, reduce the purpose of cost of manufacture.
On this basis, when touch control electrode line 50 and conductive pattern 300 are metal material, compared to conductive pattern 300
For being electrically conducting transparent material with the second electrode 202 (public electrode 20), on the one hand, the conductive pattern 300 that metal material is constituted
Electric conductivity is more preferable, so that the turn-on effect between pixel electrode 30 and drain electrode 101 is more preferable；On the other hand, metallic film
Thickness generally large, thus advantageously reduce via area drop height；Another further aspect, the pliability of metallic film is preferable,
This array base palte is made to be more suitable for being applied in flexible display apparatus, it is possible to when this via area occurs bending or bending,
The effective normally ensureing conductive pattern 300 and drain electrode 101.
The most such as, as it is shown in fig. 7, this conductive pattern 300 includes that the first conduction sub pattern 301 and second that stacking is arranged is led
Electronics pattern 302, the first conduction sub pattern 301 and the second electrode 201 are with the same material of layer, the second conduction sub pattern 302 and touch-control
Electrode wires 50 is with the same material of layer.So, the first conduction sub pattern 301 and the second electrode 201 are by a patterning processes shape
Becoming, the second conduction sub pattern 302 is formed by a patterning processes with touch control electrode line 50, and then can drop at Simplified flowsheet
While low cost of manufacture, by the first conduction sub pattern 301 and the second conduction sub pattern 302 are covered in via area simultaneously
Territory, it is possible to effectively reduce via area drop height further.
It should be noted that in the present invention, patterning processes, can refer to include photoetching process, or, including photoetching process and
Etch step, can also include simultaneously printing, ink-jet etc. other for the technique forming predetermined pattern；Photoetching process, refers to bag
Include film forming, expose, the technique utilizing photoresist, mask plate, exposure machine etc. to form figures of the technical process such as development.Can be according to this
The corresponding patterning processes of structure choice formed in invention.
On the other hand the embodiment of the present invention also provides for a kind of display device, and this display device includes any of the above-described kind of array base
Plate, has the structure identical with the array base palte that previous embodiment provides and beneficial effect.Owing to previous embodiment has been poised for battle
Structure and the beneficial effect of row substrate are described in detail, and here is omitted.
Herein it should be noted that in the case of array base palte 01 includes the first electrode 201 and the second electrode 202:
This display device can be, ADS type array base palte shown in Fig. 3 01 with to box substrate, and ADS type array base palte
01 and between box substrate liquid crystal layer constitute liquid crystal indicator, wherein, the first electrode 201 is pixel electrode, and includes
Multiple strip sub-electrodes, the second electrode 202 is public electrode, and the first insulating barrier 110 and the second insulating barrier 120 are passivation layer.
This display device can also be, the organic light-emitting display device that the array base palte shown in Fig. 4 is constituted, wherein, and first
Electrode 201 is anode, and the second electrode 202 is negative electrode, or, the first electrode 201 is negative electrode, and the second electrode 202 is anode.First
Insulating barrier 110 is passivation layer, and the second insulating barrier 120 defines layer for pixel.Certainly, the first electrode 201 and the second electrode 202 it
Between there is light emitting functional layer.
It should be noted that in the case of this display device is organic light-emitting display device, when the first electrode 201 reflects
Electrode, when the second electrode 202 is transmission electrode, this display device is bottom emitting type；When the first electrode 201 is transmission electrode, the
When two electrodes 202 are reflecting electrode, this display device is top emission type, and this is not limited by the present invention.
Herein also, it should be noted for constitute OLED array base palte, with constitute LCD ADS type array base palte phase
Ratio, two kinds of array base paltes are close about touch control electrode line 50 and the form that arranges of conductive pattern 300 and relevant principle process,
Here is omitted.
The embodiment of the present invention also provides for the preparation method of a kind of array base palte, and as shown in Figure 8, this preparation method includes:
Step S101, as illustrated in fig. 9, forms thin film transistor (TFT) 100, wherein this thin film transistor (TFT) on underlay substrate 10
100 include grid, source electrode and drain electrode 101.
Step S102, as shown in figure 9b, forms the first insulating barrier on the underlay substrate 10 be formed with thin film transistor (TFT) 100
110, the first insulating barrier 110 has the first via 41 in the position of the drain electrode 101 of corresponding thin film transistor (TFT) 100.
Step S103, as is shown in fig. 9 c, forms the first conductive thin on the underlay substrate 10 being formed with the first insulating barrier 110
Film, and the first conductive film composition is formed the first conductive layer, the first conductive layer includes the conductive pattern covering the first via 41
300。
Wherein, Fig. 9 c is only only to include conductive pattern in the first conductive layer by forming the first conductive film composition
Illustrating as a example by 300, in actual application, this first conductive layer can also include the second electrode 202, such as, in Fig. 3
Public electrode 20, or, the negative electrode in Fig. 4 or anode.
Step S104, as shown in figure 9d, shape on the underlay substrate being formed with the first conductive layer (including conductive pattern 300)
Becoming the second insulating barrier 120, the second insulating barrier 120 has the second via 42 in the position of corresponding conductive pattern 300.
Step S105, as in figure 2 it is shown, form the first electrode on the underlay substrate 10 being formed with the second insulating barrier 120
201, and the first electrode 201 covers the second via 42 and contacts with conductive pattern 300.
It should be noted that when the first conductive layer formed in step S103 also includes with the first electrode 201 along substrate base
During the second electrode 202 that the vertical direction of plate 10 is oppositely arranged, above-mentioned is only with the ADS type array base palte shown in Fig. 2, the first electricity
Pole 201 is for illustrating as a example by pixel electrode；Can certainly be the array base palte in the OLED shown in Fig. 4, when the second electricity
When pole 202 is negative electrode, the first electrode 201 is anode, or when the second electrode 202 is anode, the first electrode 201 is negative electrode.
Certainly, after step S105, can also continue to make flatness layer or protective layer, its manufacture method and existing skill
Manufacture method in art is identical, and the most no longer accompanying drawing repeats.
The above, the only detailed description of the invention of the present invention, but protection scope of the present invention is not limited thereto, and any
Those familiar with the art, in the technical scope that the invention discloses, can readily occur in change or replace, should contain
Cover within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with described scope of the claims.
Claims (10)
1. an array base palte, it is characterised in that including: the thin film transistor (TFT) being arranged on underlay substrate, and set gradually
The first insulating barrier on described thin film transistor (TFT), the second insulating barrier, the first electrode, at the drain electrode place of described thin film transistor (TFT)
Position, described first insulating barrier has the first via, and described second insulating barrier has the second via；
Described array base palte also includes: the conductive pattern between described first insulating barrier and described second insulating barrier, described
Conductive pattern cover described first via and with described drain contact, described first electrode cover described second via and with institute
State conductive pattern contact.
Array base palte the most according to claim 1, it is characterised in that described array base palte also includes being positioned at described second exhausted
The second electrode between edge layer and the first insulating barrier, in subpixel regions, described first electrode and described second electrode are along institute
The vertical direction stating underlay substrate is oppositely arranged.
Array base palte the most according to claim 2, it is characterised in that described array base palte also includes being positioned at described second exhausted
Touch control electrode line between edge layer and the first insulating barrier, described touch control electrode line contacts with the surface of described second electrode.
Array base palte the most according to claim 3, it is characterised in that described touch control electrode line is positioned at the described second electrode back of the body
On the surface of described underlay substrate side.
5. according to the array base palte described in claim 3 or 4, it is characterised in that the thickness of described touch control electrode line is more than described
The thickness of the second electrode.
6. according to the array base palte described in claim 3 or 4, it is characterised in that described touch control electrode line is made up of metal material.
7. according to the array base palte described in claim 3 or 4, it is characterised in that
Described conductive pattern and described second electrode are with the same material of layer；
Or, described conductive pattern and described touch control electrode line are with the same material of layer；
Or, described conductive pattern includes the first conduction sub pattern and the second conduction sub pattern that stacking arranges, and described first leads
Electronics pattern and described second electrode are with the same material of layer, and described second conduction sub pattern and described touch control electrode line are with the same material of layer
Material.
8. a display device, it is characterised in that include the array base palte described in any one of claim 1 to 7.
Display device the most according to claim 8, it is characterised in that include the first electrode and second at described array base palte
In the case of electrode:
Described display device is liquid crystal indicator, and described first electrode is pixel electrode, and described second electrode is public electrode；
Or,
Described display device is organic light-emitting display device, and described first electrode is anode, and described second electrode is negative electrode；Or
Person, described first electrode is negative electrode, and described second electrode is anode.
10. the preparation method of an array base palte, it is characterised in that including:
Underlay substrate is formed thin film transistor (TFT)；
Forming the first insulating barrier on the underlay substrate being formed with described thin film transistor (TFT), described first insulating barrier is described in correspondence
The position of the drain electrode of thin film transistor (TFT) has the first via；
The underlay substrate being formed with described first insulating barrier is formed the first conductive film, and to described first conductive film structure
Figure forms the first conductive layer, and described first conductive layer includes the conductive pattern covering described first via；
Forming the second insulating barrier on the underlay substrate being formed with described first conductive layer, described second insulating barrier is described in correspondence
The position of conductive pattern has the second via；
The underlay substrate being formed with described second insulating barrier is formed the first electrode, and described first electrode covers described second
Via also contacts with described conductive pattern.
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