CN106067825B - BCH pre-searchs circuit, BCH decoding circuits, BCH pre-searching methods and BCH error correction methods - Google Patents
BCH pre-searchs circuit, BCH decoding circuits, BCH pre-searching methods and BCH error correction methods Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
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Abstract
The present invention provides a kind of BCH pre-searchs circuit, BCH decoding circuits, BCH pre-searching methods and BCH error correction methods, and the BCH pre-searchs circuit includes empty search code length calculation electric circuit, and truncating code length according to BCH standards code length and BCH calculates empty search code length；First Dynamic gene counting circuit, with the first Galois field multiplier, using each bit value and the adjustment first Dynamic gene of constant calculations of the long numerical value of empty searching code；Follow-up Dynamic gene counting circuit, with the second Galois field multiplier, multiple follow-up Dynamic genes are calculated according to first Dynamic gene；The items of error location polynomial, with the 3rd Galois field multiplier, are multiplied by corresponding first Dynamic gene or follow-up Dynamic gene by error location polynomial mlultiplying circuit respectively.BCH decoding circuits have above-mentioned BCH pre-search circuits.BCH pre-searching methods are the methods using BCH pre-search circuit realiration pre-searchs.The present invention can greatly reduce the area of the chip of BCH decoding circuits.
Description
Technical field
The present invention relates to BCH Error Corrections of Coding decode field, specifically provide a kind of BCH pre-searchs circuit, can to appoint
The BCH shortened codes for code length of anticipating carry out the BCH decoding circuits and BCH pre-searching methods, BCH error correction methods of pre-search.
Background technology
In the control chip of the mass-memory units such as NandFlash, may occur when data write storage unit
The situation of write error or read error, for example, certain a data should be binary number " 0 ", quilt during write storage unit
Mistake is write as binary number " 1 ".In order to avoid write-in or readout error data, it is necessary to verified to data, it is common
Way is write after data, and artificially writing a part of redundant data is used for Error Control, to ensure to carry out during data read-out
Error detection and correction.
Bose-Chaudhuri Hocquenghem error correction codes be it is a kind of be generally used for correct random error cyclic check code, the check code by R.C.Bose,
D.K.Chaudhuri and A.Hocquenghem propose jointly, and it is that a kind of have that strict Algebraic Structure, error correcting capability be strong, structure
Make the linear block codes for the features such as simple, the more other codes of coding are easy.
When carrying out error correction using binary system Bose-Chaudhuri Hocquenghem error correction codes, it usually needs the code word decoded is carried out using decoder
Decoding.Assuming that the number for the random error that Bose-Chaudhuri Hocquenghem error correction codes can be corrected is t, then when decoding, first according to the code word received
R (X) calculates syndrome S1~S2t, then according to syndrome S1~S2tError location polynomial σ (x) is calculated, mistake is calculated
Position multinomial is obtained usually using IBM iterative algorithms.Then, using finite field gf (2n) on shortened code when, if truncate
The length of code is K (K<2n- 1), then need error location polynomial σ (x) items being multiplied by corresponding Dynamic gene α in advanceL、
α2L、α3L...αtL, so that pre-search is carried out, to skip L bit (L=2n- 1-K) position that needs not search for searches to shorten Qian Shi
The operation time of rope.Then, error location polynomial σ (x) root is solved using chien search (Chien Search), so as to ask
Solve errors present.Finally, according to errors present, to former data-conversion.Thus can be by the data modification on errors present
For correct data, error correction is realized.
Due to error location polynomial σ (x) items are being multiplied by into corresponding Dynamic gene α in advanceL、α2L、α3L...αtL
The step of in, existing method is typically once to complete all α using pure combinational logicL~αtLFinite field multiplier realize, example
Chinese invention patent application such as Publication No. CN101252361A discloses a kind of entitled " area compact type for supporting pre-search
Error location polynomial σ (x) items are exactly disposably multiplied by correspondence by the innovation and creation of BCH parallel decodings circuit ", this method
Dynamic gene αL、α2L、α3L...αtL, it is therefore desirable to completed using t constant multiplier.Moreover, it is different to shorten code code length L
When, it is necessary to the different coefficients of t be stored again, if y kinds shorten code code length L, then need the number of coefficients meeting of storage altogether
Up to y × t.
However, at present in the mass-memory unit such as Flash, Bose-Chaudhuri Hocquenghem error correction codes need the digit t corrected to be typically larger than 70,
Cause pure combinational logic once complete all finite field multipliers circuit it is very huge.And it is a variety of in order to adapt to
Flash error correction demand is, it is necessary to which the digit t corrected can be differed, and data length can also be differed, therefore usually requires to support
Hundred kinds of different shortening code code length L, then the quantity of Dynamic gene will be more than 7000.But, because the area of chip is
Limited, it is impossible to by the Dynamic gene α of all different code lengthsL~αtLIt is stored in chip, this causes BCH decoders can only
Pre-search is carried out to a limited number of kind of code length, the decoding speed of BCH decoders is had a strong impact on.
The content of the invention
The first object of the present invention is to provide one kind in finite field gf (2n) when need to only store n adjustment constant can be right
Any digit carries out the pre-search circuit of the BCH decoding circuits of error correction.
The second object of the present invention is to provide one kind in finite field gf (2n) when need to only store n adjustment constant and will not account for
The BCH decoding circuits of Dynamic gene are stored with the area of a large amount of chips.
The third object of the present invention is to provide the BCH pre-searching methods that a kind of strong BCH error correction methods of error correcting capability are used.
The fourth object of the present invention, which is to provide, a kind of can save the BCH error correction methods of chip area.
In order to realize the first above-mentioned purpose, the BCH pre-searchs circuit that the present invention is provided includes empty search code length and calculates electricity
Road, truncates code length according to BCH standards code length and BCH and calculates empty search code length；First Dynamic gene counting circuit, has with first
Finite field multiplication device, using each bit value and the adjustment first Dynamic gene of constant calculations of the long numerical value of empty searching code；Follow-up adjustment
Factor calculating circuit, with the second Galois field multiplier, multiple follow-up Dynamic genes are calculated according to first Dynamic gene；Error bit
Polynomial multiplication circuit is put, with the 3rd Galois field multiplier, the items of error location polynomial are multiplied by corresponding head respectively
Individual Dynamic gene or follow-up Dynamic gene.
From such scheme, because first Dynamic gene and multiple follow-up Dynamic genes are not to be stored in advance in core
In piece, but obtained by adjusting constant calculations, therefore BCH pre-searchs circuit need not use substantial amounts of chip area storage big
The Dynamic gene of amount.Also, because Dynamic gene is to calculate to obtain, therefore BCH pre-searchs circuit can be to the BCH of any code length
Shortened code carries out pre-search, makes BCH decoding circuit applications wider.
One preferred scheme is that BCH pre-searchs circuit also includes Dynamic gene register, calculates what is obtained for storing
Dynamic gene.
Therefore, the multiple Dynamic genes for calculating acquisition are stored in advance in register, follow-up meter can be facilitated
Calculate.
To realize the second above-mentioned purpose, the BCH decoding circuits that the present invention is provided include error location polynomial and calculate electricity
Road, receives syndrome, and with multiple Galois field multipliers, for calculating error location polynomial；Pre-search circuit, receives wrong
Miss the polynomial every value in position；Mistake address calculating circuit, receives the numerical value of pre-search circuit output, and calculates mistake
Address；Correction circuit, for by the data-conversion of errors present；Wherein, pre-search circuit includes：Sky search code length calculates electricity
Road, truncates code length according to BCH standards code length and BCH and calculates empty search code length；First Dynamic gene counting circuit, using sky search
Each bit value of code length numerical value and the adjustment first Dynamic gene of constant calculations；Follow-up Dynamic gene counting circuit, according to first
Dynamic gene calculates multiple follow-up Dynamic genes；Error location polynomial mlultiplying circuit, by the items of error location polynomial point
Corresponding first Dynamic gene or follow-up Dynamic gene are not multiplied by.
From such scheme, BCH decoding circuits are using the adjustment multiple Dynamic genes of constant calculations, that is, do not need pre-
First the corresponding Dynamic gene of different shortened codes is stored in the chips, but because the quantity of adjustment constant is in finite field gf (2n) when
Only n, general n is less than or equal to 14, the multiple different adjustment for truncating code length of the support far smaller than referred in background technology
The quantity of the factor, therefore the memory space of storage Dynamic gene can be greatlyd save, so as to allow BCH decoding circuits to adapt to different cut
Short code code length carries out the occasion of pre-search.
One preferred scheme is, multiple finite field multipliers of pre-search circuit multiplexer error location polynomial counting circuit
Device.
As can be seen here, the area of chip can be greatlyd save by being multiplexed Galois field multiplier, and will not excessively increased
Operation time, advantageously reduce the area of BCH decoding circuits, reduce the production cost of BCH decoding circuits.
To realize the 3rd above-mentioned purpose, the BCH pre-searching methods that the present invention is provided include according to BCH standards code length and
BCH truncates code length and calculates empty search code length；Using each bit value and the first tune of adjustment constant calculations of the long numerical value of empty searching code
Integral divisor；Multiple follow-up Dynamic genes are calculated according to first Dynamic gene；The items of error location polynomial are multiplied by pair respectively
The first Dynamic gene or follow-up Dynamic gene answered.
From such scheme, when carrying out BCH pre-searchs, it is not necessary to use the Dynamic gene prestored, Dynamic gene
Obtained by adjustment constant calculations, because the quantity of adjustment constant is far smaller than the number of the Dynamic gene of the shortened code of different code length
Amount, therefore need the Dynamic gene quantity stored to greatly reduce during BCH pre-searchs, so that the area of BCH pre-search circuits.
To realize the 4th above-mentioned purpose, the BCH error correction methods that the present invention is provided include calculating error location polynomial；And
And BCH pre-searchs are carried out, pre-search step includes truncating the empty search code length of code length calculating according to BCH standards code length and BCH；Using
Each bit value of the empty long numerical value of searching code and the adjustment first Dynamic gene of constant calculations；Calculate multiple according to first Dynamic gene
Follow-up Dynamic gene；The items of error location polynomial are multiplied by corresponding first Dynamic gene or follow-up Dynamic gene respectively；
The root of error location polynomial is solved, errors present is calculated；By the data-conversion of errors present.
As can be seen here, when carrying out BCH error correction, Dynamic gene is not to be stored in advance on chip, but normal by adjustment
Number, which is calculated, to be obtained, so, and BCH error correction can carry out pre-search for the BCH shortened codes of different code length, BCH error correction methods it is suitable
Ying Xinggeng is wide.
Brief description of the drawings
Fig. 1 is the structured flowchart of BCH decoding circuits embodiment of the present invention.
Fig. 2 is the structured flowchart of BCH pre-searchs circuit embodiments of the present invention.
Fig. 3 is the structure principle chart of BCH pre-searchs circuit embodiments of the present invention.
Fig. 4 is the flow chart of BCH error correction methods embodiment of the present invention.
Below in conjunction with drawings and Examples, the invention will be further described.
Embodiment
The BCH error correction methods of the present invention are to carry out the method that pre-search realizes error correction based on BCH shortened codes.The side of the present invention
Method can carry out pre-search to the BCH shortened codes of any code length and realize error correction, therefore to be provided with BCH pre- for BCH decoding circuits
Search circuit.
Referring to Fig. 1, BCH decoding circuits of the invention have error location polynomial counting circuit 10, pre-search circuit 20,
Mistake address calculating circuit 30 and error correction circuit 40, Galois field multiplier array 50.
Error location polynomial counting circuit 10 receives the syndrome S calculated by code word R (X)1~S2t, and according to companion
With formula S1~S2tCalculate error location polynomial σ (x).Generally, the application of error location polynomial counting circuit 10 is a large amount of limited
Domain multiplier realizes the calculating of error location polynomial, such as calculates error location polynomial σ using common IBM iterative algorithms
(x) every u0, u1, u2 ... ut, and error location polynomial σ (x) every u0, u1, u2 ... ut value is exported to pre-
Search circuit 20.
Pre-search circuit 20 is multiplied by correspondence respectively according to error location polynomial σ (x) every u0, u1, u2 ... ut value
Dynamic gene, obtain pre-search result.
The implementation of pre-search circuit is as shown in Fig. 2 pre-search circuit 20 is provided with empty search code length calculation electric circuit 21, head
Individual Dynamic gene counting circuit 22, follow-up Dynamic gene counting circuit 23 and error location polynomial mlultiplying circuit 24.
Assuming that in finite field gf (2n) BCH code maximum code length be 2n- 1, maximum code length is BCH error correction in the present embodiment
The standard code length of code.Due to needing to use BCH shortened codes to be decoded, and the code length of BCH shortened codes is usual than maximum code length 2n-
1 is short, it is assumed that the code length of BCH shortened codes is K, then it is L=2 that empty search code length calculation electric circuit 21, which calculates empty search code length L,n-1-K。
So, when carrying out pre-search, the L positions data needed not search for are skipped, so as to improve efficiency when calculating wrong address.
With binary representation sky search code length L, because empty search code length L numerical value is not more than (2n- 1), so empty search
Code length L binary digit is a width of n, it is assumed that empty search code length L binary xth position is represented with L.x, then is had
L=L. (n-1) * 2(n-1)+L.(n-2)*2(n-2)+L.(n-3)*2(n-3)+…+L.1*21+L.0*20
So first Dynamic gene can be obtained
Wherein,For adjustment constant.In the present embodiment, adjustment constant is to preset
Constant.Due in L.x=0,Therefore, all items are all constant terms in formula 1, so only
Need to carry out first Dynamic gene α when n constant finite field multiplier can try to achieve the empty search code length L of any code lengthLValue.
Therefore, first Dynamic gene counting circuit 22 can set Galois field multiplier, be searched using adjustment constant and sky
The rope code length L values of each calculate first Dynamic gene αLValue.
Then, the first adjustment that follow-up Dynamic gene counting circuit 23 is calculated according to first Dynamic gene counting circuit 22
Factor-alphaLValue, the multiple Dynamic gene α of calculated for subsequent2L~αtL, for example, α2L=αL*αL、α3L=α2L*αL、...αtL=α(t-1)L*
αL, and so on, common t-1 finite field multiplier computing excessively is that can calculate to obtain follow-up multiple Dynamic genes.Therefore, after
Continuous Dynamic gene counting circuit 23 can also set Galois field multiplier, for carrying out t-1 finite field multiplier computing.
Assuming that σ (x) is according to syndrome S1~S2tThe error location polynomial calculated, by error location polynomial σ (x)
Items be multiplied by Dynamic gene α respectivelyL、α2L、α3L...αtL, that is, complete pre-search.Specifically, error location polynomial multiplication electricity
Road 24 error location polynomial σ (x) items are multiplied by corresponding Dynamic gene α respectivelyL、α2L、α3L...αtL, i.e. errors present
Multinomial σ (x) Section 1 is multiplied by first Dynamic gene αL, Section 2 be multiplied by second Dynamic gene α2L, and so on, mistake
T of position multinomial σ (x) are multiplied by t-th of Dynamic gene αtL.So, common t finite field multiplier computing excessively is to obtain
Obtain pre-search result U0 ', U1 ', U2 ' ... Ut '.Therefore, error location polynomial mlultiplying circuit 24 can also set finite field to multiply
Musical instruments used in a Buddhist or Taoist mass, for carrying out multiple finite field multiplier computing.
Then, pre-search circuit 20, which is calculated, is obtained after pre-search result U0 ', U1 ', U2 ' ... Ut ', and result is output into mistake
Miss address calculating circuit 30.Mistake address calculating circuit 30 is Chien search circuit, calculates error location polynomial σ's (x)
Root, the address of the root calculated namely mistake, i.e. position where wrong data.Finally, correction circuit 40 is by errors present
On data-conversion, also just complete correction process.
The present embodiment, which is provided with Galois field multiplier array 50, the array, is provided with multiple Galois field multipliers.Errors present
Polynomial computation circuit 10 and pre-search circuit 20 receive the signal of Galois field multiplier array 50, therefore, pre-search electricity
Road 20 is actually multiple Galois field multipliers 50 of reused error position polynomial computation circuit 10.Because errors present is multinomial
The finite field multiplier operation times of formula counting circuit 10 are about (3t+2) t times, and pre-search circuit 20 needs progress (2t+n-1) secondary
Finite field multiplier computing.Therefore, when t is larger, such as t>When 40, (2t+n-1) is far smaller than (3t+2) t.Therefore, pre-search electricity
The multiplexing of road 20 calculates the Galois field multiplier of error location polynomial counting circuit 10, will not both take too many operation time,
A large amount of areas of chip can be saved, the production cost of BCH decoders is reduced.
If it should be noted that the finite field multiplier of the reused error position polynomial computation circuit 10 of pre-search circuit 20
Device, then need not be in first Dynamic gene counting circuit 22, follow-up Dynamic gene counting circuit 23, error location polynomial multiplication
Galois field multiplier is set on circuit 24, so as to reduce the area of chip.
The typical circuit schematic diagram of pre-search circuit 20 is as shown in figure 3, empty search code length calculation electric circuit 21 calculates sky and searched
Rope code length L numerical value, that is, obtain the empty search code length L numerical value of each.Then, using Galois field multiplier array
Galois field multiplier 51 calculates first Dynamic gene αLValue.Meanwhile, use first Dynamic gene αLValue, using finite field
Multiplier 52,53 ... 54 calculate t-1 follow-up Dynamic gene α2L~αtL, multiple Dynamic gene αL、α2L、α3L...αtLExport to mistake
By mistake in position polynomial multiplication circuit 24, and error location polynomial mlultiplying circuit 24 calculate pre-search result U0 ', U1 ',
U2’…Ut’。
The workflow of BCH error correction methods is introduced with reference to Fig. 4.First, the companion calculated by code word R (X) is received
With formula S1~S2t, and according to syndrome S1~S2tError location polynomial σ (x) is calculated, that is, performs step S1.Then, perform
Pre-search is operated, and first carries out step S2, and empty search code length L is calculated according to the code length K of BCH maximum code length and BCH shortened codes.
Assuming that n=14, BCH shortened code code length K=12287, then when to the BCH shortened codes progress pre-search of any code length, calculate
Sky search code length L=2n- 1-K=214- 1-12287=4096.
In the present embodiment, with binary representation sky search code length L, then there is L=1_0000_0000_0000, then L=0*2^
13+1*2^12+0*2^11+0*2^10+......0*2^1+0*2^0.Then, step S3 is performed, first Dynamic gene α is calculatedL
Value, it can be seen from method described above, first Dynamic gene
Due toTo adjust constant, for example Cause
This, can calculate the first Dynamic gene of acquisition
Then, step S4 is performed, multiple follow-up adjustment constant αs are calculated2L~αtL, it can be seen from foregoing method, α2L=
0X06BF*0X06BF、α3L=α2L*0X06BF、...αtL=α(t-1)L*0X06BF。
Then, step S5 is performed, error location polynomial σ (x) items are multiplied by corresponding Dynamic gene α respectivelyL、
α2L、α3L...αtL, result is output to money search module and scanned for.Finally, solve error location polynomial σ (x) and obtain wrong
Position multinomial σ (x) root, that is, perform step S6 by mistake, so as to obtain errors present, and performs step S7, by mistake
The data-conversion of position, realizes error correction.
In the BCH error correction methods of this implementation, the common 2t+12 of finite field multiplier computing completed is needed during pre-search
It is secondary, and the finite field multiplier operation times for calculating error location polynomial σ (x) are about (3t+2) t times.Therefore, in pre-search mistake
Multiplexing calculates the Galois field multiplier used during error location polynomial in journey, will increase the time of BCH error correction, when institute is increased
Between ratio c be：C=(2t+12)/((3t+2) t).Because present Nand Flash require that BCH error correcting capability would generally be big
In 40bit.As t=40, the increased time ratio c=92/4880=0.019 of multiplexing Galois field multiplier institute.It can be seen that, error correction
Digit t is bigger, and the increased time ratio c of institute is smaller.When therefore, when carrying out pre-search, multiplexing calculates error location polynomial
Galois field multiplier, will not take too many operation time, but can save a large amount of areas of circuit board, be set so as to reduce storage
Standby volume, also reduces the production cost of BCH decoding circuits.
Certainly, above-mentioned scheme is the preferred embodiment of the invention, and practical application is that can also have more changes,
For example, pre-search circuit can not reused error position polynomial computation circuit Galois field multiplier, that is, pre-search electricity
Road uses respective Galois field multiplier respectively with error location polynomial counting circuit, and these changes do not affect the present invention's
Implement, should also include within the scope of the present invention.
Claims (10)
1.BCH pre-search circuits, it is characterised in that including：
Sky search code length calculation electric circuit, truncates code length according to BCH standards code length and BCH and calculates empty search code length；
First Dynamic gene counting circuit, with the first Galois field multiplier, each of code length binary numeral is searched for using empty
Bit value and the adjustment first Dynamic gene of constant calculations；
Follow-up Dynamic gene counting circuit, with the second Galois field multiplier, according to the first Dynamic gene calculate it is multiple after
Continuous Dynamic gene；
Error location polynomial mlultiplying circuit, with the 3rd Galois field multiplier, the items of error location polynomial are multiplied respectively
With the corresponding first Dynamic gene or the follow-up Dynamic gene.
2. BCH pre-searchs circuit according to claim 1, it is characterised in that：
Also include Dynamic gene register, for store calculate obtain the first Dynamic gene and the follow-up adjustment because
Son.
3.BCH decoding circuits, including：
Error location polynomial counting circuit, receives syndrome, and with multiple Galois field multipliers, for calculating errors present
Multinomial；
Pre-search circuit, receives every value of the error location polynomial；
Mistake address calculating circuit, receives the numerical value of the pre-search circuit output, and calculates wrong address；
Correction circuit, for by the data-conversion of errors present；
Characterized in that, the pre-search circuit includes：
Sky search code length calculation electric circuit, truncates code length according to BCH standards code length and BCH and calculates empty search code length；
First Dynamic gene counting circuit, it is first using the empty each bit value for searching for code length binary numeral and adjustment constant calculations
Individual Dynamic gene；
Follow-up Dynamic gene counting circuit, multiple follow-up Dynamic genes are calculated according to the first Dynamic gene；
Error location polynomial mlultiplying circuit, by error location polynomial items be multiplied by respectively the corresponding first adjustment because
Sub or described follow-up Dynamic gene.
4. BCH decoding circuits according to claim 3, it is characterised in that：
Multiple Galois field multipliers of error location polynomial counting circuit described in the pre-search circuit multiplexer.
5. the BCH decoding circuits according to claim 3 or 4, it is characterised in that：
The pre-search circuit also include Dynamic gene register, for store calculate obtain the first Dynamic gene and
The follow-up Dynamic gene.
6.BCH pre-searching methods, it is characterised in that including：
Code length is truncated according to BCH standards code length and BCH and calculates empty search code length；
Using each bit value and the adjustment first Dynamic gene of constant calculations of empty search code length binary numeral；
Multiple follow-up Dynamic genes are calculated according to the first Dynamic gene；
The items of error location polynomial are multiplied by the corresponding first Dynamic gene or the follow-up Dynamic gene respectively.
7. BCH pre-searching methods according to claim 6, it is characterised in that：
The first Dynamic gene obtained and the follow-up Dynamic gene storage will be calculated in a register.
8.BCH error correction methods, including：
Calculate error location polynomial；
It is characterized in that：
BCH pre-searchs are carried out, pre-search step includes：Code length is truncated according to BCH standards code length and BCH and calculates empty search code length；
Using each bit value and the adjustment first Dynamic gene of constant calculations of empty search code length binary numeral；According to the first tune
Integral divisor calculates multiple follow-up Dynamic genes；By error location polynomial items be multiplied by respectively the corresponding first adjustment because
Sub or described follow-up Dynamic gene；
The root of error location polynomial is solved, errors present is calculated；
By the data-conversion of errors present.
9. BCH error correction methods according to claim 8, it is characterised in that：
In the pre-search step, multiplexing calculates Galois field multiplier during error location polynomial.
10. BCH error correction methods according to claim 8 or claim 9, it is characterised in that：
The first Dynamic gene obtained and the follow-up Dynamic gene storage will be calculated in a register.
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| CN102594370A (en) * | 2012-02-27 | 2012-07-18 | 成都国微电子有限公司 | High-efficient low-delay parallel Chien search method and device |
| CN104716965A (en) * | 2015-03-09 | 2015-06-17 | 复旦大学 | BCH soft decoding algorithm and implementation circuit thereof |
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