CN106067825A - BCH pre-search circuit, BCH decoding circuit, BCH pre-searching method and BCH error correction method - Google Patents
BCH pre-search circuit, BCH decoding circuit, BCH pre-searching method and BCH error correction method Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
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Abstract
The present invention provides a kind of BCH pre-search circuit, BCH decoding circuit, BCH pre-searching method and BCH error correction method, and this BCH pre-search circuit includes empty search code length calculation electric circuit, calculates sky search code length according to BCH standard code length and BCH truncate code length；First Dynamic gene counting circuit, has the first Galois field multiplier, each numerical value of the empty long numerical value of searching code of application and the adjustment first Dynamic gene of constant calculations；Follow-up Dynamic gene counting circuit, has the second Galois field multiplier, calculates multiple follow-up Dynamic gene according to first Dynamic gene；Error location polynomial mlultiplying circuit, has the 3rd Galois field multiplier, by every first Dynamic gene being multiplied by correspondence respectively or the follow-up Dynamic gene of error location polynomial.BCH decoding circuit has above-mentioned BCH pre-search circuit.BCH pre-searching method is the method for application BCH pre-search circuit realiration pre-search.The present invention can be greatly reduced the area of the chip of BCH decoding circuit.
Description
Technical field
The present invention relates to BCH Error Correction of Coding decoding field, specifically, be to provide a kind of BCH pre-search circuit, can be to appointing
The BCH shortened code of meaning code length carries out BCH decoding circuit and BCH pre-searching method, the BCH error correction method of pre-search.
Background technology
In the control chip of the mass-memory units such as NandFlash, when data write storage unit it may happen that
Write error or the situation of read error, such as, certain a data should be binary number " 0 ", quilt during write storage unit
Mistake is write as binary number " 1 ".In order to avoid write or the data of readout error, need data are verified, common
After way is write data, writes a part of redundant data artificially for Error Control, can carry out during to ensure data read-out
Error detection and correction.
Bose-Chaudhuri Hocquenghem error correction codes be a kind of be generally used for correct random error cyclic check code, this check code by R.C.Bose,
D.K.Chaudhuri and A.Hocquenghem proposes jointly, and it is a kind of to have that strict Algebraic Structure, error correcting capability be strong, structure
Make the linear block codes of simple, coding relatively other yard feature such as easily.
When using binary system Bose-Chaudhuri Hocquenghem error correction codes to carry out error correction, it usually needs use decoder that the most decoded code word is carried out
Decoding.The number assuming the random error that Bose-Chaudhuri Hocquenghem error correction codes can correct is t, then when decoding, first according to the code word received
R (X) calculates syndrome S1～S2t, then according to syndrome S1～S2tCalculate error location polynomial σ (x), mistake in computation
Position multinomial generally uses IBM iterative algorithm to obtain.Then, finite field gf (2 is usednDuring shortened code on), if truncate
A length of K (the K < 2 of coden-1), then need every Dynamic gene α being multiplied by correspondence in advance of error location polynomial σ (x)L、
α2L、α3L...αtL, thus carry out pre-search, to skip L bit (L=2n-1-K) position that needs not search for searches to shorten Qian Shi
The operation time of rope.Then, application chien search (Chien Search) solves the root of error location polynomial σ (x), thus asks
Solve errors present.Finally, according to errors present, to former data-conversion.Thus can be by the data modification on errors present
For correct data, it is achieved error correction.
Due to by every Dynamic gene α being multiplied by correspondence in advance of error location polynomial σ (x)L、α2L、α3L...αtL
Step in, existing method is typically with pure combination logic and once completes all αL～αtLFinite field multiplier realize, example
As the Chinese invention patent application of Publication No. CN101252361A discloses entitled " a kind of area compact type supporting pre-search
BCH parallel decoding circuit " innovation and creation, the every of error location polynomial σ (x) is disposably multiplied by correspondence by the method exactly
Dynamic gene αL、α2L、α3L...αtL, it is therefore desirable to use t constant multiplier to complete.And, shorten code code length L different
Time, need to store t different coefficient again, if there being y kind to shorten code code length L, then altogether need the number of coefficients meeting of storage
Up to y × t.
But, in the mass-memory unit such as current Flash, Bose-Chaudhuri Hocquenghem error correction codes needs figure place t corrected to be typically larger than 70,
Pure combination logic is caused once to complete the circuit of all finite field multipliers the hugest.And it is various different in order to adapt to
The error correction demand of flash, needs figure place t corrected to differ, and data length also can differ, and therefore typically requires in support
Hundred kinds of different shortening code code lengths L, then the quantity of Dynamic gene will be more than 7000.But, owing to the area of chip is
Limited, it is impossible to by the Dynamic gene α of all different code lengthsL～αtLBeing stored in chip, this causes the BCH decoder can only
A limited number of kind of code length is carried out pre-search, has a strong impact on the decoding speed of BCH decoder.
Summary of the invention
The first object of the present invention is to provide a kind of at finite field gf (2n) time only need to store n adjust constant can be right
Any digit carries out the pre-search circuit of the BCH decoding circuit of error correction.
The second object of the present invention is to provide a kind of at finite field gf (2n) time only need to store n and adjust will not the accounting for of constant
The BCH decoding circuit of Dynamic gene is stored with the area of a large amount of chips.
The third object of the present invention is to provide the BCH pre-searching method that the strong BCH error correction method of a kind of error correcting capability uses.
The fourth object of the present invention is to provide a kind of BCH error correction method that can save chip area.
In order to realize the first above-mentioned purpose, the BCH pre-search circuit that the present invention provides includes that empty search code length calculates electricity
Road, calculates sky search code length according to BCH standard code length and BCH truncate code length；First Dynamic gene counting circuit, having first has
Finite field multiplication device, each numerical value of the empty long numerical value of searching code of application and the adjustment first Dynamic gene of constant calculations；Follow-up adjustment
Factor calculating circuit, has the second Galois field multiplier, calculates multiple follow-up Dynamic gene according to first Dynamic gene；Error bit
Put polynomial multiplication circuit, there is the 3rd Galois field multiplier, by every head being multiplied by correspondence respectively of error location polynomial
Individual Dynamic gene or follow-up Dynamic gene.
From such scheme, owing to first Dynamic gene and multiple follow-up Dynamic gene are not to be stored in advance in core
In sheet, but obtaining by adjusting constant calculations, therefore BCH pre-search circuit need not use the storage of substantial amounts of chip area big
The Dynamic gene of amount.Further, owing to Dynamic gene is to be calculated, therefore BCH pre-search circuit can be to the BCH of any code length
Shortened code carries out pre-search, makes BCH decoding circuit range of application wider.
One preferred scheme is, BCH pre-search circuit also includes Dynamic gene depositor, calculates acquisition for storing
Dynamic gene.
Therefore, it is stored in advance in calculating the multiple Dynamic gene obtained in depositor, follow-up meter can be facilitated
Calculate.
For realizing the second above-mentioned purpose, the BCH decoding circuit that the present invention provides includes that error location polynomial calculates electricity
Road, receives syndrome, and has multiple Galois field multiplier, for mistake in computation position multinomial；Pre-search circuit, receives mistake
The polynomial every value in position by mistake；Mistake address calculating circuit, receives the numerical value of pre-search circuit output, and mistake in computation
Address；Correction circuit, for by the data-conversion of errors present；Wherein, pre-search circuit includes: empty search code length calculates electricity
Road, calculates sky search code length according to BCH standard code length and BCH truncate code length；First Dynamic gene counting circuit, application sky search
Each numerical value of code length numerical value and the adjustment first Dynamic gene of constant calculations；Follow-up Dynamic gene counting circuit, according to first
Dynamic gene calculates multiple follow-up Dynamic gene；Error location polynomial mlultiplying circuit, by every point of error location polynomial
It is not multiplied by the first Dynamic gene of correspondence or follow-up Dynamic gene.
From such scheme, BCH decoding circuit uses and adjusts the multiple Dynamic gene of constant calculations, namely need not pre-
First Dynamic gene corresponding for different shortened codes is stored in the chips, again because adjusting the quantity of constant at finite field gf (2n) time
Only n, general n is less than or equal to 14, is far smaller than the adjustment of the multiple different truncate code lengths of the support mentioned in background technology
The quantity of the factor, therefore can be greatly saved the memory space of storage Dynamic gene, thus allow BCH decoding circuit adapt to difference and cut
Short code code length carries out the occasion of pre-search.
One preferred scheme is, multiple finite field multipliers of pre-search circuit multiplexer error location polynomial counting circuit
Device.
As can be seen here, the area of chip can be greatly saved by multiplexing Galois field multiplier, and will not too much increase
Operation time, advantageously reduces the area of BCH decoding circuit, reduces the production cost of BCH decoding circuit.
For realizing the 3rd above-mentioned purpose, the BCH pre-searching method that the present invention provides include according to BCH standard code length and
BCH truncate code length calculates sky search code length；Each numerical value of the empty long numerical value of searching code of application and the adjustment first tune of constant calculations
Integral divisor；Multiple follow-up Dynamic gene are calculated according to first Dynamic gene；It is right error location polynomial every to be multiplied by respectively
The first Dynamic gene answered or follow-up Dynamic gene.
From such scheme, when carrying out BCH pre-search, it is not necessary to use the Dynamic gene prestored, Dynamic gene
Obtained by adjusting constant calculations, be far smaller than the number of the Dynamic gene of the shortened code of different code length due to the quantity of adjustment constant
Amount, therefore needs the Dynamic gene quantity of storage to greatly reduce during BCH pre-search, thus the area of BCH pre-search circuit.
For realizing the 4th above-mentioned purpose, the BCH error correction method that the present invention provides includes mistake in computation position multinomial；And
And carrying out BCH pre-search, pre-search step includes calculating sky search code length according to BCH standard code length and BCH truncate code length；Application
Each numerical value of the empty long numerical value of searching code and the adjustment first Dynamic gene of constant calculations；Calculate multiple according to first Dynamic gene
Follow-up Dynamic gene；By every first Dynamic gene being multiplied by correspondence respectively or the follow-up Dynamic gene of error location polynomial；
Solve the root of error location polynomial, mistake in computation position；By the data-conversion of errors present.
As can be seen here, when carrying out BCH error correction, Dynamic gene is not to be stored in advance on chip, but by often adjusting
Number calculates and obtains, and so, BCH error correction can carry out pre-search for the BCH shortened code of different code length, fitting of BCH error correction method
Ying Xinggeng is wide.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of BCH decoding circuit embodiment of the present invention.
Fig. 2 is the structured flowchart of BCH pre-search circuit embodiments of the present invention.
Fig. 3 is the structure principle chart of BCH pre-search circuit embodiments of the present invention.
Fig. 4 is the flow chart of BCH error correction method embodiment of the present invention.
Below in conjunction with drawings and Examples, the invention will be further described.
Detailed description of the invention
The BCH error correction method of the present invention is to carry out, based on BCH shortened code, the method that pre-search realizes error correction.The side of the present invention
Method can carry out pre-search to the BCH shortened code of any code length and realize error correction, and therefore to be provided with BCH pre-for BCH decoding circuit
Search circuit.
See Fig. 1, the BCH decoding circuit of the present invention have error location polynomial counting circuit 10, pre-search circuit 20,
Mistake address calculating circuit 30 and error correction circuit 40, Galois field multiplier array 50.
Error location polynomial counting circuit 10 receives the syndrome S calculated by code word R (X)1～S2t, and according to companion
With formula S1～S2tCalculate error location polynomial σ (x).Generally, error location polynomial counting circuit 10 is applied the most limited
Territory multiplier realizes the calculating of error location polynomial, as used common IBM iterative algorithm mistake in computation position multinomial σ
Every u0, u1, the u2 of (x) ... ut, and by every u0, u1, u2 of error location polynomial σ (x) ... the value of ut exports in advance
Search circuit 20.
Pre-search circuit 20 is according to every u0, u1, u2 of error location polynomial σ (x) ... the value of ut is multiplied by correspondence respectively
Dynamic gene, it is thus achieved that pre-search result.
The implementation of pre-search circuit is as in figure 2 it is shown, pre-search circuit 20 is provided with empty search code length calculation electric circuit 21, head
Individual Dynamic gene counting circuit 22, follow-up Dynamic gene counting circuit 23 and error location polynomial mlultiplying circuit 24.
Assume at finite field gf (2n) the maximum code length of BCH code be 2n-1, BCH error correction in maximum code length i.e. the present embodiment
The standard code length of code.Owing to needs use BCH shortened code to be decoded, and the code length of BCH shortened code is generally than maximum code length 2n-
1 is short, it is assumed that the code length of BCH shortened code is K, then empty search code length calculation electric circuit 21 calculates empty search code length L is L=2n-1-K。
So, when carrying out pre-search, skip the L bit data needed not search for, thus efficiency when improving mistake in computation address.
Code length L is searched for, because the numerical value of empty search code length L is not more than (2 with binary representation skyn-1), so sky is searched for
Binary digit a width of n position of code length L, it is assumed that the binary xth position representing empty search code length L with L.x, then have
L=L. (n-1) * 2(n-1)+L.(n-2)*2(n-2)+L.(n-3)*2(n-3)+…+L.1*21+L.0*20
So first Dynamic gene can be obtained
Wherein,For adjusting constant.In the present embodiment, adjusting constant is to preset
Constant.Due to when L.x=0,Therefore, in formula 1, all items are all constant terms, so only
Need to carry out first Dynamic gene α when n constant finite field multiplier can try to achieve empty search code length L of any code lengthLValue.
Therefore, first Dynamic gene counting circuit 22 can arrange Galois field multiplier, and application adjusts constant and sky is searched
Rope code length L each value calculate first Dynamic gene αLValue.
Then, the first adjustment that follow-up Dynamic gene counting circuit 23 is calculated according to first Dynamic gene counting circuit 22
Factor-alphaLValue, calculated for subsequent multiple Dynamic gene α2L～αtL, such as, α2L=αL*αL、α3L=α2L*αL、...αtL=α(t-1)L*
αL, and so on, common t-1 finite field multiplier computing excessively i.e. can calculate and obtain follow-up multiple Dynamic gene.Therefore, after
Continuous Dynamic gene counting circuit 23 can also arrange Galois field multiplier, is used for carrying out t-1 finite field multiplier computing.
Assume that σ (x) is according to syndrome S1～S2tThe error location polynomial calculated, by error location polynomial σ (x)
Every be multiplied by Dynamic gene α respectivelyL、α2L、α3L...αtL, i.e. complete pre-search.Specifically, error location polynomial multiplication electricity
Road 24 is by every Dynamic gene α being multiplied by correspondence respectively of error location polynomial σ (x)L、α2L、α3L...αtL, i.e. errors present
The Section 1 of multinomial σ (x) is multiplied by first Dynamic gene αL, Section 2 be multiplied by second Dynamic gene α2L, and so on, mistake
The t item of position multinomial σ (x) is multiplied by the t Dynamic gene αtL.So, common t finite field multiplier computing excessively i.e. can obtain
Pre-search result U0 ', U1 ', U2 ' ... Ut '.Therefore, error location polynomial mlultiplying circuit 24 can also be provided with confinement and takes advantage of
Musical instruments used in a Buddhist or Taoist mass, is used for carrying out repeatedly finite field multiplier computing.
Then, pre-search circuit 20 calculate obtain pre-search result U0 ', U1 ', U2 ' ... after Ut ', result is exported mistake
Address calculating circuit 30 by mistake.Mistake address calculating circuit 30 is Chien search circuit, calculates error location polynomial σ (x)
Root, the address of the root calculated namely mistake, i.e. the position at wrong data place.Finally, correction circuit 40 is by errors present
On data-conversion, the most just complete correction process.
The present embodiment is provided with Galois field multiplier array 50, is provided with multiple Galois field multiplier in this array.Errors present
Polynomial computation circuit 10 and pre-search circuit 20 all receive the signal of Galois field multiplier array 50, therefore, pre-search electricity
Multiple Galois field multipliers 50 of road 20 actually reused error position polynomial computation circuit 10.Owing to errors present is multinomial
The finite field multiplier operation times of formula counting circuit 10 is about (3t+2) t time, and it is secondary that pre-search circuit 20 needs carry out (2t+n-1)
Finite field multiplier computing.Therefore, when t is bigger, such as t > 40 time, (2t+n-1) is far smaller than (3t+2) t.Therefore, pre-search electricity
The Galois field multiplier of multiplexing mistake in computation position, road 20 polynomial computation circuit 10, both will not take too many operation time, also
A large amount of areas of chip can be saved, reduce the production cost of BCH decoder.
If it should be noted that the finite field multiplier of pre-search circuit 20 reused error position polynomial computation circuit 10
Device, then need not at first Dynamic gene counting circuit 22, follow-up Dynamic gene counting circuit 23, error location polynomial multiplication
Galois field multiplier is set on circuit 24, thus reduces the area of chip.
The typical circuit schematic diagram of pre-search circuit 20 is as it is shown on figure 3, empty search code length calculation electric circuit 21 calculates sky and searches
The numerical value of rope code length L, namely obtains the numerical value of each of sky search code length L.Then, Galois field multiplier array is applied
Galois field multiplier 51 calculates first Dynamic gene αLValue.Meanwhile, first Dynamic gene α is usedLValue, apply finite field
Multiplier 52,53 ... 54 calculate t-1 follow-up Dynamic gene α2L～αtL, multiple Dynamic gene αL、α2L、α3L...αtLOutput is to wrong
By mistake in position polynomial multiplication circuit 24, and error location polynomial mlultiplying circuit 24 calculates pre-search result U0 ', U1 ',
U2’…Ut’。
The workflow of BCH error correction method is introduced below in conjunction with Fig. 4.First, the companion calculated by code word R (X) is received
With formula S1～S2t, and according to syndrome S1～S2tCalculate error location polynomial σ (x), i.e. perform step S1.Then, perform
Pre-search operates, and first carries out step S2, calculates sky search code length L according to the maximum code length of BCH and code length K of BCH shortened code.
Assume n=14, BCH shortened code code length K=12287, then, when the BCH shortened code to any code length carries out pre-search, calculate
Empty search code length L=2n-1-K=214-1-12287=4096.
In the present embodiment, search for code length L with binary representation sky, then have L=1_0000_0000_0000, then
L=0*2^13+1*2^12+0*2^11+0*2^10+......0*2^1+0*2^0.Then, step S3, meter are performed
Calculate first Dynamic gene αLValue, according to method described above, first Dynamic gene
Due toFor adjusting constant, such as Cause
This, can calculate the first Dynamic gene of acquisition
Then, perform step S4, calculate multiple follow-up adjustment constant α2L～αtL, according to aforesaid method, α2L=
0X06BF*0X06BF、α3L=α2L*0X06BF、...αtL=α(t-1)L*0X06BF。
Then, perform step S5, by every Dynamic gene α being multiplied by correspondence respectively of error location polynomial σ (x)L、
α2L、α3L...αtL, result is exported money search module and scans for.Finally, solve error location polynomial σ (x) and obtain mistake
The root of position multinomial σ (x) by mistake, namely performs step S6, thus obtains errors present, and perform step S7, by mistake
The data-conversion of position, it is achieved error correction.
In the BCH error correction method of this enforcement, the finite field multiplier computing needed during pre-search 2t+12 altogether
Secondary, and the finite field multiplier operation times of mistake in computation position multinomial σ (x) is about (3t+2) t time.Therefore, in pre-search mistake
In journey during multiplexing mistake in computation position multinomial use Galois field multiplier, will increase BCH error correction time, increased time
Between ratio c be: c=(2t+12)/((3t+2) t).Owing to present Nand Flash requires that the error correcting capability of BCH would generally be big
In 40bit.As t=40, time ratio c=92/4880=0.019 that multiplexing Galois field multiplier is increased.Visible, error correction
Figure place t is the biggest, and time ratio c increased is the least.Therefore, when carrying out pre-search recurrence of disease at the same time next year mistake in computation position multinomial
Galois field multiplier, will not take too many operation time, but can save a large amount of areas of circuit board, thus reduce storage and set
Standby volume, also reduces the production cost of BCH decoding circuit.
Certainly, above-mentioned scheme is the preferred embodiment of the invention, and actual application is to have more change,
Such as, pre-search circuit can not the Galois field multiplier of reused error position polynomial computation circuit, namely pre-search electricity
Road and error location polynomial counting circuit use respective Galois field multiplier respectively, and these changes do not affect the present invention's
Implement, also should include within the scope of the present invention.
Claims (10)
1.BCH pre-search circuit, it is characterised in that including:
Empty search code length calculation electric circuit, calculates sky search code length according to BCH standard code length and BCH truncate code length；
First Dynamic gene counting circuit, has the first Galois field multiplier, each numerical value of the empty long numerical value of searching code of application
With the adjustment first Dynamic gene of constant calculations；
Follow-up Dynamic gene counting circuit, has the second Galois field multiplier, according to described first Dynamic gene calculate multiple after
Continuous Dynamic gene；
Error location polynomial mlultiplying circuit, has the 3rd Galois field multiplier, and every by error location polynomial takes advantage of respectively
With corresponding described first Dynamic gene or described follow-up Dynamic gene.
BCH pre-search circuit the most according to claim 1, it is characterised in that:
Also include Dynamic gene depositor, calculate, for storing, the described Dynamic gene obtained.
3.BCH decoding circuit, including:
Error location polynomial counting circuit, receives syndrome, and has multiple Galois field multiplier, for mistake in computation position
Multinomial；
Pre-search circuit, receives every value of described error location polynomial；
Mistake address calculating circuit, receives the numerical value of described pre-search circuit output, and mistake in computation address；
Correction circuit, for by the data-conversion of errors present；
It is characterized in that, described pre-search circuit includes:
Empty search code length calculation electric circuit, calculates sky search code length according to BCH standard code length and BCH truncate code length；
First Dynamic gene counting circuit, each numerical value of the empty long numerical value of searching code of application and the adjustment first adjustment of constant calculations
The factor；
Follow-up Dynamic gene counting circuit, calculates multiple follow-up Dynamic gene according to described first Dynamic gene；
Error location polynomial mlultiplying circuit, error location polynomial every is multiplied by respectively the described first adjustment of correspondence because of
Sub or described follow-up Dynamic gene.
BCH decoding circuit the most according to claim 3, it is characterised in that:
The multiple described Galois field multiplier of error location polynomial counting circuit described in described pre-search circuit multiplexer.
5. according to the BCH decoding circuit described in claim 3 or 4, it is characterised in that:
Described pre-search circuit also includes Dynamic gene depositor, calculates, for storing, the described Dynamic gene obtained.
6.BCH pre-searching method, it is characterised in that including:
Sky search code length is calculated according to BCH standard code length and BCH truncate code length；
Each numerical value of the empty long numerical value of searching code of application and the adjustment first Dynamic gene of constant calculations；
Multiple follow-up Dynamic gene are calculated according to described first Dynamic gene；
By every described first Dynamic gene being multiplied by correspondence respectively or the described follow-up Dynamic gene of error location polynomial.
BCH pre-searching method the most according to claim 6, it is characterised in that:
Store calculating the described Dynamic gene obtained in a register.
8.BCH error correction method, including:
Mistake in computation position multinomial；
It is characterized in that:
Carrying out BCH pre-search, pre-search step includes: calculate sky search code length according to BCH standard code length and BCH truncate code length；
Each numerical value of the empty long numerical value of searching code of application and the adjustment first Dynamic gene of constant calculations；According to described first Dynamic gene
Calculate multiple follow-up Dynamic gene；By every described first Dynamic gene being multiplied by correspondence respectively or the institute of error location polynomial
State follow-up Dynamic gene；
Solve the root of error location polynomial, mistake in computation position；
By the data-conversion of errors present.
BCH error correction method the most according to claim 8, it is characterised in that:
Galois field multiplier in described pre-search step, during multiplexing mistake in computation position multinomial.
BCH error correction method the most according to claim 8 or claim 9, it is characterised in that:
Store calculating the described Dynamic gene obtained in a register.
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