CN106030783B - 用于低温附接的混合互连 - Google Patents
用于低温附接的混合互连 Download PDFInfo
- Publication number
- CN106030783B CN106030783B CN201480076416.XA CN201480076416A CN106030783B CN 106030783 B CN106030783 B CN 106030783B CN 201480076416 A CN201480076416 A CN 201480076416A CN 106030783 B CN106030783 B CN 106030783B
- Authority
- CN
- China
- Prior art keywords
- solder
- alloy
- pad
- fusing point
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002156 mixing Methods 0.000 title description 6
- 229910000679 solder Inorganic materials 0.000 claims abstract description 182
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 95
- 239000000956 alloy Substances 0.000 claims abstract description 95
- 239000006071 cream Substances 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 238000000034 method Methods 0.000 claims abstract description 57
- 230000008569 process Effects 0.000 claims abstract description 43
- 238000010992 reflux Methods 0.000 claims abstract description 29
- 239000000463 material Substances 0.000 claims description 28
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 26
- 239000010949 copper Substances 0.000 claims description 25
- 229910052802 copper Inorganic materials 0.000 claims description 21
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 20
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 15
- 239000011135 tin Substances 0.000 claims description 14
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 12
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 12
- 229910052797 bismuth Inorganic materials 0.000 claims description 12
- 229910000765 intermetallic Inorganic materials 0.000 claims description 12
- 229910052718 tin Inorganic materials 0.000 claims description 12
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 9
- 229910052759 nickel Inorganic materials 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 8
- 229910052738 indium Inorganic materials 0.000 claims description 8
- 239000004332 silver Substances 0.000 claims description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 7
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 7
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910052763 palladium Inorganic materials 0.000 claims description 6
- 239000003755 preservative agent Substances 0.000 claims description 6
- 238000004381 surface treatment Methods 0.000 claims description 6
- 229910001316 Ag alloy Inorganic materials 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 238000004891 communication Methods 0.000 description 17
- 238000005538 encapsulation Methods 0.000 description 11
- 239000000843 powder Substances 0.000 description 10
- 238000010168 coupling process Methods 0.000 description 9
- 238000005859 coupling reaction Methods 0.000 description 9
- 230000008878 coupling Effects 0.000 description 8
- 238000000151 deposition Methods 0.000 description 8
- 238000001125 extrusion Methods 0.000 description 7
- 230000004927 fusion Effects 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 238000006467 substitution reaction Methods 0.000 description 4
- 229910001152 Bi alloy Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000008187 granular material Substances 0.000 description 3
- 238000011900 installation process Methods 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 229910001245 Sb alloy Inorganic materials 0.000 description 2
- 229940070259 deflux Drugs 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
- 229910000846 In alloy Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 238000004873 anchoring Methods 0.000 description 1
- 239000002140 antimony alloy Substances 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 239000010426 asphalt Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 239000002648 laminated material Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000002335 preservative effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4867—Applying pastes or inks, e.g. screen printing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05664—Palladium [Pd] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/0569—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13014—Shape in top view being circular or elliptic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2902—Disposition
- H01L2224/29026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29109—Indium [In] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29113—Bismuth [Bi] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92143—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
文中描述了与具有提高的z高度和降低的回流温度的互连有关的设备、过程和***。在实施例中,互连可以包括焊料球和用以将焊料球耦合至基板的焊料膏。焊料球和/或焊料膏可以由具有相对低的熔点的合金和具有相对高的熔点的合金构成。
Description
技术领域
本公开内容的实施例总体上涉及低温互连领域。
背景技术
包含焊料球、并且特别是设置在贯穿模具的互连(TMI)中的焊料球的封装可能要求某一球高度,以在满足球高度要求的同时实现用于室温翘曲和高温翘曲二者的期望模具厚度。高度要求可以基于(例如)对在表面安装过程期间附接至底部片上***(SOC)封装的顶部存储器封装的高度要求。
在一些情况下,所述封装可以包括在沉积焊料球之后形成在封装的基板上的模具物料。模制过程的温度和压力可能导致焊料球的变形和/或塌陷。
附图说明
图1描绘了根据各种实施例的具有一个或多个互连的封装的示例。
图2描绘了根据各种实施例的互连的更加详细的示例。
图3描绘了根据各种实施例的互连中的回流前和回流后二者的不同球高度的示例。
图4描绘了根据各种实施例的用于在基板上形成互连的示例性过程。
图5描绘了根据各种实施例的用于在基板上形成互连的替代的示例性过程。
图6描绘了根据各种实施例的用于在芯片上形成互连的示例性过程。
图7描绘了根据各种实施例的用于在芯片上形成互连的替代的示例性过程。
图8描绘了根据各种实施例的用于形成互连的概括性示例。
图9示意性示出了根据各种实施例的计算装置。
具体实施方式
本公开内容的实施例总体上涉及低温互连领域。在一些实施例中,互连也可以被称为“焊料接头”。然而,为了保持一致性,本文中术语“互连”将被用作互连、焊料接头或焊料凸块的广义术语。
在下面的具体实施方式中,参考形成具体实施方式的部分的附图,在附图中,始终以类似的附图标记表示类似的部分,并且在附图中以举例说明的方式示出了可以实践本公开内容的主题的实施例。应当理解,可以利用其它实施例并且可以做出结构或逻辑上的改变而不脱离本公开内容的范围。因此,不应从限制的意义上理解下述具体实施方式,并且实施例的范围仅由所附权利要求及其等价方案限定。
出于本公开内容的目的,短语“A和/或B”是指(A)、(B)或者(A和B)。出于本公开内容的目的,短语“A、B和/或C”是指(A)、(B)、(c)、(A和B)、(A和C)、(B和C)或者(A、B和C)。
本说明书可以使用诸如顶部/底部、内/外、之上/之下等基于透视的描述。这样的描述只是用来便于讨论,并非意在使文中描述的实施例的应用局限于任何特定的取向。
所述描述可以使用短语“在实施例中”,其可以指代相同或不同实施例中的一者或多者。此外,相对于本公开内容的实施例使用的术语“包括”、“包含”、“具有”等是同义的。
文中可以使用词语“与……耦合”连同其派生词。“耦合”可以表示下述意思中的一者或多者。“耦合”可以表示两个或更多元件直接物理或电接触。然而,“耦合”也可以表示两个或更多元件相互间接接触,但是仍然相互协作或相互作用,并且可以表示在被叙述为相互耦合的元件之间耦合或连接了一个或多个其它元件。术语“直接耦合”可以表示两个或更多元件直接接触。
在各种实施例中,短语“形成、沉积或以其它方式设置在第二特征上的第一特征”可以表示第一特征形成、沉积或者设置在特征层之上,并且第一特征的至少一部分可以与第二特征的至少一部分直接接触(例如,直接物理和/或电接触)或者间接接触(例如,在第一特征和第二特征之间具有一个或更多其它特征)。
可以按照对理解所主张保护的主题最有帮助的方式将各项操作依次描述为多个分立的操作。然而,不应将描述的顺序解释为暗示这些操作必然是顺序相关的。
如文中使用的,术语“模块”可以指代、包括运行一个或多个软件或固件程序的专用集成电路(ASIC)、电子电路、处理器(共享、专用或群组)和/或存储器(共享、专用或群组)、组合逻辑电路、和/或提供所描述的功能的其它适当部件,或者是其部分。
文中的各附图可以描绘芯片、基板或互连的一个或多个层或元件。将文中描绘的元件描绘为不同元件的相对位置的示例。仅出于举例说明的目的来描述元件,并且所述元件并不是按比例绘制的。因此,不应根据附图来假定元件的相对尺寸,并且对于一些实施例而言,只有在具体指示或讨论的地方才可以假定大小、厚度或尺寸。
图1描绘了示例性封装100。封装100包括可以是有机层压材料或陶瓷材料的基板105。封装100可以包括一个或多个互连110。可以使互连110与设置在基板105上的焊盘115耦合。在一些实施例中,焊盘115可以由铜构成,尽管在其它实施例中,焊盘115可以由一些其它导电或导热材料(例如,镍、金、钯、铂或其合金)构成。在一些实施例中,焊盘115可以具有一般设置在焊盘115的外表面上并且置于焊盘115与互连110之间的表面加工或表面处理(finish)。表面处理可以由诸如镍、钯、金、铜或有机可焊性保存剂(preservative)等材料构成。
在一些实施例中,封装100还可以包括一般设置在互连110和/或焊盘115周围并与之横向相邻的模具物料120。模具物料120可以包括一个或多个贯穿模具的通孔125。可以使用一种或多种方法(例如,物理、化学或光学蚀刻)在模具物料120中形成通孔125。在一些实施例中,可以将模具物料120挤到基板105上,以使其至少部分地覆盖互连110,并且然后可以将通孔125蚀刻到模具物料120中。在其它实施例中,可以将模具物料120挤到基板105上,并且可以例如通过使用罩或其它遮蔽元件来保护互连110,以使模具物料120不覆盖互连110。
图2更加详细地描绘了诸如互连110等互连的示例。具体而言,图2描绘了可以与互连110之一类似的互连200。互连200由焊料球205以及大致置于焊料球205与焊盘215之间的焊料膏210组成,焊盘215可以与图1的焊盘115类似。在一些实施例中,金属间化合物(IMC)220通常可以置于焊料膏210与焊盘215之间,如下文将更加详细解释的。焊盘215可以设置在可以与图1的基板105类似的基板225上。
在一些实施例中,焊料球205可以由包括锡、银和铜(SAC)的合金构成。在其它实施例中,焊料球205可以是锡和锑的合金、无共晶(off-eutectic)锡和铜、具有铜芯的SAC壳球、具有聚合物芯的SAC壳球、或者一些其它类型的具有相对高的熔点的焊料球,如下文更加详细描述的。在一些实施例中,焊料球205可以是无铅的。在一些实施例中,焊料球205的熔点可以是217摄氏度。在其它实施例中,焊料球205的熔点可以高于217摄氏度,例如240摄氏度或更高。在其它实施例中,焊料球205的熔点可以处于大约180摄氏度与大约280摄氏度之间。如文中所使用的,焊料球205或者包括焊料球205的合金或材料的熔点可以被称为“相对高的”熔点,以将焊料球205的熔点与焊料膏210或者下文讨论的低温焊料(LTS)合金的熔点区分开。
例如,在一些实施例中,焊料膏210可以是LTS合金。例如,LTS合金可以是或者包括:锡和铋的合金(SnBi);锡、铋、镍和铜的合金(SnBiNiCu);锡、铋、铜和锑的合金(SnBiCuSb);锡、银和铋的合金(SnAgBi);锡和铟的合金(SnIn);锡、铟和铋的合金(SnlnBi);或者铋和/或铟以及与焊料球205的熔点相比具有相对低的熔点的一些其它合金的组合。在一些实施例中,焊料膏210可以是无铅的。在一些实施例中,焊料膏210可以具有低于200摄氏度的熔点,例如175摄氏度的熔点,尽管在其它实施例中,焊料膏210可以具有较低熔点或者处于大约120摄氏度与大约180摄氏度之间的熔点。在一些实施例中,期望的是焊料膏210的熔点比焊料球205的熔点低25摄氏度左右。
通过使用熔点比焊料球205的熔点低的焊料膏210,可以对互连200的回流过程加以控制,以使得回流温度高于焊料膏210的熔点,但是低于焊料球205的熔点。具体而言,回流过程可以包括通过直接施加提高的温度和/或压力来加热焊料膏210和/或焊料球205,以使焊料膏210和/或焊料球205液化或熔化。该液化可能导致焊料膏210和/或焊料球205与基板225接合。例如,如果在200摄氏度执行回流过程,那么焊料膏210可以熔化并且可以与焊盘215化学和/或物理接合,与此同时焊料球205可以不显著熔化或以其它方式发生变形。结果,互连200可以具有比传统互连大的z高度,该高度被测量为从焊盘215开始的距离。例如,互连200可以具有处于290微米与310微米之间的z高度。该z高度可以比传统互连的z高度高大约32%到41%。
暂时转向图3,图3描绘了对于具有相对高的熔点的焊料球(例如焊料球205)和具有相对低的熔点的焊料膏(例如焊料膏210)的一个实施例而言的回流后焊料球高度对照回流前焊料球直径的比较。图3的实施例假定大约21微米的阻焊剂(SR)厚度。在实施例中,SR可以是诸如基板225的基板的最外层。可以看出,对于0.3毫米到0.65毫米的间距而言,与回流前焊料球直径相比,回流后焊料球高度可以降低大约30%到50%。
返回图2,在一些实施例中,焊料膏210可以是诸如上文描述的LTS合金中的一种或多种(例如SnBi、SnBiNiCu等)的LTS合金与具有相对高的熔点的合金(例如上文相对于焊料球205所描述的合金)的组合。例如,在一个实施例中,焊料膏210可以包括SnBi和SAC。在一些实施例中,焊料膏210可以包括近似相等的量的SnBi和SAC,尽管在其它实施例中两种材料之比可以发生变化。
可能期望的是将由近似相等的量的LTS合金和SAC构成的焊料膏210的实施例用于图1的封装100中。具体地,如上所述,可以在互连110设置在基板105上之后挤出模具物料120。然而,在一些实施例中,可以在从165摄氏度到175摄氏度的温度下借助于压力挤出模具物料120,所述温度可以接近于诸如具有大约175摄氏度的熔点的焊料膏210等焊料膏的熔点。因此,模具物料120的挤出可能对焊料膏210造成不利影响,例如,使其发生不期望出现的熔化和塌陷或者其它形式的变形。
然而,使用由LTS合金和SAC构成的焊料膏210可以减小塌陷或变形的量。具体地,可以在发生回流过程之前将LTS合金和SAC以粉末形式沉积在基板210上。之后,随着温度升高到LTS合金的可以是如上文所述的大约175摄氏度的熔点以上,LTS合金可以熔化并润湿SAC粉末颗粒。如上所述,互连200的温度可以由于例如回流、模具挤压或者一些其它过程而升高。由于来自LTS合金和SAC的锡的相互扩散,回流后的焊料膏210的总金属成分不再相同,而是可以由于锡的量相对较高而对熔化温度造成决定性影响。换言之,由于LTS合金和SAC的组合,焊料膏210的总体熔化温度可能高于175摄氏度。因此,相对较高的熔化温度可以防止或者减少焊料膏210在模具物料120的挤出期间发生再熔化。
此外,在模具物料120的挤出期间,焊料膏210的LTS合金可以熔化并润湿焊料球205。此外,焊料膏210的LTS合金可以与下层焊盘215的金属化,并且特别是焊盘215的表面处理发生反应,以形成IMC 220。IMC220可以由(例如)镍、铜、锡、铋或其合金构成。IMC 220可以用来将回流的焊料膏210和/或焊料球205至少部分地锚固到焊盘215,从而提高互连200在LTS合金的熔点以上的温度上更好地抵御与模具物料120的挤压相关联的压力的能力。
在一些实施例中,可以根据LTS合金与SAC之比来调节包括LTS合金和SAC两者的焊料膏210的熔化温度。具体地,随着焊料膏210中的SAC的浓度增大,焊料膏210的熔点可以进一步增大到LTS合金的熔点以上。此外,随着焊料膏210中的SAC的浓度增大,可以降低焊料膏210在模具挤压过程期间可能塌陷或以其它方式变形的程度,这可以导致互连200的更大的z高度。
图4描绘了用于在基板225上形成诸如互连200的互连的一个示例性过程。具体地,图4描绘了用于将诸如焊料球205的一个或多个焊料球置于诸如基板225的基板上的示例性过程。在一些实施例中,可以将图4的过程描述为受控塌陷芯片连接(C4)碰撞过程,并且可以将由焊料球和焊料膏形成的互连称为第一级互连(FLI)。具体地,第一级互连可以是将芯片耦合至基板或者诸如印刷电路板等板的互连。
在实施例中,可以将具有多个焊盘405的基板400(其可以与上文描述的基板105和焊盘115类似)置于模具410中。模具可以包括具有多个开口420的型板415。模具410可以与被配置为分配LTS膏430的分配器425耦合或者以其它方式设置在该分配器之下。在该实施例中,图4的LTS膏430可以是诸如SnBi的LTS合金或者上文所述的一些其它LTS合金。
可以在435执行印刷过程,以使可以与LTS膏430类似的LTS膏440通过开口420直接沉积到基板400的焊盘405上。之后,可以去除型板415。接下来,可以在445执行球安装过程。球安装过程可以包括将具有多个开口455的第二型板450置于LTS膏440、焊盘405和基板400之上。可以与焊料球205类似的一个或多个焊料球460可以置于开口455内并直接处于LTS膏440之上。在实施例中,焊料球460可以由诸如SAC等具有相对高的熔点的合金构成,如上文所讨论的。
可以去除型板450,并且可以执行回流过程。在实施例中,回流过程可以包括施加温度和/或压力,以使基板400、焊盘405、LTS膏440和焊料球460的温度总体上升高到LTS膏440的熔点以上,但是在焊料球460的熔点以下。在一些实施例中,回流过程可以包括将诸如模具物料120的模具物料挤到基板上。
在一些实施例中,可以在高于焊料球460的熔点的温度上执行回流过程。在该实施例中,可以在去除型板450之前执行回流过程。焊料球460和LTS膏440可以在回流过程期间熔化并在焊盘405和/或基板400上形成混合LTS/SAC焊料球,即,由LTS合金和SAC二者构成的焊料球。
在执行回流过程之后,可以执行去焊剂过程。具体地,可以通过电气、光学、机械或化学手段去除在图4的过程中使用的任何助焊剂。
图5描绘了将诸如焊料球205的一个或多个焊料球置于诸如基板225的基板上的替代的示例性过程。在一些实施例中,可以将图5的过程描绘为“微碰撞”过程,并且可以将由焊料球和焊料膏形成的互连称为第一级互连,如上文所述。
在实施例中,可以将具有多个焊盘505的基板500(其可以与上文描述的基板400和焊盘405类似)置于模具510中。模具可以包括具有多个开口520的型板515。模具510可以与被配置为分配助焊剂530的分配器525耦合或者以其它方式设置在分配器525之下。助焊剂530可以由(例如)松脂、溶剂、酸、胺或其组合构成。
可以在535执行印刷过程,以使可以与助焊剂530类似的助焊剂540通过开口520直接沉积到基板500的焊盘505上。之后,可以去除型板515。接下来,可以在545执行球安装过程。球安装过程可以包括将具有多个开口555的第二型板550置于助焊剂540、焊盘505和基板500之上。可以与焊料球205类似的一个或多个焊料球560可以置于开口555内并且直接位于助焊剂540之上。在一些实施例中,焊料球可以由具有相对高的熔点的合金(例如SAC)与具有相对低的熔点的合金(例如,诸如SnBi的LTS)合金的混合物构成,如上文所讨论的。
可以去除型板550,并且可以执行回流过程。在实施例中,可以在总体上高于焊料球560的LTS合金的熔点、但是低于焊料球560的SAC的熔点的温度上执行回流过程。如上文关于图2所述的,LTS合金可以熔化并与焊盘505和/或基板500接合,而SAC则不熔化或以其它方式变形。在该过程中,与如果使用仅由LTS合金构成的焊料球相比,由焊料球560和焊盘505形成的互连的z高度可以更高。
在执行回流过程之后,可以执行去焊剂过程。具体地,可以通过电气、光学、机械或化学手段去除在图5的过程中使用的任何助焊剂。
图6描绘了用以生成具有熔点相对高的合金(例如SAC)与熔点相对低的合金(例如SnBi)的组合的互连的示例性过程。例如,可以使用图6的过程生成用于芯片到芯片附接过程的具有SAC/LTS混合结构的互连。在一些实施例中,可以将芯片到芯片附接过程称为局部存储器互连(LMI)过程。
图6描绘了可以包括管芯605的芯片600。管芯605可以包括多个凸块610,所述凸块可以是铜或者一些其它导电材料或合金。可以将具有相对高的熔点的焊料615合金(例如SAC)沉积在凸块610上。在625,可以将芯片600,并且特别是凸块610和焊料615浸渍或以其它方式没入到具有相对低的熔点的合金的池620(例如,诸如SnBi等LTS合金的池620)中。在一些实施例中,可以控制芯片600的浸渍深度,使得仅焊料615或仅焊料615的一部分没入到池620中。在630,然后可以从熔池620中去除芯片600。在一些实施例中,可以在受控速度下去除芯片600。
通过在625将焊料615没入到池620中,熔化的LTS合金可以将焊料615润湿,这导致由于池620中的熔化的LTS合金的强表面张力和润湿力而形成混合LTS/SAC合金。由于池620可以是熔化的LTS或者具有相对低的熔点的一些其它合金,将SAC没入到池620中可以不导致SAC熔化或以其它方式变形。因此,芯片600可以具有由混合LTS/SAC合金构成的多个凸块或互连635。
图7描绘了用于生成具有熔点相对高的合金(例如SAC)和熔点相对低的LTS合金(例如SnBi)的组合的互连的过程的替代示例。与图6的过程类似,也可以使用图7的过程生成用于芯片到芯片附接过程的具有SAC/LTS混合结构的互连。
与图6类似,图7可以包括芯片700,该芯片包括具有多个凸块710的管芯705,其中,凸块710上设置有焊料715,它们可以分别类似于芯片600、管芯605、凸块610和焊料615。在实施例中,焊料715可以由熔点相对高的合金(例如SAC)构成。
没有如例如关于图6所示的那样将焊料715浸没到熔化的LTS的池中,可以使用冲压机722将LTS 720冲压到凸块710上,并且具体是冲压到焊料715上,如725所示。施加LTS720的冲压机722可以获得如上文关于互连635所描述的由混合LTS/SAC合金构成的凸块或互连735。
图4到图7的实施例可以表现出各种优点。例如,由于包括混合LTS/SAC合金的互连的相对较低的熔点,可以向FLI或LMI实施低温回流过程或低温热压缩接合(TCB)过程。由于相对低的温度的回流或接合过程,可以改善芯片附接后封装翘曲,并且提高TCB过程运转率。此外,对于LMI过程,由于LTS合金在相对较低的温度下熔化,因而可以提高原位环氧树脂TCB过程期间的二氧化硅颗粒捕集。LTS合金可以润湿芯片的焊盘,例如芯片的铜焊盘,这可以在原位环氧树脂TCB过程的环氧树脂固化之前将二氧化硅颗粒驱逐出焊盘,由此限制二氧化硅颗粒在高温下的移动。
图8描绘了用于形成诸如图2的互连200等互连的概括性过程。具体地,在800,可以在诸如基板225的基板上沉积具有相对低的熔点的合金,例如诸如SnBi的LTS合金。具体地,可以将LTS合金沉积在基板上的诸如焊盘215的焊盘上。
接下来,在805,可以将具有相对高的熔点的合金(例如SAC)沉积在基板上。具体地,可以将合金沉积在基板的焊盘上。在一些实施例中,可以将800和805的要素预先混合并将其大体上同时沉积在基板上。在一些实施例中,可以在800的将LTS沉积在基板上之前,在805将合金沉积在基板上。在实施例中,在800沉积的LTS合金和在805沉积的SAC可以是互连200的焊料膏210。
接下来,在810,诸如焊料球205的焊料球沉积在LTS合金和SAC上。最后,可以在815发生回流过程。如上文所述,回流过程可以作为模具物料挤压过程的结果而发生。在一些实施例中,回流过程可以发生在等于或者高于LTS合金的熔点但是低于SAC的熔点的温度上。因此,所形成的互连(例如互连200)可以具有从基板开始测量的z高度,所述z高度高于一些传统互连的z高度。
应当理解,上文关于图4到图8描述的过程只是可以如何形成诸如互连200的互连的示例。在其它实施例中,可以执行额外的或者替代的过程。
可以将本公开内容的实施例实施到使用任何适当的硬件和/或软件来进行期望的配置的***中。图9示意性示出根据本发明的一种实施方式的计算装置900。计算装置900可以容纳诸如母板902的板。母板902可以包括若干部件,其包括但不限于处理器904以及至少一个通信芯片906。处理器904可以物理和电耦合到母板902。在一些实施方式中,也可以使至少一个通信芯片906物理和电耦合到母板902。在其它实施方式中,通信芯片906可以是处理器904的部分。在一些实施例中,可以使用互连(例如,互连200)或者使用上文关于图4到图8描述的过程中的一个或多个过程所形成的另一互连来使通信芯片906、处理器904或者计算装置900的其它部件中的一者或多者相互耦合。
根据其应用,计算装置900可以包括其它部件,这些部件可以或可以不物理和电耦合至母板902。这些其它部件可以包括但不限于易失性存储器(例如,动态随机存取存储器(DRAM))920、非易失性存储器(例如,只读存储器(ROM))924、闪速存储器922、图形处理器930、数字信号处理器(未示出)、密码处理器(未示出)、芯片组926、天线928、显示器(未示出)、触摸屏显示器932、触摸屏控制器946、电池936、音频编译码器(未示出)、视频编译码器(未示出)、功率放大器941、全球定位***(GPS)装置940、罗盘942、加速度计(未示出)、陀螺仪(未示出)、扬声器950、照相机952和大容量存储装置(例如硬盘驱动器、光盘(CD)、数字通用盘(DVD)等)(未示出)。图9中未示出的其它部件可以包括麦克风、滤波器、振荡器、压力传感器或者视频识别器(RFID)芯片。
通信芯片906可以实现用于往返于计算装置900的数据传输的无线通信。术语“无线”及其派生词可以用于描述可以通过使用经调制的电磁辐射经由非固体介质来传递数据的电路、装置、***、方法、技术、通信通道等。该术语并不暗示相关联的装置不包含任何线,虽然在一些实施例中它们可以不包含线。通信芯片906可以实现多种无线标准或协议中的任一个,包括但不限于电气与电子工程师协会(IEEE)标准(包括Wi-Fi(IEEE 802.11族)、IEEE 802.16标准(例如IEEE 802.16-2005修订))、长期演进(LTE)计划连同任何修订、更新和/或修正(例如,高级LTE计划、超移动宽带(UMB)计划(也被称为“3GPP2”)等)。与IEEE802.16兼容的BWA网络通常被称为WiMAX网络,其是代表微波接入全球互操作性的首字母缩略词,其为通过IEEE 802.16标准的一致性和互操作性测试的产品的证明标志。通信芯片906可以根据全球移动通信***(GSM)、通用分组无线服务(GPRS)、通用移动电信***(UMTS)、高速分组接入(HSPA)、演进HSPA(E-HSPA)或LTE网络来操作。通信芯片906可以根据增强数据GSM演进(EDGE)、GSM EDGE无线接入网络(GERAN)、通用地面无线接入网络(UTRAN)或演进UTRAN(E-UTRAN)来操作。通信芯片906可以根据码分多址(CDMA)、时分多址(TDMA)、数字增强无绳电信(DECT)、演进数据优化(EV-DO)、其派生物以及被指定为3G、4G、5G和更高代的任何其它无线协议来操作。在其它实施例中,通信芯片906可以根据其它无线协议来操作。
计算装置900可以包括多个通信芯片906。例如,第一通信芯片906可以专用于较短范围的无线通信,例如,Wi-Fi和蓝牙,第二通信芯片906可以专用于较长范围的无线通信,例如,GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其它。
计算装置900的处理器904可以包括封装中的管芯。术语“处理器”可以指对来自寄存器和/或存储器的电子数据进行处理以将该电子数据变换为可以存储在寄存器和/或存储器内的其它电子数据的任何装置或装置的部分。
在各种实施方式中,计算装置900可以是膝上型电脑、上网本、笔记本、超级本、智能电话、平板电脑、个人数字助理(PDA)、超级移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字照相机、便携式音乐播放器或者数字视频记录仪。在其它实施方式中,计算装置900可以是处理数据的任何其它电子装置,例如,诸如一体式传真机或打印装置的一体式装置。
示例
示例1可以包括一种设备,其包括:基板,其具有设置于基板上的焊盘;与焊盘耦合的焊料球,所述焊料球包括锡、银和铜的合金;以及总体置于焊盘与焊料球之间的焊料膏,所述焊料膏包括合金和低温焊料(LTS),所述低温焊料的熔点低于或者等于所述合金的熔点。
示例2可以包括示例1的设备,其中,所述焊盘包含铜并且具有镍、钯、金、铜或有机可焊性保存剂的表面处理。
示例3可以包括示例1的设备,其中,所述合金为无铅合金。
示例4可以包括示例1的设备,其中,所述LTS包括铟或铋。
示例5可以包括示例1的设备,其中,所述焊料膏包括近似等量的所述合金和所述LTS。
示例6可以包括示例1-5中的任何一者的设备,还包括:模具物料,其与基板耦合并且总体上被设置为与焊料球和焊料膏横向相邻并总体上包围焊料球和焊料膏。
示例7可以包括示例1-5中的任何一者的设备,还包括设置在焊料膏与基板之间的金属间化合物(IMC)。
示例8可以包括示例7的设备,其中,IMC包括镍、铜、锡、铋或其合金。
示例9可以包括示例1-5中的任何一者的设备,其中,所述合金具有在大约180摄氏度与大约280摄氏度之间的熔点。
示例10可以包括示例9的设备,其中,所述焊料膏具有等于或者高于175摄氏度的熔点。
示例11可以包括一种方法,其包括:在基板的焊盘上沉积焊料膏,所述焊料膏包括熔点低于或等于217摄氏度的低温焊料(LTS)以及锡、银和铜的合金;将包括所述合金的焊料球置于所述焊料膏上,以使所述焊料膏设置在所述焊盘与焊料球之间;以及在高于LTS的熔点并低于合金的熔点的温度下执行回流过程。
示例12可以包括示例11的方法,其中,所述LTS包括铟或铋。
示例13可以包括示例11的方法,其中,所述合金的熔点处于大约180摄氏度与大约280摄氏度之间。
示例14可以包括示例11-13中的任何一者的方法,还包括在低温回流过程中将金属间化合物(IMC)形成在焊料球与焊盘之间并且与焊盘直接相邻。
示例15可以包括11-13中的任何一者的方法,其中,所述焊盘包括铜。
示例16可以包括一种设备,其包括:基板,其具有第一侧和第二侧、安装在第一侧上的管芯以及设置在基板的第一侧上的焊盘;与基板的第一侧耦合的模具物料,所述模具物料具有所述焊盘之上的贯穿模具的通孔;焊料接头,其置于所述贯穿模具的通孔内并且与焊盘耦合,所述焊料接头包括:包括无铅合金的焊料球;以及总体上置于基板与焊料球之间的焊料膏,所述焊料膏包括总体上等量的无铅合金和熔点等于或低于175摄氏度的低温焊料(LTS),其中,焊料接头被配置为对管芯的电信号进行布线。
示例17可以包括示例16的设备,其中,无铅合金包括锡、银和铜。
示例18可以包括示例16的设备,其中,LTS包括铟或铋。
示例19可以包括示例16-18中的任何一者的设备,其中,所述无铅合金具有217摄氏度的熔点。
示例20可以包括示例19的设备,其中,所述焊料膏具有大于175摄氏度的熔点。
示例21可以包括示例16-18中的任何一者的设备,其中,所述焊盘包括铜,具有镍、钯、金、铜或有机可焊性保存剂的表面处理。
示例22可以包括一个或多个非暂态计算机可读介质,包括指令,所述指令在被计算装置的一个或多个处理器执行时使得计算装置执行示例11-15中的任何一者的方法。
各种实施例可以包括上述实施例的任何适当组合,包括上文通过逻辑乘形式(和)描述的实施例的替代(或)实施例(例如,“和”可以是“和/或”)。此外,一些实施例可以包括具有存储于其上的指令的一个或多个制品(例如,非暂态计算机可读介质),所述指令在被执行时触发上文所述的实施例中的任何实施例的动作。此外,一些实施例可以包括具有用于实施上述实施例的各种操作的任何适当的措施的设备或***。
对本发明的所示出的实施方式的以上描述(包括摘要中描述的内容)并非旨在穷举,或将本发明限制于所公开的精确形式。尽管出于举例说明的目的在文中描述了本发明的具体实施方式和示例,但是相关领域技术人员将认识到,在本发明的范围内各种等价修改都是可能的。
在考虑上述具体实施方式的情况下,可以对本发明做出这些修改。不应将下面的权利要求中使用的术语理解为使本发明限制于说明书和权利要求中所公开的具体实施方式。相反,本发明的范围将完全由所附权利要求确定,应当根据所建立的权利要求的解释原则来理解权利要求。
Claims (19)
1.一种包括基板的设备,所述基板具有设置于所述基板上的焊盘,所述设备还包括:
与所述焊盘耦合的焊料球,所述焊料球包括锡、银和铜的合金;以及
总体上置于所述焊盘与所述焊料球之间的焊料膏,所述焊料膏包括所述合金以及熔点低于或等于所述合金的熔点的低温焊料(LTS),其中,所述焊料膏包括总体上等量的所述合金和所述低温焊料。
2.根据权利要求1所述的设备,其中,所述焊盘包含铜并且具有镍、钯、金、铜或有机可焊性保存剂的表面处理。
3.根据权利要求1所述的设备,其中,所述合金为无铅合金。
4.根据权利要求1所述的设备,其中,所述低温焊料包括铟或铋。
5.根据权利要求1-4中的任一项所述的设备,还包括:
模具物料,其与所述基板耦合并且总体上被设置为与所述焊料球和所述焊料膏横向相邻并总体上包围所述焊料球和所述焊料膏。
6.根据权利要求1-4中的任一项所述的设备,还包括设置在所述焊料膏与所述基板之间的金属间化合物(IMC)。
7.根据权利要求6所述的设备,其中,所述金属间化合物包括镍、铜、锡、铋或其合金。
8.根据权利要求1-4中的任一项所述的设备,其中,所述合金具有处于180摄氏度与280摄氏度之间的熔点。
9.根据权利要求8所述的设备,其中,所述焊料膏具有大于或等于175摄氏度的熔点。
10.一种与焊料膏一起使用的方法,包括:
将所述焊料膏沉积在基板的焊盘上,所述焊料膏包括熔点低于或等于217摄氏度的低温焊料(LTS)、以及锡、银和铜的合金;
将包括所述合金的焊料球置于所述焊料膏上,以使所述焊料膏设置在所述焊盘与所述焊料球之间;以及
在高于所述低温焊料的熔点并低于所述合金的熔点的温度下执行回流过程,其中,所述焊料膏包括总体上等量的所述合金和所述低温焊料。
11.根据权利要求10所述的方法,其中,所述低温焊料包括铟或铋。
12.根据权利要求10所述的方法,其中,所述合金的熔点处于180摄氏度与280摄氏度之间。
13.根据权利要求10-12中的任一项所述的方法,还包括:在低温回流过程期间,将金属间化合物(IMC)形成在所述焊料球与所述焊盘之间并且与所述焊盘直接相邻。
14.根据权利要求10-12中的任一项所述的方法,其中,所述焊盘包括铜。
15.一种包括基板的设备,所述基板具有第一侧和第二侧、安装在所述第一侧上的管芯以及设置在所述基板的所述第一侧上的焊盘,所述设备还包括:
与所述基板的所述第一侧耦合的模具物料,所述模具物料具有在所述焊盘之上的贯穿模具的通孔;
焊料接头,其置于所述贯穿模具的通孔内并且与所述焊盘耦合,所述焊料接头包括:
包括无铅合金的焊料球;以及
总体上置于所述基板与所述焊料球之间的焊料膏,所述焊料膏包括总体上等量的所述无铅合金和低温焊料(LTS),所述低温焊料的熔点低于或者等于175摄氏度,其中,所述焊料接头被配置为对所述管芯的电信号进行布线,其中,所述无铅合金包括锡、银和铜。
16.根据权利要求15所述的设备,其中,所述低温焊料包括铟或铋。
17.根据权利要求15-16中的任一项所述的设备,其中,所述无铅合金具有217摄氏度的熔点。
18.根据权利要求17所述的设备,其中,所述焊料膏具有大于175摄氏度的熔点。
19.根据权利要求15-16中的任一项所述的设备,其中,所述焊盘包含铜以及镍、钯、金、铜或有机可焊性保存剂的表面处理。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2014/032084 WO2015147844A1 (en) | 2014-03-27 | 2014-03-27 | Hybrid interconnect for low temperature attach |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106030783A CN106030783A (zh) | 2016-10-12 |
CN106030783B true CN106030783B (zh) | 2019-06-18 |
Family
ID=54196160
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201480076416.XA Active CN106030783B (zh) | 2014-03-27 | 2014-03-27 | 用于低温附接的混合互连 |
Country Status (7)
Country | Link |
---|---|
US (1) | US20160260679A1 (zh) |
JP (1) | JP2017508293A (zh) |
KR (1) | KR20160113686A (zh) |
CN (1) | CN106030783B (zh) |
DE (1) | DE112014006271B4 (zh) |
GB (1) | GB2540060B (zh) |
WO (1) | WO2015147844A1 (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20210157787A (ko) | 2020-06-22 | 2021-12-29 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI230103B (en) * | 2000-06-12 | 2005-04-01 | Hitachi Ltd | Semiconductor module and circuit substrate connecting to semiconductor device |
CN1738039A (zh) * | 2004-08-13 | 2006-02-22 | 株式会社东芝 | 半导体器件及其制造方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11307565A (ja) * | 1998-04-24 | 1999-11-05 | Mitsubishi Electric Corp | 半導体装置の電極およびその製造方法ならびに半導体装置 |
JP2002076605A (ja) * | 2000-06-12 | 2002-03-15 | Hitachi Ltd | 半導体モジュール及び半導体装置を接続した回路基板 |
US6433425B1 (en) * | 2000-09-12 | 2002-08-13 | International Business Machines Corporation | Electronic package interconnect structure comprising lead-free solders |
JP4656275B2 (ja) * | 2001-01-15 | 2011-03-23 | 日本電気株式会社 | 半導体装置の製造方法 |
US6784086B2 (en) * | 2001-02-08 | 2004-08-31 | International Business Machines Corporation | Lead-free solder structure and method for high fatigue life |
JP2003303842A (ja) * | 2002-04-12 | 2003-10-24 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP4008799B2 (ja) * | 2002-11-20 | 2007-11-14 | ハリマ化成株式会社 | 無鉛はんだペースト組成物およびはんだ付け方法 |
US6897761B2 (en) * | 2002-12-04 | 2005-05-24 | Cts Corporation | Ball grid array resistor network |
US6854636B2 (en) * | 2002-12-06 | 2005-02-15 | International Business Machines Corporation | Structure and method for lead free solder electronic package interconnections |
US20040155358A1 (en) * | 2003-02-07 | 2004-08-12 | Toshitsune Iijima | First and second level packaging assemblies and method of assembling package |
JP4130668B2 (ja) * | 2004-08-05 | 2008-08-06 | 富士通株式会社 | 基体の加工方法 |
JP4939891B2 (ja) * | 2006-10-06 | 2012-05-30 | 株式会社日立製作所 | 電子装置 |
US8378485B2 (en) * | 2009-07-13 | 2013-02-19 | Lsi Corporation | Solder interconnect by addition of copper |
US8232643B2 (en) * | 2010-02-11 | 2012-07-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lead free solder interconnections for integrated circuits |
JP5837339B2 (ja) * | 2011-06-20 | 2015-12-24 | 新光電気工業株式会社 | 半導体装置の製造方法及び半導体装置 |
-
2014
- 2014-03-27 WO PCT/US2014/032084 patent/WO2015147844A1/en active Application Filing
- 2014-03-27 KR KR1020167023490A patent/KR20160113686A/ko active Search and Examination
- 2014-03-27 DE DE112014006271.5T patent/DE112014006271B4/de active Active
- 2014-03-27 US US14/430,131 patent/US20160260679A1/en not_active Abandoned
- 2014-03-27 GB GB1614555.9A patent/GB2540060B/en active Active
- 2014-03-27 JP JP2016554385A patent/JP2017508293A/ja active Pending
- 2014-03-27 CN CN201480076416.XA patent/CN106030783B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI230103B (en) * | 2000-06-12 | 2005-04-01 | Hitachi Ltd | Semiconductor module and circuit substrate connecting to semiconductor device |
CN1738039A (zh) * | 2004-08-13 | 2006-02-22 | 株式会社东芝 | 半导体器件及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20160260679A1 (en) | 2016-09-08 |
JP2017508293A (ja) | 2017-03-23 |
DE112014006271T5 (de) | 2016-12-01 |
CN106030783A (zh) | 2016-10-12 |
GB2540060B (en) | 2019-02-13 |
GB2540060A (en) | 2017-01-04 |
KR20160113686A (ko) | 2016-09-30 |
GB201614555D0 (en) | 2016-10-12 |
DE112014006271B4 (de) | 2023-03-09 |
WO2015147844A1 (en) | 2015-10-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10770387B2 (en) | Integrated circuit package substrate | |
US11817364B2 (en) | BGA STIM package architecture for high performance systems | |
US9257405B2 (en) | Multi-solder techniques and configurations for integrated circuit package assembly | |
US9305855B2 (en) | Semiconductor package devices including interposer openings for heat transfer member | |
US8920934B2 (en) | Hybrid solder and filled paste in microelectronic packaging | |
CN110024117B (zh) | 用于***级封装设备的与铜柱连接的裸管芯智能桥 | |
CN111937145A (zh) | 具有改进的顺应性的电互连 | |
CN105981159A (zh) | 具有设置在封装体内的无源微电子器件的微电子封装件 | |
US9299602B2 (en) | Enabling package-on-package (PoP) pad surface finishes on bumpless build-up layer (BBUL) package | |
TWI736072B (zh) | 封裝結構與其形成方法 | |
CN106030783B (zh) | 用于低温附接的混合互连 | |
US20210375811A1 (en) | Pin-grid-array-type semiconductor package | |
DE112015007162T5 (de) | Stapelchipgehäuse mit wäremleitenden strukturen durch-die-form zwischen einem unteren chip und einem wärmeleitenden material | |
US20160372433A1 (en) | Methods of fabricating a semiconductor package | |
CN109935567A (zh) | 用于超高密度第一级互连的双焊接方法 | |
US11804420B2 (en) | Core-shell particles for magnetic packaging | |
US20180315731A1 (en) | Inkjet printable mask apparatus and method for solder on die technology | |
CN108847396B (zh) | 倒装方法 | |
JP2008034632A (ja) | インターポーザーとその製造方法及び半導体モジュール並びにその製造方法 | |
CN117546285A (zh) | 用于细间距异构应用的第一级互连凸块下金属化部 | |
US9735032B2 (en) | System and method for manufacturing a fabricated carrier | |
JP2007335832A (ja) | フリップチップパッケージ及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |