CN106019118A

CN106019118A - Method for determining invalid position of power MOS

Info

Publication number: CN106019118A
Application number: CN201610329281.4A
Authority: CN
Inventors: 马香柏
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2016-05-18
Filing date: 2016-05-18
Publication date: 2016-10-12

Abstract

The invention discloses a method for determining the invalid position of a power MOS, and the method comprises the steps: 1, removing a surface passivation layer of a sample chip, and exposing metal; 2, locating a bright point through employing a bright point positioning tool; 3, recording the bright point and the shapes of crystal grains surrounding the bright point; 4, setting a mark nearby the bright point; 5, finding a mark position under a focused ion beam table, finding a crystal grain boundary corresponding to the bright point, and carrying out the slice analysis, thereby finding the invalid position.

Description

The decision method of power MOS invalid position

Technical field

The present invention relates to semiconductor failure analysis field, particularly relate to a kind of power MOS invalid position Decision method.

Background technology

Power MOS is many electronic conductivities device, have that switching speed is fast, input impedance is high, easy driving, There is not the advantages such as secondary-breakdown phenomenon, application is widely.The feature of power MOS is device top layer There is large-area metal to cover, be to repeat cell (body born of the same parents) unit in a large number below metal.

The conventional needle failure analysis to integrated circuit, especially lost efficacy pointing technology, can be according to luminescence Position, this luminous point position, around there is different wirings, it is easy to find this by domain Individual position, in follow-up physical failure analysis, as long as combining layout data successively go research, so that it may Invalid position is easily found, as shown in Figure 1 to eventually find origin ceasing to be effective.But for power MOS, top layer has substantial amounts of metal and covers, as shown in Figure 2, and is a large amount of under metal covers Identical body born of the same parents, for repetitive, be all identical cell around all of cell, be difficult to carry out Further location because near bright spot all as, i.e. there is no feature pattern, it is impossible to find tool Body invalid position, brings difficulty to failure analysis location.

Summary of the invention

The technical problem to be solved is to provide the decision method of a kind of power MOS invalid position, Solve the problem that power MOS invalid position is difficult to determine.

For solving the problems referred to above, the present invention provides the decision method of a kind of power MOS invalid position, bag Containing the steps:

Step 1, removes sample chip surface passivation layer, exposes metal；

Step 2, uses bright spot location instrument to orient bright spot；

Step 3, uses technique of laser imaging, records bright spot and the pattern of crystal grain about；

Step 4, is made around mark position in bright spot；

Step 5, finds mark position under focused ion bundle board, and the crystal grain finding bright spot corresponding is handed over Boundary, carries out slice analysis, thus finds invalid position.

In described step 1, remove surface passivation layer and use reactive ion etching machine platform.

In described step 2, bright spot location tool kit contains but is not limited only to EMMI, OBIRCH, LC.

In described step 4, mark position distance bright spot 5～50 μm, use laser to get labelling.

The decision method of power MOS invalid position of the present invention, can position mistake simply and easily The invalid position of effect chip, it is simple to defect is analyzed timely and effectively.Mode of the present invention Be applicable not only to that power MOS is this large amount of chip repeating unit cell, for other chip also Equally applicable.

Accompanying drawing explanation

Fig. 1 is that integrated circuit bright spot positions schematic diagram.

Fig. 2 is the body born of the same parents figure after power MOS (Metal Oxide Semiconductor) device top view and removal surface metal.

Fig. 3 is to remove the schematic diagram after chip surface passivation layer.

Fig. 4 is to use instrument location, bright spot location bright spot schematic diagram.

Fig. 5 is the schematic diagram that the pattern of bright spot and crystal grain about is recorded in laser imaging.

Fig. 6 laser gets mark position schematic diagram.

Fig. 7 is slice analysis schematic diagram.

Fig. 8 is the inventive method flow chart.

Detailed description of the invention

The decision method of a kind of power MOS invalid position of the present invention, comprises the steps:

Step 1, as it is shown on figure 3, use reactive ion etching machine platform, by sample chip surface passivation layer Remove, expose the metal level on surface.

Step 2, uses bright spot location instrument, as bright spot oriented by the instruments such as EMMI, OBIRCH, LC, Speckle as shown in Figure 4.

Step 3, uses technique of laser imaging, records bright spot and the pattern of crystal grain about, such as figure Shown in 5.

Step 4, as shown in Figure 6, near bright spot, distance L is the position use laser of 5～50 μm Make a mark position on surface.

Step 5, finds the mark position shown in Fig. 6 under focused ion bundle board, and finds bright spot Corresponding crystal grain has a common boundary, and carries out slice analysis, thus finds invalid position, can under this tangent plane picture To see the concrete defect of chip as it is shown in fig. 7, analyze the origin cause of formation of this defect, can be to follow-up technique It is adjusted.

These are only the preferred embodiments of the present invention, be not intended to limit the present invention.For this area For technical staff, the present invention can have various modifications and variations.All in the spirit and principles in the present invention Within, any modification, equivalent substitution and improvement etc. made, should be included in the protection model of the present invention Within enclosing.

Claims

1. the decision method of a power MOS invalid position, it is characterised in that: comprise the steps:

Step 1, removes sample chip surface passivation layer, exposes metal；

Step 2, uses bright spot location instrument to orient bright spot；

Step 4, is made around mark position in bright spot；

2. the decision method of power MOS invalid position as claimed in claim 1, it is characterised in that: In described step 1, remove surface passivation layer and use reactive ion etching machine platform.

3. the decision method of power MOS invalid position as claimed in claim 1, it is characterised in that: In described step 2, bright spot location tool kit contains but is not limited only to EMMI, OBIRCH, LC.

4. the decision method of power MOS invalid position as claimed in claim 1, it is characterised in that: In described step 4, mark position distance bright spot 5～50 μm, use laser to get labelling.