CN105990433A - Low resistance trench type metal oxide semiconductor field effect transistor and self-alignment process thereof - Google Patents
Low resistance trench type metal oxide semiconductor field effect transistor and self-alignment process thereof Download PDFInfo
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- CN105990433A CN105990433A CN201510096547.0A CN201510096547A CN105990433A CN 105990433 A CN105990433 A CN 105990433A CN 201510096547 A CN201510096547 A CN 201510096547A CN 105990433 A CN105990433 A CN 105990433A
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Abstract
The invention relates to the field of semiconductors and particularly relates to a low resistance trench type metal oxide semiconductor field effect transistor and a self-alignment process thereof. The low resistance trench type metal oxide semiconductor field effect transistor comprises a substrate which is orderly provided with an epitaxial layer, a P- type well, and an N+ type well. The epitaxial layer, the P- type well and the N+ type well have trench type gate doping polysilicon as gates. An intermediate layer dielectric is above the N+ type well, metal is above the intermediate layer dielectric, and a contactor is between the metal and the intermediate layer dielectric, wherein the refractory metal silicide WSI which is in contact with the contactor is above the trench type gate doping polysilicon. In order to reduce gate resistance, the WSI is deposited on polycrystalline silicon, the conducting area of the polysilicon in a trench is increased, and since the resistance of the WSI is lower than that of the polycrystalline silicon, the gate resistance of the trench is greatly reduced compared with the gate resistance in a normal process.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly to the groove of a kind of shallow degree of depth of little live width
The low resistance self-registered technology of MOS.
Background technology
Line along with trench mosfet (Trench MOSFet)
Width is more and more less, the degree of depth is increasingly deeper, and resistance becomes more and more higher, thus it is dynamic to add switch
Make the power switched loss caused；In the conventional processing procedure of Trench MOSFet, Hardmask
It is served only for doing the hard mask layer of trench etch, all removes before gate oxidation, accordingly even when to polycrystalline
Silicon carries out dropping low-resistance process, it is also difficult to meet the requirement of alignment precision in the case of little live width.
Summary of the invention
For the deficiency of prior art, in order to reduce resistance, the present invention deposits difficulty on the polysilicon
Molten metal silicide WSI, increases the conducting area of polysilicon in groove, owing to the resistance value ratio of WSI is many
The resistance of crystal silicon is lower, and therefore the grid resistance of the groove of the present invention can hinder than the grid in normal process
Value is greatly reduced.
The WSI deposition of the present invention is realized by self-registered technology, deposited sacrificial oxidation on hard curtain cover
Layer, before gate oxidation, removes described sacrificial oxide layer and the hard mask layer of part, member-retaining portion
Hardmask, the hardmask remained form the autoregistration of WSI, WSI CMP when,
The WSI on hardmask surface is worn away, and the WSI between hardmask is retained when, the most both
Save the autoregistration of WSI, turn avoid the requirement for alignment precision in the case of little live width.
In order to realize foregoing invention purpose, the technical solution adopted in the present invention is as follows:
A kind of low resistance trench mosfet, comprises:
Substrate, is disposed with epitaxial layer, P-type trap, N+ type trap thereon, described epitaxial layer,
P-type trap, N+ type trap have the groove type grid DOPOS doped polycrystalline silicon as grid, described N+ type trap
Top has interlayer dielectric, has metal above described interlayer dielectric, described metal with in
There is between interlayer dielectric catalyst, wherein, have above described grid polycrystalline silicon and contact with described
The refractory metal silicide WSI of device contact.
Further, the thickness of described WSI is
A kind of self-registered technology of low resistance trench mosfet, bag
Containing following steps:
Step 1: provide a substrate, the upper surface in described substrate arranges epitaxial layer, described epitaxial layer
Upper surface arranges curtain layer of hard hood；
Step 2: use the microspur lithographic trench region of 0.1～0.4 μm on described curtain layer of hard hood, and
Described hard mask layer is etched；Then use and be etched in the trench region being positioned at described curtain layer of hard hood
The groove of 0.4～1.0 μm is formed on the described epitaxial layer of lower section；
Step 3: form the groove being used as grid in described step 2 on the basis of, form sacrificial oxide layer,
Then take out described sacrificial oxide layer and the hard mask layer of part；
Step 4: on the basis of the groove of described step 3, is formedGate oxide also
DepositionDOPOS doped polycrystalline silicon；
Step 5: carry out back carving to the DOPOS doped polycrystalline silicon of step 4 deposition, and form polysilicon recess；
Step 6: utilize under the autoregistration effect of remaining hard mask layer, in the polysilicon that step 5 is formed
Groove deposits insoluble metal silicide WSI, and described WSI is chemically-mechanicapolish polished；
Step 7: remove remaining hard mask layer, and the WSI formed in step 6 is annealed, shape
Become grid.
Further, the thickness of described hard mask layer is
Further, the thickness of described sacrificial oxide layer isThe sacrificial oxide layer removed
With the gross thickness of hard mask layer it is
Further, the degree of depth at quarter of returning described in step 5 isThe groove formed is deep
Degree is
Further, the deposit thickness of described WSI is
Accompanying drawing explanation
Fig. 1 is the structure of the low resistance trench mosfet of the present invention
Schematic diagram；
Fig. 2-5 shows the low resistance trench mosfet of the present invention
Self-registered technology flow process.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage more clear bright from, below in conjunction with the accompanying drawings
And embodiment, the present invention is further elaborated.Should be appreciated that described herein specifically
Embodiment only in order to explain the present invention, is not intended to limit the present invention.
As it is shown in figure 1, the low resistance trench mosfet of the present invention
Comprise substrate 1, be disposed with epitaxial layer 2, P-type trap 3, N+ type trap 4 on the base 1, described
Epitaxial layer 2, P-type trap 3, N+ type trap 4 have the groove type grid DOPOS doped polycrystalline silicon 9 as grid,
There is above described N+ type trap 4 interlayer dielectric 5, above described interlayer dielectric 5, there is metal
6, there is between described metal 6 and interlayer dielectric 5 catalyst 7, wherein, described grid doping is many
There is above crystal silicon 9 the refractory metal silicide WSI 8 contacted with described catalyst 7.The present invention's
In one preferred embodiment, the thickness of described WSI 8 is
Below by Fig. 2-5 and combine Fig. 1 the low resistance trench metal-oxide half of the present invention is described
The self-registered technology flow process of conductor field-effect transistor.As shown in Figure 2, it is provided that a substrate 1, described
The upper surface of substrate 1 arranges epitaxial layer 2, and described epitaxial layer upper surface arranges curtain layer of hard hood 10；
Described curtain layer of hard hood 10 uses the microspur lithographic trench region of 0.1～0.4 μm, and to described
Hard mask layer 10 is etched；Then use and be etched under the trench region being positioned at described curtain layer of hard hood 10
The groove 11 of 0.4～1.0 μm is formed on the described epitaxial layer 2 of side；
On the basis of forming the groove 11 being used as grid, forming thickness isSacrificial oxide layer
(not shown), then removes described sacrificial oxide layer and the hard mask layer of part, the sacrificial oxidation of removal
The gross thickness of layer and hard mask layer is
After removing described sacrificial oxide layer and the hard mask layer of part, as it is shown on figure 3, in groove and surplus
Remaining hard mask layer surface is formedGate oxide 12, and in groove 11 depositDOPOS doped polycrystalline silicon 9；
Carrying out back carving to the DOPOS doped polycrystalline silicon of above-mentioned deposition, and form polysilicon recess, returning the degree of depth at quarter isThe depth of groove formed is
As shown in Figure 4, under the autoregistration effect of remaining hard mask layer, at above-mentioned polysilicon recess
Middle deposit thickness isInsoluble metal silicide WSI 8, and described WSI 8 is changed
Learn mechanical polishing；
Finally, remove remaining hard mask layer, and above-mentioned WSI 8 is annealed, form grid.
On the basis of forming the grid with WSI 8, as it is shown in figure 5, further in described extension
Above Ceng, infiltration forms P-type trap 3 and N+ type trap 4 successively, and respectively to described P-type trap 3 and N+
Type trap 4 makes annealing treatment.Interlayer dielectric 5 it is sequentially depositing after above-mentioned process, and to centre
Layer electrolyte is etched forming catalyst 7, and described catalyst 7 contacts with WSI 8, then in institute
State deposition metal in interlayer dielectric 5, finally obtain the low resistance trench metal oxidation of the present invention
Thing semiconductor field effect transistor (sees Fig. 1).
Embodiment described above only have expressed embodiments of the present invention, and it describes more concrete and detailed
Carefully, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that, it is right
For those of ordinary skill in the art, without departing from the inventive concept of the premise, it is also possible to do
Going out some deformation and improvement, these broadly fall into protection scope of the present invention.Therefore, patent of the present invention
Protection domain should be as the criterion with claims.
Claims (7)
1. a low resistance trench mosfet, comprises:
Substrate, is disposed with epitaxial layer, P-type trap, N+ type trap thereon, described epitaxial layer,
P-type trap, N+ type trap have the groove type grid DOPOS doped polycrystalline silicon as grid, described N+ type trap
Top has interlayer dielectric, has metal above described interlayer dielectric, described metal with in
There is between interlayer dielectric catalyst,
Wherein, above described grid polycrystalline silicon, there is the refractory metal silicide contacted with described catalyst
WSI。
Low resistance trench metal-oxide semiconductor field effect transistor the most according to claim 1
Pipe, it is characterised in that the thickness of described WSI is
3. a self-registered technology for low resistance trench mosfet,
Comprise the steps of
Step 1: provide a substrate, the upper surface in described substrate arranges epitaxial layer, described epitaxial layer
Upper surface arranges curtain layer of hard hood；
Step 2: use the microspur lithographic trench region of 0.1～0.4 μm on described curtain layer of hard hood, and right
Described hard mask layer is etched；Then use and be etched under the trench region being positioned at described curtain layer of hard hood
The groove of 0.4～1.0 μm is formed on the described epitaxial layer of side；
Step 3: form the groove being used as grid in described step 2 on the basis of, form sacrificial oxide layer,
Then take out described sacrificial oxide layer and the hard mask layer of part；
Step 4: on the basis of the groove of described step 3, is formedGate oxide also
DepositionDOPOS doped polycrystalline silicon；
Step 5: carry out back carving to the DOPOS doped polycrystalline silicon of step 4 deposition, and form polysilicon recess；
Step 6: utilize under the autoregistration effect of remaining hard mask layer, in the polysilicon that step 5 is formed
Groove deposits insoluble metal silicide WSI, and described WSI is chemically-mechanicapolish polished；
Step 7: remove remaining hard mask layer, and the WSI formed in step 6 is annealed, shape
Become grid.
Self-registered technology the most according to claim 3, it is characterised in that described hard mask layer
Thickness is
Self-registered technology the most according to claim 3, it is characterised in that described sacrificial oxide layer
Thickness beThe sacrificial oxide layer removed and the gross thickness of hard mask layer are
Self-registered technology the most according to claim 3, it is characterised in that returning described in step 5
Quarter, the degree of depth wasThe depth of groove formed is
Self-registered technology the most according to claim 3, it is characterised in that the deposition of described WSI
Thickness is
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510096547.0A CN105990433A (en) | 2015-03-04 | 2015-03-04 | Low resistance trench type metal oxide semiconductor field effect transistor and self-alignment process thereof |
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| CN201510096547.0A CN105990433A (en) | 2015-03-04 | 2015-03-04 | Low resistance trench type metal oxide semiconductor field effect transistor and self-alignment process thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108735334A (en) * | 2017-04-18 | 2018-11-02 | E.I.内穆尔杜邦公司 | Conducting paste composition and with its manufactured semiconductor device |
| CN115029681A (en) * | 2021-03-03 | 2022-09-09 | 和舰芯片制造(苏州)股份有限公司 | Load effect degree characterization method during thin film deposition in LPCVD (low pressure chemical vapor deposition) process and deposition method |
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| US6376887B2 (en) * | 1998-05-26 | 2002-04-23 | Nec Corporation | Semiconductor memory having buried digit lines |
| US20020115257A1 (en) * | 2001-02-19 | 2002-08-22 | Hitachi, Ltd. | Insulated gate type semiconductor device and method for fabricating the same |
| CN101009328A (en) * | 2006-01-24 | 2007-08-01 | 万国半导体股份有限公司 | Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions |
| CN103165669A (en) * | 2011-12-09 | 2013-06-19 | 上海华虹Nec电子有限公司 | Trench power metal oxide semiconductor (MOS) device and manufacturing method thereof |
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2015
- 2015-03-04 CN CN201510096547.0A patent/CN105990433A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6376887B2 (en) * | 1998-05-26 | 2002-04-23 | Nec Corporation | Semiconductor memory having buried digit lines |
| US20020115257A1 (en) * | 2001-02-19 | 2002-08-22 | Hitachi, Ltd. | Insulated gate type semiconductor device and method for fabricating the same |
| CN101009328A (en) * | 2006-01-24 | 2007-08-01 | 万国半导体股份有限公司 | Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions |
| CN103165669A (en) * | 2011-12-09 | 2013-06-19 | 上海华虹Nec电子有限公司 | Trench power metal oxide semiconductor (MOS) device and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108735334A (en) * | 2017-04-18 | 2018-11-02 | E.I.内穆尔杜邦公司 | Conducting paste composition and with its manufactured semiconductor device |
| CN115029681A (en) * | 2021-03-03 | 2022-09-09 | 和舰芯片制造(苏州)股份有限公司 | Load effect degree characterization method during thin film deposition in LPCVD (low pressure chemical vapor deposition) process and deposition method |
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Application publication date: 20161005 |