CN104465404B - The manufacture method of radio frequency LDMOS device - Google Patents
The manufacture method of radio frequency LDMOS device Download PDFInfo
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- CN104465404B CN104465404B CN201410837468.6A CN201410837468A CN104465404B CN 104465404 B CN104465404 B CN 104465404B CN 201410837468 A CN201410837468 A CN 201410837468A CN 104465404 B CN104465404 B CN 104465404B
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 70
- 229920005591 polysilicon Polymers 0.000 claims abstract description 70
- 239000002184 metal Substances 0.000 claims abstract description 68
- 229910052751 metal Inorganic materials 0.000 claims abstract description 68
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 44
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 44
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 21
- 230000008569 process Effects 0.000 claims abstract description 15
- 230000026267 regulation of growth Effects 0.000 claims abstract description 8
- 239000003990 capacitor Substances 0.000 claims abstract description 6
- 239000000126 substance Substances 0.000 claims abstract description 4
- 238000001039 wet etching Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 139
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 24
- 229910052710 silicon Inorganic materials 0.000 claims description 24
- 239000010703 silicon Substances 0.000 claims description 24
- 150000002500 ions Chemical class 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 230000003213 activating effect Effects 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28255—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66719—With a step of forming an insulating sidewall spacer
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of manufacture method of radio frequency LDMOS device, including step：The gate dielectric layer of growth regulation one after p-well is formed in the epitaxial layer；It is that it is placed only in drift region to carry out chemical wet etching to the first gate dielectric layer；The gate dielectric layer of growth regulation two；Deposit plus lithographic etch process formation polysilicon gate；Form channel region, drift region, source-drain area and P+ draw-out areas；Form side wall；Deposit metal silicide block media layer；The forming region that quarter autoregistration defines metal silicide is returned to carrying out dielectric layer；Deposit metal is gone forward side by side row metal silication.Energy autoregistration of the invention defines the metal silicide forming region of device, moreover it is possible to reduce the coupled capacitor between the grid of device and drain electrode.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method, more particularly to a kind of system of radio frequency LDMOS device
Make method.
Background technology
For lifted more than breakdown voltage 50V radio frequency lateral fet (RF LDMOS) radio-frequency performance, it is necessary to
Reduce parasitic capacitance and resistance.
In existing process, to reduce resistance, using polysilicon and the lamination of metal silicide；Metal silicide can be with
Deposited together with polysilicon, such as tungsten silicon, but it is general more than 5 ohm per square resistance；Another is deposit metal, such as titanium
Or cobalt (Co) etc. can obtain the resistance of every 2 ohm of square (Ti).
Because RFLDMOS grid width is below 0.5 micron, while to improve breakdown voltage, the close drain terminal of polysilicon gate
Side is low-doped drift region, it is impossible to do low-resistance metal silication；So due to alignment precision the problem of, it is difficult to only open many
The blocking layer of metal silicide of crystal silicon grid and the barrier layer for retaining drift region, namely due to alignment precision, to polysilicon
When blocking layer of metal silicide at the top of grid open definition, the region of opening will not be opened just at the top of polysilicon gate
Region can to polysilicon gate lateral offset, when being displaced to outside the close drain terminal side of polysilicon gate, at the top of drift region
Barrier layer can also be opened, so as to can also form metal silicide at the top of drift region, and metallic silicon is formed at the top of drift region
Compound and drift region are not inconsistent for the requirement of low-doped high resistance and high withstand voltage.Therefore photoetching process can not be directly used in existing process
Open at the top of polysilicon gate to form metal silicide.
Metal silicide is formed at the top of polysilicon gate in order to open RFLDMOS devices, in a kind of existing process
It is that carving technology is returned using BARC ARCs (Bottom Anti Reflective coating, BARC), utilizes BARC's
The difference of height of flowable and grid, that is, form the thickness of thin formed after BARC at the top of polysilicon gate, outside polysilicon gate
Thickness it is thick, so return comprehensively carve after only the region at the top of polysilicon gate can be exposed, the region outside polysilicon gate is still
Protected by dielectric layer, i.e., the blocking layer of metal silicide on polysilicon gate can be removed by Alignment Method；Then open again
It is other to need the region of metal silication, finally carry out metal silication.Existing this method can autoregistration define polysilicon gate
The metal silicide forming region at top, but also need to define source region and drain region using the extra photoetching process of a step
Form the region of metal silicide.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of manufacture method of radio frequency LDMOS device, and energy autoregistration is determined
Justice goes out the metal silicide forming region of device, moreover it is possible to reduce the coupled capacitor between the grid of device and drain electrode.
In order to solve the above technical problems, the manufacture method for the radio frequency LDMOS device that the present invention is provided comprises the following steps：
Step 1: forming surface of silicon formation epitaxial layer, p-well is formed in the epitaxial layer, afterwards the gate medium of growth regulation one
Layer.
Step 2: removing first gate dielectric layer, described outside the forming region of drift region using lithographic etch process
First gate dielectric layer of the forming region of drift region retains.
Step 3: the gate dielectric layer of growth regulation two, the thickness of second gate dielectric layer is less than first gate dielectric layer
Thickness.
Step 4: depositing polysilicon and to the polysilicon carry out chemical wet etching formation polysilicon gate, by the polysilicon gate
The grid structure to form radio frequency LDMOS device is superimposed with the second gate dielectric layer of its bottom；The second of the polysilicon gate
Extend sideways to above second gate dielectric layer.
Step 5: the first of progress first time p-type ion implanting formation channel region, the channel region and the polysilicon gate
Side autoregistration；Carry out the second side of second of N-type ion implanting formation drift region, the drift region and the polysilicon gate
Autoregistration；Third time N-type source and drain ion implanting formation source region and drain region are carried out, the source region is located in the channel region and and institute
The first side autoregistration of polysilicon gate is stated, the drain region is the second side in the drift region simultaneously with second gate dielectric layer
Face autoregistration；The 4th p-type ion implanting formation P+ draw-out area is carried out, the P+ draw-out areas are located in the channel region and and institute
State source contact, for the channel region to be drawn；Using thermal annealing to the channel region, the drift region, the source region, institute
Drain region and the P+ draw-out areas is stated to enter the channel region and the drift region after line activating and propulsion, thermal annealing and respectively from both sides prolong
The bottom of the polysilicon gate is reached, the channel region surface covered by the polysilicon gate is used to form raceway groove.
Step 6: using deposit and returning side formation side wall of the carving technology in the polysilicon gate.
Step 7: deposit metal silicide block media layer.
Step 8: to the metal silicide block media layer in the radio frequency LDMOS device region and the second gate
Dielectric layer carve, described in Hui Kehou at the top of polysilicon gate, outside the side wall of the polysilicon gate first side and described
Silicon outside first gate dielectric layer second side exposes, the thickness requirement of first gate dielectric layer deposited described in step one
Ensure by step 6 return carve and step 8 return carve after still with a hook at the end and certain thickness and cover the drift region so that
Autoregistration defines the forming region of metal silicide, and the forming region of the metal silicide is the region that silicon exposes.
Step 9: deposit metal, carries out the forming region for the metal silicide that metal silication is defined in autoregistration
Form the metal silicide.
Further improve is that the material of first gate dielectric layer is oxide layer.
Further improve be, the thickness of first gate dielectric layer meet can autoregistration define the metallic silicon
Under conditions of the forming region of compound, the radio frequency LDMOS device is reduced by the thickness for increasing by first gate dielectric layer
Grid and the coupled capacitor of drain electrode.
Further improve is that the thickness of first gate dielectric layer is 300 angstroms to 800 angstroms.
Further improve is that the material of second gate dielectric layer is oxide layer.
Further improve is the side wall medium layer thickness deposited during the side wall to be formed in step 6 for 400 angstroms extremely
600 angstroms.
Further improve is that oxygen of the side wall medium layer deposited during the side wall successively by being superimposed is formed in step 6
SiClx and silicon nitride composition.
Further improve is to return the damage carved and required to first gate dielectric layer when side wall is formed in step 6
Vector is less than 100 angstroms.
Further improvement is that the material of the metal silicide block media layer deposited in step 7 is oxidation
Silicon,
Further improve is that the thickness of the metal silicide block media layer is 300 angstroms to 700 angstroms.
Further improvement is that the thickness of the polysilicon deposited in step 4 is 2500 angstroms to 3500 angstroms.
Further improve is that the metal that step 9 is deposited is tungsten, titanium, cobalt.
Further improve also is comprised the following steps after step 9：
Step 10: forming faraday shield layer, it is covered on the ledge structure at the second side of the polysilicon gate, institute
Stating isolation between faraday shield layer and the polysilicon gate of its bottom has shielding dielectric layer；
Step 11: carrying out deep etching, the deep trouth is gone forward side by side through the source region, the channel region and the epitaxial layer
Enter into the silicon substrate；Metal is filled in the deep trouth and forms the deep contact hole, the deep contact hole by the source region,
The channel region, the epitaxial layer and silicon substrate electrical connection；
Step 12: forming interlayer film, contact hole and front metal layer pattern.
The present invention has the advantages that：
1st, the present invention is covered in the drift region surface of radio frequency LDMOS device by forming the first gate dielectric layer, utilizes first
Protection of the gate dielectric layer to drift region, can carry out returning to carve comprehensively defining metal silicide simultaneously to radio frequency LDMOS device region
Forming region, so the present invention can realize that autoregistration defines the metal silicide forming region of device；Because autoregistration is fixed
Justice need not use photoetching process, so cost is low, and can also eliminate the registration problems that photoetching process is brought, the size of device
It can accomplish smaller.
2nd, the present invention is covered in drift region surface by the first gate dielectric layer, and the thickness of the first gate dielectric layer is more than second
The thickness of dielectric layer, can to isolate thicker dielectric layer between polysilicon gate and drift region, so between grid and drain electrode
Parasitic capacitance can be lower, so the present invention can also reduce the coupled capacitor between the grid of device and drain electrode, this electric capacity is defeated
The direct-coupling for entering and exporting, reducing this electric capacity has very big lifting to radio-frequency performance；Simultaneously in the second side of polysilicon gate
The thickness of i.e. the first gate dielectric layer is set greater than the thickness of second dielectric layer i.e. after the gate dielectric layer thickness increase of drain terminal at end
After degree, the longitudinal electric field of drain terminal can be reduced, has lifting to the robustness of device, has inhibitory action to hot carrier in jection (HCI).
3rd, radio frequency LDMOS device of the present invention is generally required integrates to be formed with other MOS devices, so the first grid is situated between
Matter layer can simultaneously be formed with other MOS devices with thick gate medium, so in actual fabrication process, the first gate dielectric layer
Formed simultaneously with existing thick gate medium, deposit and the lithographic etch process of formation will not be increased, so the present invention can be realized
In the case where not increasing reticle, the autoregistration definition of the metal silicide forming region of radio frequency LDMOS device is realized.
4th, the metal silication of source of the present invention is the side wall of the i.e. autoregistration polysilicon gate of self-aligning grid, can further be dropped
The ON resistance of low device, and increase the saturation current of device.
5th, because the first side that channel region is the i.e. autoregistration polysilicon gate in grid side of autoregistration source is injected and picked
Enter, the doping concentration close to drain region one side channel region under polysilicon gate is relatively low, the gate dielectric layer thickness on increase leakage one side
Threshold voltage is not influenceed using the first thicker gate dielectric layer.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is the manufacture method flow chart of radio frequency LDMOS device of the embodiment of the present invention；
Fig. 2A-Fig. 2 I be radio frequency LDMOS device of the embodiment of the present invention each step of manufacture method in device architecture schematic diagram.
Embodiment
As shown in figure 1, being the manufacture method flow chart of radio frequency LDMOS device of the embodiment of the present invention；As Fig. 2A to Fig. 2 I institute
Show, be radio frequency LDMOS device of the embodiment of the present invention each step of manufacture method in device architecture schematic diagram；The embodiment of the present invention is penetrated
The manufacture method of frequency LDMOS device comprises the following steps：
Step 1: as shown in Figure 2 A, forming the surface of silicon substrate 1 and forming epitaxial layer 2, p-well 3 is formed in epitaxial layer 2, afterwards
The gate dielectric layer 4 of growth regulation one.In embodiments of the present invention, the silicon substrate 1 is p-type heavy doping, and the epitaxial layer 2 is that p-type is light
Doping, the epitaxial layer 2 can be superimposed by epitaxial layer to be formed.
The material of first gate dielectric layer 4 is oxide layer.The thickness requirement of first gate dielectric layer 4 of the deposit
Ensure by subsequent step six return carve and step 8 return carve after still with a hook at the end and certain thickness and cover drift region 8, from
And autoregistration defines the forming region of metal silicide 13.In addition, the thickness of first gate dielectric layer 4 can be certainly in satisfaction
Alignment is defined under conditions of the forming region of the metal silicide 13, by the thickness for increasing by first gate dielectric layer 4
Reduce the grid of the radio frequency LDMOS device and the coupled capacitor of drain electrode.
Preferably, the thickness of first gate dielectric layer 4 is 300 angstroms to 800 angstroms, the thickness of first gate dielectric layer 4
Representative value be 550 angstroms.
Radio frequency LDMOS device of the embodiment of the present invention can be integrated in other MOS devices with a piece of silicon substrate 1,
At this moment, first gate dielectric layer 4 can as other MOS devices using this thickness gate dielectric layer, namely both energy
It is enough to be formed simultaneously, so first gate dielectric layer 4 that the embodiment of the present invention is formed in radio frequency LDMOS device region and not needing
The light shield that the new depositing step of increase and increase are formed, namely using the other MOS integrated with radio frequency LDMOS device
The original gate dielectric layer deposit of device and photoetching process can be formed.
Step 2: as shown in Figure 2 B, the first grid outside the forming region of drift region 8 is removed using lithographic etch process
Dielectric layer 4, first gate dielectric layer 4 of the forming region of the drift region 8 retain.
Step 3: as shown in Figure 2 C, the gate dielectric layer 5 of growth regulation two, the thickness of second gate dielectric layer 5 is less than described the
The thickness of one gate dielectric layer 4.The material of second gate dielectric layer 5 is oxide layer.Second gate dielectric layer 5 is the present invention
Embodiment radio frequency LDMOS device required gate dielectric layer in itself.
Step 4: as shown in Figure 2 D, depositing polysilicon 6 simultaneously carries out chemical wet etching formation polysilicon gate 6 to the polysilicon 6,
The grid structure of radio frequency LDMOS device is formed by second gate dielectric layer 5 superposition of the polysilicon gate 6 He its bottom；Institute
The second side for stating polysilicon gate 6 extends to the top of the second gate dielectric layer 5.
Preferably, the thickness of the polysilicon 6 deposited is 2500 angstroms to 3500 angstroms.
Step 5: as shown in Figure 2 D, first time p-type ion implanting formation channel region 7 is carried out, the channel region 7 and described
The first side autoregistration of polysilicon gate 6；Carry out second N-type ion implanting formation drift region 8, the drift region 8 and described
The second side autoregistration of polysilicon gate 6；Carry out source region 9a and the leakage of third time N-type source and drain ion implanting formation N-type heavy doping
Area 9b, the source region 9a are located at the first side autoregistration in the channel region 7 simultaneously with the polysilicon gate 6, the drain region 9b
For the second side autoregistration in the drift region 8 simultaneously with second gate dielectric layer 5；Carry out the 4th p-type ion implanting shape
Into P+ draw-out areas 10, the P+ draw-out areas 10 are located in the channel region 7 and with source region 9a contacts, for by the raceway groove
Area 7 is drawn；The channel region 7, the drift region 8, the source region 9a, the drain region 9b and the P+ are drawn using thermal annealing
Area 10 enters the channel region 7 and the drift region 8 after line activating and propulsion, thermal annealing and extends to the polysilicon from both sides respectively
The bottom of grid 6, the surface of the channel region 7 covered by the polysilicon gate 6 is used to form raceway groove.
Step 6: as shown in Figure 2 E, side wall 11 is formed in the side of the polysilicon gate 6 using deposit and time carving technology.
Preferably, the side wall medium layer deposited when forming the side wall 11 is successively by the silica 11a being superimposed and nitridation
Silicon 11b is constituted.It is 400 angstroms to 600 angstroms to form the thickness of dielectric layers of side wall 11 deposited during the side wall 11.
Returning when forming the side wall 11, which is carved, to be required to be less than 100 angstroms, such energy to the loss amount of first gate dielectric layer 4
Make the loss amount of the first gate dielectric layer 4 relatively low.
Step 7: as shown in Figure 2 F, deposit metal silicide 13 block media layer 12.
Preferably, the material of the block media of metal silicide 13 layer 12 is silica, and thickness is 300 angstroms to 700 angstroms.
Step 8: as shown in Figure 2 G, to the block media of the metal silicide 13 layer in the radio frequency LDMOS device region
12 and second gate dielectric layer 5 carve, the top of polysilicon gate 6 described in Hui Kehou, the first side of the polysilicon gate 6
Silicon outside the outside of side wall 11 and the second side of the first gate dielectric layer 4 exposes, namely returns the thickness carved and be greater than and be equal to
The thickness of the block media of metal silicide 13 layer 12 and second gate dielectric layer 5 and, so just can guarantee that the polycrystalline
Outside the top of Si-gate 6, the outside of side wall 11 of the first side of the polysilicon gate 6 and the second side of the first gate dielectric layer 4
Silicon expose.
The thickness requirement of first gate dielectric layer 4 deposited described in step one ensures to carve and walk by returning for step 6
Rapid eight return still is withed a hook at the end after carving certain thickness and to be covered the drift region 8, so that autoregistration defines metal silicide
13 forming region, the forming region of the metal silicide 13 is the region that silicon exposes；Namely the quarter of returning of step 8 also should not
It is excessive, return first gate dielectric layer 4 after carving and still with a hook at the end and certain thickness and cover the drift region 8.
Step 9: as illustrated in figure 2h, depositing metal, the metal silicide that metal silication is defined in autoregistration is carried out
13 forming region forms the metal silicide 13.The metal preferably deposited is tungsten, titanium, cobalt.
Step 10: as shown in figure 2i, using deposit plus lithographic etch process formation faraday shield layer 15, being covered in described
On ledge structure at the second side of polysilicon gate 6, the polysilicon gate 6 of the faraday shield layer 15 and its bottom it
Between isolation have shielding dielectric layer 14；
Step 11: carrying out deep etching, the deep trouth passes through the source region 9a, the channel region 7 and the epitaxial layer 2
And enter in the silicon substrate 1；Metal is filled in the deep trouth and forms the deep contact hole, the deep contact hole will be described
Source region 9a, the channel region 7, the epitaxial layer 2 and the silicon substrate 1 are electrically connected；
Step 12: forming interlayer film, contact hole and front metal layer pattern.Wherein described contact hole can pass through the layer
Between film and the polysilicon gate 6 of bottom, the source region 9a and the P+ draw-out areas 10 and the drain region 9b contact, it is described to connect
The top of contact hole and front metal layer contact, the front metal layer draw the source electrode of device, drain and gate respectively.
The present invention is described in detail above by specific embodiment, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (13)
1. a kind of manufacture method of radio frequency LDMOS device, it is characterised in that comprise the following steps：
Step 1: in surface of silicon formation epitaxial layer, forming p-well in the epitaxial layer, afterwards the gate dielectric layer of growth regulation one；
Step 2: removing first gate dielectric layer outside the forming region of drift region, the drift using lithographic etch process
First gate dielectric layer of the forming region in area retains；
Step 3: the gate dielectric layer of growth regulation two, the thickness of second gate dielectric layer is less than the thickness of first gate dielectric layer；
Step 4: depositing polysilicon and to the polysilicon carry out chemical wet etching formation polysilicon gate, by the polysilicon gate and its
The second gate dielectric layer of bottom is superimposed the grid structure to form radio frequency LDMOS device；The second side of the polysilicon gate
Extend to above first gate dielectric layer；
Step 5: carrying out the first side of first time p-type ion implanting formation channel region, the channel region and the polysilicon gate
Autoregistration；Carry out second N-type ion implanting formation drift region, the second side of the drift region and the polysilicon gate is from right
It is accurate；Third time N-type source and drain ion implanting formation source region and drain region are carried out, the source region is located in the channel region and and described many
The first side autoregistration of crystal silicon grid, the drain region be the drift region in and and second gate dielectric layer second side from
Alignment；Carry out the 4th p-type ion implanting formation P+ draw-out areas, the P+ draw-out areas be located in the channel region and with the source
Area is contacted, for the channel region to be drawn；Using thermal annealing to the channel region, the drift region, the source region, the leakage
Area and the P+ draw-out areas are entered the channel region and the drift region after line activating and propulsion, thermal annealing and extended to respectively from both sides
The bottom of the polysilicon gate, the channel region surface covered by the polysilicon gate is used to form raceway groove；
Step 6: using deposit and returning side formation side wall of the carving technology in the polysilicon gate；
Step 7: deposit metal silicide block media layer；
Step 8: to the metal silicide block media layer in the radio frequency LDMOS device region and second gate medium
Layer carve, polysilicon gate top, the side wall outside and described first of the polysilicon gate first side described in Hui Kehou
Silicon outside gate dielectric layer second side exposes, and the thickness requirement of first gate dielectric layer deposited in step one ensures to pass through
The returning of step 6 carve and step 8 return carve after still with a hook at the end and certain thickness and cover the drift region so that autoregistration is fixed
Justice goes out the forming region of metal silicide, and the forming region of the metal silicide is the region that silicon exposes；
Step 9: deposit metal, the forming region for carrying out the metal silicide that metal silication is defined in autoregistration is formed
The metal silicide.
2. the manufacture method of radio frequency LDMOS device as claimed in claim 1, it is characterised in that：First gate dielectric layer
Material is oxide layer.
3. the manufacture method of radio frequency LDMOS device as claimed in claim 1 or 2, it is characterised in that：First gate dielectric layer
Thickness meet can be under conditions of autoregistration defines the forming region of the metal silicide, by increasing described first
The thickness of gate dielectric layer reduces the grid of the radio frequency LDMOS device and the coupled capacitor of drain electrode.
4. the manufacture method of radio frequency LDMOS device as claimed in claim 1 or 2, it is characterised in that：First gate dielectric layer
Thickness be 300 angstroms to 800 angstroms.
5. the manufacture method of radio frequency LDMOS device as claimed in claim 1, it is characterised in that：Second gate dielectric layer
Material is oxide layer.
6. the manufacture method of radio frequency LDMOS device as claimed in claim 1, it is characterised in that：The side is formed in step 6
The side wall medium layer thickness deposited during wall is 400 angstroms to 600 angstroms.
7. the manufacture method of radio frequency LDMOS device as claimed in claim 1, it is characterised in that：The side is formed in step 6
The side wall medium layer deposited during wall is made up of the silica and silicon nitride that are superimposed successively.
8. the manufacture method of radio frequency LDMOS device as claimed in claim 1, it is characterised in that：The side is formed in step 6
Returning during wall, which is carved, to be required to be less than 100 angstroms to the loss amount of first gate dielectric layer.
9. the manufacture method of radio frequency LDMOS device as claimed in claim 1, it is characterised in that：The institute deposited in step 7
The material for stating metal silicide block media layer is silica.
10. the manufacture method of the radio frequency LDMOS device as described in claim 1 or 9, it is characterised in that：The metal silicide
The thickness of block media layer is 300 angstroms to 700 angstroms.
11. the manufacture method of radio frequency LDMOS device as claimed in claim 1, it is characterised in that：The institute deposited in step 4
The thickness for stating polysilicon is 2500 angstroms to 3500 angstroms.
12. the manufacture method of radio frequency LDMOS device as claimed in claim 1, it is characterised in that：The metal that step 9 is deposited
For tungsten, titanium, cobalt.
13. the manufacture method of radio frequency LDMOS device as claimed in claim 1, it is characterised in that：Also include such as after step 9
Lower step：
Step 10: forming faraday shield layer, it is covered on the ledge structure at the second side of the polysilicon gate, the method
Isolation between screen layer and the polysilicon gate of its bottom is drawn to have shielding dielectric layer；
Step 11: carrying out deep etching, the deep trouth is through the source region, the channel region and the epitaxial layer and enters
In the silicon substrate；Metal is filled in the deep trouth and forms deep contact hole, the deep contact hole is by the source region, the raceway groove
Area, the epitaxial layer and silicon substrate electrical connection；
Step 12: forming interlayer film, contact hole and front metal layer pattern.
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| CN108010836A (en) * | 2017-12-12 | 2018-05-08 | 江苏博普电子科技有限责任公司 | The forming method of the short grid low square resistance value grid silicides of RF-LDMOS |
| CN110299413A (en) * | 2019-07-11 | 2019-10-01 | 上海华虹宏力半导体制造有限公司 | A kind of LDMOS device and its manufacturing method |
| CN110391293A (en) * | 2019-07-29 | 2019-10-29 | 上海华虹宏力半导体制造有限公司 | LDMOSFET device and its manufacturing method |
| CN111063737A (en) * | 2019-11-25 | 2020-04-24 | 上海华虹宏力半导体制造有限公司 | LDMOS device and technological method |
| CN111092123A (en) * | 2019-12-10 | 2020-05-01 | 杰华特微电子（杭州）有限公司 | Lateral double-diffused transistor and manufacturing method thereof |
| CN112216745B (en) * | 2020-12-10 | 2021-03-09 | 北京芯可鉴科技有限公司 | High-voltage asymmetric LDMOS device and preparation method thereof |
| CN115513060A (en) * | 2022-11-03 | 2022-12-23 | 杭州晶丰明源半导体有限公司 | LDMOS device and manufacturing method thereof |
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