CN105990170B - Analytical method of wafer yield and device - Google Patents
Analytical method of wafer yield and device Download PDFInfo
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- CN105990170B CN105990170B CN201510044709.6A CN201510044709A CN105990170B CN 105990170 B CN105990170 B CN 105990170B CN 201510044709 A CN201510044709 A CN 201510044709A CN 105990170 B CN105990170 B CN 105990170B
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Abstract
The invention discloses a kind of analytical method of wafer yield and devices.Wherein, analytical method of wafer yield includes: that chip to be measured on wafer to be measured is divided into multiple regions, wherein wafer to be measured includes multiple chips to be measured；Obtain the history killing rate according to multiple regions on the chip counted in advance, wherein multiple regions and history killing rate correspond；The history killing rate that will acquire as the corresponding killing rate of multiple regions on chip to be measured, killing rate be used to indicate region corresponding with the rate that kills there are the probability of critical defect；The corresponding critical defect rate of wafer to be measured is calculated according to the corresponding killing rate of multiple regions on chip to be measured；And the yield of wafer to be measured is calculated by critical defect rate.Through the invention, solve the problems, such as that the yield of wafer in the prior art calculates inaccuracy.
Description
Technical field
The present invention relates to semiconductor fields, in particular to a kind of analytical method of wafer yield and device.
Background technique
In the production procedure of semiconductor subassembly, all Alternatives are contained, each technique has pollution wafer
(wafer), the reasons such as crystal column surface are broken, cause wafer yield bad, therefore, carrying out analysis prediction to the yield of wafer seems
It is very necessary.Defect (Defect) killing rate (killer rate) is to indicate wafer there are the probability of fatal killing, and defect kills
Rate is most important for the yield prediction of wafer.
Currently, semiconductor industry is past when calculating wafer defect (Defect) killing rate (killer rate) using system
It is that unit is calculated toward using with chip (Die), gives the killing rate of chip to calculate the killing rate of the chip of wafer to be measured.
However, due to homotype wafer killed in different chips variation it is very big, cause the analysis of yield pre- using such calculation
Surveying result, there are great differences with actual result, the result inaccuracy for causing yield to calculate.
The problem of inaccuracy is calculated for the yield of wafer in the prior art, currently no effective solution has been proposed.
Summary of the invention
The main purpose of the present invention is to provide a kind of analytical method of wafer yield and devices, brilliant in the prior art to solve
Round yield calculates the problem of inaccuracy.
To achieve the goals above, according to an aspect of an embodiment of the present invention, a kind of wafer yield analysis side is provided
Method.Analytical method of wafer yield according to the present invention includes: that chip to be measured on wafer to be measured is divided into multiple regions, wherein
The wafer to be measured includes multiple chips to be measured；Obtain the history killing according to the multiple region on the chip counted in advance
Rate, wherein the multiple region and the history killing rate correspond；The history killing rate that will acquire is as the core to be measured
The corresponding killing rate in the multiple region of on piece, the killing rate are used to indicate that the presence in region corresponding with the killing rate to cause
Order the probability of defect；It is corresponding that the wafer to be measured is calculated according to the corresponding killing rate in region the multiple on the chip to be measured
Critical defect rate；And the yield of the wafer to be measured is calculated by the critical defect rate.
Further, the wafer pair to be measured is calculated according to the corresponding killing rate in region the multiple on the chip to be measured
The critical defect rate answered includes: by judging that it is more than default for whether there is killing rate on the chip to be measured in the multiple region
The region of threshold value judges on the wafer to be measured that multiple chips to be measured whether there is critical defect one by one, wherein if it is determined that
There are the regions that killing rate is more than preset threshold in the multiple region on the chip to be measured out, it is determined that the core to be measured
There are critical defects for piece；If it is judged that there is no killing rates more than preset threshold in the multiple region on the chip to be measured
Region, it is determined that the chip to be measured be not present critical defect；There are the quantity of the chip to be measured of critical defect for record；With
And there are the quantity of the chip to be measured of critical defect to calculate the corresponding critical defect rate of the wafer to be measured by described.
Further, chip to be measured on wafer to be measured is divided into multiple regions includes: to be measured on the wafer to be measured
Chip carries out defects detection, obtains the defective chip of existing defects；And the defective chip is divided into multiple regions.
Further, described after obtaining according to the history killing rate in the multiple region on the chip counted in advance
Analytical method of wafer yield further include: successively judge the difference of the corresponding killing rate in two regions adjacent in the multiple region
Whether difference threshold is less than；If it is determined that the difference of the corresponding killing rate in two regions adjacent in the multiple region is less than institute
Difference threshold is stated, then by two adjacent region merging techniques at a region.
Further, after the yield for calculating the wafer to be measured by the critical defect rate, the wafer yield point
Analysis method further include: obtain the actual defects testing result of the wafer to be measured, the actual defects testing result includes described
The practical killing rate of multiple regions；The practical killing rate in the multiple region and the history killing rate in the multiple region are closed
And the history killing rate after being merged.
To achieve the goals above, according to another aspect of an embodiment of the present invention, a kind of wafer yield analysis dress is provided
It sets.Wafer yield analytical equipment according to the present invention includes: division unit, more for chip to be measured on wafer to be measured to be divided into
A region, wherein the wafer to be measured includes multiple chips to be measured；First acquisition unit, for obtaining according to counting in advance
The history killing rate in the multiple region on chip, wherein the multiple region and the history killing rate correspond；It determines
Unit, the history killing rate for will acquire are described to kill as the corresponding killing rate in region the multiple on the chip to be measured
Hurt rate for indicate region corresponding with the killing rate there are the probability of critical defect；First computing unit is used for basis
The corresponding killing rate in the multiple region calculates the corresponding critical defect rate of the wafer to be measured on the chip to be measured；And the
Two computing units, for calculating the yield of the wafer to be measured by the critical defect rate.
Further, first computing unit includes: judgment module, for described on the chip to be measured by judging
Multiple cores to be measured on the wafer to be measured are judged one by one with the presence or absence of killing rate is more than the region of preset threshold in multiple regions
Piece whether there is critical defect, wherein if it is judged that there are killing rates in the multiple region on the chip to be measured is more than
The region of preset threshold, it is determined that there are critical defects for the chip to be measured；If it is judged that described on the chip to be measured
There is no the regions that killing rate is more than preset threshold in multiple regions, it is determined that critical defect is not present in the chip to be measured；
Logging modle, for recording the quantity of the chip to be measured there are critical defect；And computing module, for there are fatal by described
The quantity of the chip to be measured of defect calculates the corresponding critical defect rate of the wafer to be measured.
Further, the division unit includes: detection module, scarce for carrying out to chip to be measured on the wafer to be measured
Detection is fallen into, the defective chip of existing defects is obtained；And division module, for the defective chip to be divided into multiple regions.
Further, the wafer yield analytical equipment further include: judging unit, for obtaining what basis counted in advance
On chip after the history killing rate in the multiple region, successively judge that two regions adjacent in the multiple region are corresponding
Whether the difference of killing rate is less than difference threshold；First combining unit, for if it is determined that adjacent two in the multiple region
The difference of the corresponding killing rate in a region is less than the difference threshold, then by two adjacent region merging techniques at an area
Domain.
Further, the wafer yield analytical equipment further include: second acquisition unit, for by the critical defect
After rate calculates the yield of the wafer to be measured, the actual defects testing result of the wafer to be measured, the actual defects are obtained
Testing result includes the practical killing rate in the multiple region；Second combining unit, for actually killing the multiple region
Hurt rate to merge with the history killing rate in the multiple region, the history killing rate after being merged.
In the embodiment of the present invention, by the way that chip to be measured on wafer to be measured is divided into multiple regions, obtain according to system in advance
The history killing rate of multiple regions, the history killing rate that will acquire are corresponding as multiple regions on chip to be measured on the chip of meter
Killing rate calculates the corresponding critical defect rate of wafer to be measured according to the corresponding killing rate of multiple regions on chip to be measured, by fatal
Ratio of defects calculates the yield of wafer to be measured, to realize that the analysis to the yield of wafer to be measured is predicted.By thus according to core to be measured
Wafer to be measured is calculated to determine the fatal killing rate of chip to be measured, then by the fatal killing rate in the multiple regions that on piece divides
Yield, relative to for the yield of wafer to be measured is calculated, improving the precision of calculating as unit of chip, solve
The yield of wafer calculates the problem of inaccuracy in the prior art, has achieved the effect that the calculating accuracy for improving wafer yield.
Detailed description of the invention
The attached drawing constituted part of this application is used to provide further understanding of the present invention, schematic reality of the invention
It applies example and its explanation is used to explain the present invention, do not constitute improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is the flow chart of analytical method of wafer yield according to an embodiment of the present invention；And
Fig. 2 is the schematic diagram of wafer yield analytical equipment according to an embodiment of the present invention.
Specific embodiment
It should be noted that in the absence of conflict, the features in the embodiments and the embodiments of the present application can phase
Mutually combination.The present invention will be described in detail below with reference to the accompanying drawings and embodiments.
In order to enable those skilled in the art to better understand the solution of the present invention, below in conjunction in the embodiment of the present invention
Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only
The embodiment of a part of the invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people
The model that the present invention protects all should belong in member's every other embodiment obtained without making creative work
It encloses.
It should be noted that description and claims of this specification and term " first " in above-mentioned attached drawing, "
Two " etc. be to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should be understood that using in this way
Data be interchangeable under appropriate circumstances, so as to the embodiment of the present invention described herein.In addition, term " includes " and " tool
Have " and their any deformation, it is intended that cover it is non-exclusive include, for example, containing a series of steps or units
Process, method, system, product or equipment those of are not necessarily limited to be clearly listed step or unit, but may include without clear
Other step or units listing to Chu or intrinsic for these process, methods, product or equipment.
The embodiment of the invention provides a kind of analytical method of wafer yield.
Fig. 1 is the flow chart of analytical method of wafer yield according to an embodiment of the present invention.As shown in Figure 1, the wafer yield
Analysis method comprises the following steps that
Chip to be measured on wafer to be measured is divided into multiple regions by step S102.Wherein, wafer to be measured includes multiple to be measured
Chip.
There are multiple chip circuits, i.e., chip to be measured, the embodiment of the present invention is according to pre-set on each wafer to be measured
Each chip to be measured is divided into multiple regions by rule, and the size in each of which region, which can according to need, to be configured.Specifically,
Each chip can be divided automatically by designing a set of grid system.
Specifically, chip to be measured is carried out dividing to can be according to quantity or fixed size dividing.User can be with
Rule of thumb or pervious test result sets the region of division, with set important area (can be killing rate compared with
High region) and secondary regions (can be the lower region of killing rate).
Step S104 obtains the history killing rate according to multiple regions on the chip counted in advance.Wherein, multiple regions with
History killing rate corresponds.
Step S106, the history killing rate that will acquire is as the corresponding killing rate of multiple regions on chip to be measured.The killing
Rate be used for indicate region corresponding with the rate that kills there are the probability of critical defect.
History killing rate is the killing rate obtained according to the actually detected result in region each in former chip, wherein every
A region is corresponding with its killing rate, as the killing rate of corresponding region on chip to be measured.
Specifically, phase can be searched from the database for being stored with the history killing rate that statistics obtains according to the region of division
The history killing rate answered.For example, chip to be measured is divided into region A, region B, the region region C ... Z, gone through according to what is got
History killing rate, wherein in history killing rate region A, region B, the region region C ... Z killing rate successively are as follows: a, b,
C ... z, then, successively it regard killing rate a, b, c ... z as the region A of chip to be measured, region B, the region region C ... Z
Killing rate.
Step S108 calculates the corresponding critical defect of wafer to be measured according to the corresponding killing rate of multiple regions on chip to be measured
Rate.
Step S110 is calculated the yield of wafer to be measured by critical defect rate.
After obtaining the corresponding killing rate in each region on chip to be measured, it can be determined according to the killing rate corresponding
Whether chip to be measured has fatal killing, is determined using aforesaid way each chip to be measured, to obtain that there are fatal
The corresponding critical defect of wafer to be measured is calculated with there is no the quantity of the chip to be measured of critical defect in the chip to be measured of defect
Rate, then there is the critical defect rate analytical calculation to obtain the yield of wafer to be measured, to realize the analysis to the yield of wafer to be measured
Prediction.
In the embodiment of the present invention, by the way that chip to be measured on wafer to be measured is divided into multiple regions, obtain according to system in advance
The history killing rate of multiple regions, the history killing rate that will acquire are corresponding as multiple regions on chip to be measured on the chip of meter
Killing rate calculates the corresponding critical defect rate of wafer to be measured according to the corresponding killing rate of multiple regions on chip to be measured, by fatal
Ratio of defects calculates the yield of wafer to be measured, to realize that the analysis to the yield of wafer to be measured is predicted.By thus according to core to be measured
Wafer to be measured is calculated to determine the fatal killing rate of chip to be measured, then by the fatal killing rate in the multiple regions that on piece divides
Yield, relative to for the yield of wafer to be measured is calculated, improving the precision of calculating as unit of chip, solve
The yield of wafer calculates the problem of inaccuracy in the prior art, has achieved the effect that the calculating accuracy for improving wafer yield.
Preferably, the corresponding critical defect rate of wafer to be measured is calculated according to the corresponding killing rate of multiple regions on chip to be measured
Include: by judge on chip to be measured in multiple regions with the presence or absence of killing rate be more than the region of preset threshold judge one by one to
Surveying multiple chips to be measured on wafer whether there is critical defect, wherein if it is judged that existing in multiple regions on chip to be measured
Killing rate is more than the region of preset threshold, it is determined that there are critical defects for the chip to be measured；If it is judged that more on chip to be measured
There is no the regions that killing rate is more than preset threshold in a region, it is determined that critical defect is not present in the chip to be measured；Record is deposited
In the quantity of the chip to be measured of critical defect；And it is corresponded to by calculating wafer to be measured there are the quantity of the chip to be measured of critical defect
Critical defect rate.
There is a killing rate since each region is corresponding, in the embodiment of the present invention, by the way that corresponding threshold value is arranged, this
Threshold value, which can according to need, to be configured, and is compared with the killing rate in each region, determines chip to be measured according to comparison result
In whether there is fatal killing.
Specifically, if there are fatal for the chip to be measured simply by the presence of the region of a fatal killing in chip to be measured
Killing.Judge the region that whether there is fatal killing in each chip to be measured one by one by above-mentioned preset threshold, if it is,
There are the chip to be measured of critical defect, count is incremented.After having traversed each chip to be measured, there are the cores to be measured of critical defect for record
The quantity of piece, the quantity obtain the corresponding critical defect rate of wafer to be measured divided by the quantity of total chip to be measured.
Preferably, by chip to be measured on wafer to be measured be divided into multiple regions include: to chip to be measured on wafer to be measured into
Row defects detection obtains the defective chip of existing defects；And defective chip is divided into multiple regions.
Defect Scanning first is carried out to wafer to be measured, scanning result is obtained, includes the core of existing defects in the scanning result
Piece and chip there is no defect.Since there is no also there is no fatal killings in the chip of defect, and there are fatal killings
Chip is defective chip.The defective chip that defect preferably will be present in the embodiment of the present invention is divided into multiple regions, with
Convenient for only judging the region of existing defects, to improve the calculating speed of fatal killing rate.
Preferably, after obtaining according to the history killing rate of multiple regions on the chip counted in advance, wafer yield point
Analysis method further include: successively judge whether the difference of the corresponding killing rate in two regions adjacent in multiple regions is less than difference threshold
Value；If it is determined that the difference of the corresponding killing rate in two regions adjacent in multiple regions is less than difference threshold, then it will be adjacent
Two region merging techniques are at a region.
After getting the history killing rate of multiple regions, the killing rate in two adjacent regions is judged, is sentenced
Whether the difference for its killing rate of breaking is less than preset threshold (the threshold value very little), that is, judges whether the killing rate in two neighboring region compares
It is closer to, if it is, by two region merging techniques at a region.The multiple regions after division are closed in the manner described above
And handle, to reduce the quantity in region.Since as long as there are the regions that killing rate is more than preset threshold in chip, then it is assumed that core
There are critical defects for piece, and by the close region merging technique of killing rate, the quantity for reducing region, which can be improved, carries out fatal lack to chip
Fall into the speed of judgement.
Preferably, after the yield for calculating wafer to be measured by critical defect rate, analytical method of wafer yield further include: obtain
The actual defects testing result of wafer to be measured is taken, actual defects testing result includes the practical killing rate of multiple regions；It will be multiple
The practical killing rate in region merges with the history killing rate of multiple regions, the history killing rate after being merged.
Yield since wafer to be measured is calculated is the value that participle prediction obtains, and can be used for judging wafer to be measured
Availability.In the embodiment of the present invention, in order to improve wafer yield prediction accuracy, practical inspection is being carried out to the wafer to be measured
After survey, the result that can be will test is placed into there are in the database of killing rate, by the actually detected result of the wafer to be measured
It is re-used as history killing rate.
Optionally, the method for the embodiment of the present invention can realize that the analysis system is by Dice subregion by analysis system
Setting system, subregion killer rate computing system, Yield predict system composition.Specifically, system operational process is such as
Under:
1) it is defined according to defect testing result by engineer when system is run or the division methods of system default is automatically right
Each Dice of testing result carries out subregion.And this defect pairs is calculated according to the killer rate for corresponding to subregion in database
The influence of dice, to predict the yield of defect impact wafer.
2) after new yield feedback, system carries out by station the defect of detection automatically according to the product partitioning scenario
Point, region calculates the killer rate of every layer of defect, and combines historical data, updates into database, in case homotype product
Future anticipation uses.
In the embodiment of the present invention, system automatically can divide wafer according to the defects detection state of production product
Group.And by main system, grouping rear region is analyzed.Its grouping standard can be set automatically by system or be set by engineering staff
Fixed and modification, is grouped using wafer or dice as object.
System can be according to killer rate database, and combines grouped element, carries out different zones defect analysis, mentions
For region impact rate Macro or mass analysis.Network analysis killer rate is mainly by the place defect subregion, classification, size etc.
Defect parameter, limitation can not updated with above defect parameter information data by yield system automatic feedback.
System can count the yield of wafer according to subregion, prompt whether engineer's product needs to scrap.
The embodiment of the invention also provides a kind of wafer yield analytical equipments.The device can be realized by computer equipment
Its function.It should be noted that the wafer yield analytical equipment of the embodiment of the present invention can be used for executing institute of the embodiment of the present invention
The analytical method of wafer yield of offer, the analytical method of wafer yield of the embodiment of the present invention can also institutes through the embodiment of the present invention
The wafer yield analytical equipment of offer executes.
Fig. 2 is the schematic diagram of wafer yield analytical equipment according to an embodiment of the present invention.As shown in Fig. 2, the wafer yield
Analytical equipment includes: that division unit 10, first acquisition unit 20, determination unit 30, the first computing unit 40 and the second calculating are single
Member 50.
Division unit 10 is used to chip to be measured on wafer to be measured being divided into multiple regions, wherein wafer to be measured includes more
A chip to be measured.
There are multiple chip circuits, i.e., chip to be measured, the embodiment of the present invention is according to pre-set on each wafer to be measured
Each chip to be measured is divided into multiple regions by rule, and the size in each of which region, which can according to need, to be configured.Specifically,
Each chip can be divided automatically by designing a set of grid system.
Specifically, chip to be measured is carried out dividing to can be according to quantity or fixed size dividing.User can be with
Rule of thumb or pervious test result sets the region of division, with set important area (can be killing rate compared with
High region) and secondary regions (can be the lower region of killing rate).
First acquisition unit 20 is used to obtain the history killing rate according to multiple regions on the chip counted in advance, wherein
Multiple regions and history killing rate correspond.
The history killing rate that determination unit 30 is used to will acquire is killed as the corresponding killing rate of multiple regions on chip to be measured
Hurt rate for indicate region corresponding with the rate that kills there are the probability of critical defect.
History killing rate is the killing rate obtained according to the actually detected result in region each in former chip, wherein every
A region is corresponding with its killing rate, as the killing rate of corresponding region on chip to be measured.
Specifically, phase can be searched from the database for being stored with the history killing rate that statistics obtains according to the region of division
The history killing rate answered.For example, chip to be measured is divided into region A, region B, the region region C ... Z, gone through according to what is got
History killing rate, wherein in history killing rate region A, region B, the region region C ... Z killing rate successively are as follows: a, b,
C ... z, then, successively it regard killing rate a, b, c ... z as the region A of chip to be measured, region B, the region region C ... Z
Killing rate.
First computing unit 40 is used to calculate wafer to be measured according to the corresponding killing rate of multiple regions on chip to be measured corresponding
Critical defect rate.
Second computing unit 50 is used to be calculated the yield of wafer to be measured by critical defect rate.
After obtaining the corresponding killing rate in each region on chip to be measured, it can be determined according to the killing rate corresponding
Whether chip to be measured has fatal killing, is determined using aforesaid way each chip to be measured, to obtain that there are fatal
The corresponding critical defect of wafer to be measured is calculated with there is no the quantity of the chip to be measured of critical defect in the chip to be measured of defect
Rate, then there is the critical defect rate analytical calculation to obtain the yield of wafer to be measured, to realize the analysis to the yield of wafer to be measured
Prediction.
In the embodiment of the present invention, by the way that chip to be measured on wafer to be measured is divided into multiple regions, obtain according to system in advance
The history killing rate of multiple regions, the history killing rate that will acquire are corresponding as multiple regions on chip to be measured on the chip of meter
Killing rate calculates the corresponding critical defect rate of wafer to be measured according to the corresponding killing rate of multiple regions on chip to be measured, by fatal
Ratio of defects calculates the yield of wafer to be measured, to realize that the analysis to the yield of wafer to be measured is predicted.By thus according to core to be measured
Wafer to be measured is calculated to determine the fatal killing rate of chip to be measured, then by the fatal killing rate in the multiple regions that on piece divides
Yield, relative to for the yield of wafer to be measured is calculated, improving the precision of calculating as unit of chip, solve
The yield of wafer calculates the problem of inaccuracy in the prior art, has achieved the effect that the calculating accuracy for improving wafer yield.
Preferably, the first computing unit includes: judgment module, for by judge on chip to be measured in multiple regions whether
Judge that multiple chips to be measured whether there is critical defect on wafer to be measured one by one there are killing rate is more than the region of preset threshold,
Wherein, if it is judged that there are the regions that killing rate is more than preset threshold in multiple regions on chip to be measured, it is determined that this is to be measured
There are critical defects for chip；If it is judged that there is no the areas that killing rate is more than preset threshold in multiple regions on chip to be measured
Domain, it is determined that critical defect is not present in the chip to be measured；Logging modle, for recording the number of the chip to be measured there are critical defect
Amount；And computing module, for by there are the quantity of the chip to be measured of critical defect to calculate the corresponding critical defect of wafer to be measured
Rate.
There is a killing rate since each region is corresponding, in the embodiment of the present invention, by the way that corresponding threshold value is arranged, this
Threshold value, which can according to need, to be configured, and is compared with the killing rate in each region, determines chip to be measured according to comparison result
In whether there is fatal killing.
Specifically, if there are fatal for the chip to be measured simply by the presence of the region of a fatal killing in chip to be measured
Killing.Judge the region that whether there is fatal killing in each chip to be measured one by one by above-mentioned preset threshold, if it is,
There are the chip to be measured of critical defect, count is incremented.After having traversed each chip to be measured, there are the cores to be measured of critical defect for record
The quantity of piece, the quantity obtain the corresponding critical defect rate of wafer to be measured divided by the quantity of total chip to be measured.
Preferably, division unit includes: detection module, for carrying out defects detection to chip to be measured on wafer to be measured, is obtained
To the defective chip of existing defects；And division module, for defective chip to be divided into multiple regions.
Defect Scanning first is carried out to wafer to be measured, scanning result is obtained, includes the core of existing defects in the scanning result
Piece and chip there is no defect.Since there is no also there is no fatal killings in the chip of defect, and there are fatal killings
Chip is defective chip.The defective chip that defect preferably will be present in the embodiment of the present invention is divided into multiple regions, with
Convenient for only judging the region of existing defects, to improve the calculating speed of fatal killing rate.
Preferably, wafer yield analytical equipment further include: judging unit, for obtaining according to the chip counted in advance
After the history killing rate of multiple regions, successively judge that the difference of the corresponding killing rate in two regions adjacent in multiple regions is
It is no to be less than difference threshold；First combining unit, for if it is determined that the corresponding killing rate in two regions adjacent in multiple regions
Difference be less than difference threshold, then by two adjacent region merging techniques at a region.
After getting the history killing rate of multiple regions, the killing rate in two adjacent regions is judged, is sentenced
Whether the difference for its killing rate of breaking is less than preset threshold (the threshold value very little), that is, judges whether the killing rate in two neighboring region compares
It is closer to, if it is, by two region merging techniques at a region.The multiple regions after division are closed in the manner described above
And handle, to reduce the quantity in region.Since as long as there are the regions that killing rate is more than preset threshold in chip, then it is assumed that core
There are critical defects for piece, and by the close region merging technique of killing rate, the quantity for reducing region, which can be improved, carries out fatal lack to chip
Fall into the speed of judgement.
Preferably, wafer yield analytical equipment further include: second acquisition unit, for be measured by the calculating of critical defect rate
After the yield of wafer, the actual defects testing result of wafer to be measured is obtained, actual defects testing result includes multiple regions
Practical killing rate；Second combining unit, for the practical killing rate of multiple regions to be merged with the history killing rate of multiple regions,
History killing rate after being merged.
Yield since wafer to be measured is calculated is the value that participle prediction obtains, and can be used for judging wafer to be measured
Availability.In the embodiment of the present invention, in order to improve wafer yield prediction accuracy, practical inspection is being carried out to the wafer to be measured
After survey, the result that can be will test is placed into there are in the database of killing rate, by the actually detected result of the wafer to be measured
It is re-used as history killing rate.
It should be noted that for the various method embodiments described above, for simple description, therefore, it is stated as a series of
Combination of actions, but those skilled in the art should understand that, the present invention is not limited by the sequence of acts described because
According to the present invention, some steps may be performed in other sequences or simultaneously.Secondly, those skilled in the art should also know
It knows, the embodiments described in the specification are all preferred embodiments, and related actions and modules is not necessarily of the invention
It is necessary.
In the above-described embodiments, it all emphasizes particularly on different fields to the description of each embodiment, there is no the portion being described in detail in some embodiment
Point, reference can be made to the related descriptions of other embodiments.
In several embodiments provided herein, it should be understood that disclosed device, it can be by another way
It realizes.For example, the apparatus embodiments described above are merely exemplary, such as the division of the unit, it is only a kind of
Logical function partition, there may be another division manner in actual implementation, such as multiple units or components can combine or can
To be integrated into another system, or some features can be ignored or not executed.Another point, shown or discussed is mutual
Coupling, direct-coupling or communication connection can be through some interfaces, the indirect coupling or communication connection of device or unit,
It can be electrical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.Above-mentioned integrated list
Member both can take the form of hardware realization, can also realize in the form of software functional units.
If the integrated unit is realized in the form of SFU software functional unit and sells or use as independent product
When, it can store in a computer readable storage medium.Based on this understanding, technical solution of the present invention is substantially
The all or part of the part that contributes to existing technology or the technical solution can be in the form of software products in other words
It embodies, which is stored in a storage medium, including some instructions are used so that a computer
Equipment (can be personal computer, mobile terminal, server or network equipment etc.) executes side described in each embodiment of the present invention
The all or part of the steps of method.And storage medium above-mentioned include: USB flash disk, read-only memory (ROM, Read-Only Memory),
Random access memory (RAM, Random Access Memory), mobile hard disk, magnetic or disk etc. are various to be can store
The medium of program code.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (8)
1. a kind of analytical method of wafer yield characterized by comprising
Chip to be measured on wafer to be measured is divided into multiple regions, wherein the wafer to be measured includes multiple chips to be measured；
Obtain the history killing rate according to the multiple region on the chip to be measured that counts in advance, wherein the multiple region with
The history killing rate corresponds；
The history killing rate that will acquire is used as the corresponding killing rate in region the multiple on the chip to be measured, the killing rate
In indicate corresponding with killing rate region there are the probability of critical defect；
The corresponding critical defect of the wafer to be measured is calculated according to the corresponding killing rate in region the multiple on the chip to be measured
Rate；And
The yield of the wafer to be measured is calculated by the critical defect rate；
The corresponding critical defect of the wafer to be measured is calculated according to the corresponding killing rate in region the multiple on the chip to be measured
Rate includes:
By judge on the chip to be measured in the multiple region with the presence or absence of killing rate be more than the region of preset threshold come by
Multiple chips to be measured whether there is critical defect on a judgement wafer to be measured, wherein if it is judged that the chip to be measured
There are the regions that killing rate is more than preset threshold in upper the multiple region, it is determined that the chip to be measured is lacked there are fatal
It falls into；If it is judged that there is no the regions that killing rate is more than preset threshold in the multiple region on the chip to be measured, then really
Critical defect is not present in the fixed chip to be measured；
There are the quantity of the chip to be measured of critical defect for record；And
There are the quantity of the chip to be measured of critical defect to calculate the corresponding critical defect rate of the wafer to be measured by described.
2. analytical method of wafer yield according to claim 1, which is characterized in that divide chip to be measured on wafer to be measured
Include: for multiple regions
Defects detection is carried out to chip to be measured on the wafer to be measured, obtains the defective chip of existing defects；And
The defective chip is divided into multiple regions.
3. analytical method of wafer yield according to claim 2, which is characterized in that count to be measured in advance obtaining basis
On chip after the history killing rate in the multiple region, the analytical method of wafer yield further include:
Successively judge whether the difference of the corresponding killing rate in two regions adjacent in the multiple region is less than difference threshold；
If it is determined that the difference of the corresponding killing rate in two regions adjacent in the multiple region is less than the difference threshold, then
By two adjacent region merging techniques at a region.
4. analytical method of wafer yield according to claim 1, which is characterized in that calculating institute by the critical defect rate
After the yield for stating wafer to be measured, the analytical method of wafer yield further include:
The actual defects testing result of the wafer to be measured is obtained, the actual defects testing result includes the multiple region
Practical killing rate；
The practical killing rate in the multiple region is merged with the history killing rate in the multiple region, the history after being merged
Killing rate.
5. a kind of wafer yield analytical equipment characterized by comprising
Division unit, for chip to be measured on wafer to be measured to be divided into multiple regions, wherein the wafer to be measured includes multiple
Chip to be measured；
First acquisition unit, for obtaining the history killing rate according to the multiple region on the chip to be measured counted in advance,
In, the multiple region and the history killing rate correspond；
Determination unit, the history killing rate for will acquire is as the corresponding killing in region the multiple on the chip to be measured
Rate, the killing rate be used for indicate region corresponding with the killing rate there are the probability of critical defect；
First computing unit, for calculating the crystalline substance to be measured according to the corresponding killing rate in region the multiple on the chip to be measured
The corresponding critical defect rate of circle；And
Second computing unit, for calculating the yield of the wafer to be measured by the critical defect rate；
First computing unit includes:
Judgment module, for by judging that whether there is killing rate on the chip to be measured in the multiple region is more than default threshold
The region of value judges on the wafer to be measured that multiple chips to be measured whether there is critical defect one by one, wherein if it is judged that
There are the regions that killing rate is more than preset threshold in the multiple region on the chip to be measured, it is determined that the chip to be measured
There are critical defects；If it is judged that there is no killing rates more than preset threshold in the multiple region on the chip to be measured
Region, it is determined that critical defect is not present in the chip to be measured；
Logging modle, for recording the quantity of the chip to be measured there are critical defect；And
Computing module, for calculate the wafer to be measured corresponding fatal there are the quantity of the chip to be measured of critical defect by described
Ratio of defects.
6. wafer yield analytical equipment according to claim 5, which is characterized in that the division unit includes:
Detection module obtains the defective chip of existing defects for carrying out defects detection to chip to be measured on the wafer to be measured；
And
Division module, for the defective chip to be divided into multiple regions.
7. wafer yield analytical equipment according to claim 6, which is characterized in that the wafer yield analytical equipment also wraps
It includes:
Judging unit, after the history killing rate in the multiple region on obtaining the chip to be measured that basis counts in advance,
Successively judge whether the difference of the corresponding killing rate in two regions adjacent in the multiple region is less than difference threshold；
First combining unit, for if it is determined that the difference of the corresponding killing rate in two regions adjacent in the multiple region is small
In the difference threshold, then by two adjacent region merging techniques at a region.
8. wafer yield analytical equipment according to claim 5, which is characterized in that the wafer yield analytical equipment also wraps
It includes:
Second acquisition unit, for after the yield for calculating the wafer to be measured by the critical defect rate, obtain it is described to
The actual defects testing result of wafer is surveyed, the actual defects testing result includes the practical killing rate in the multiple region；
Second combining unit, for closing the history killing rate of the practical killing rate in the multiple region and the multiple region
And the history killing rate after being merged.
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| CN110969175B (en) * | 2018-09-29 | 2022-04-12 | 长鑫存储技术有限公司 | Wafer processing method and device, storage medium and electronic equipment |
| CN109741779B (en) * | 2018-12-29 | 2020-10-16 | 西安紫光国芯半导体有限公司 | Method for dynamically adjusting test conditions in wafer test process |
| CN110456003A (en) * | 2019-08-23 | 2019-11-15 | 武汉新芯集成电路制造有限公司 | Wafer defect analysis method and system, analytical method of wafer yield and system |
| CN114068341B (en) * | 2020-08-06 | 2024-06-28 | 长鑫存储技术有限公司 | Test method and test system |
| CN112527586A (en) * | 2020-11-03 | 2021-03-19 | 特劢丝软件科技(上海)有限公司 | Silicon wafer production control method, electronic device, and computer-readable storage medium |
| CN112599434B (en) * | 2020-11-24 | 2023-12-22 | 全芯智造技术有限公司 | Chip product yield prediction method, storage medium and terminal |
| CN112200806A (en) * | 2020-12-03 | 2021-01-08 | 晶芯成(北京)科技有限公司 | Wafer defect analysis method and system |
| CN112990479B (en) * | 2021-02-26 | 2022-02-11 | 普赛微科技(杭州)有限公司 | Method for improving semiconductor chip yield by using machine learning classifier |
| CN116682743B (en) * | 2023-05-15 | 2024-01-23 | 珠海妙存科技有限公司 | Memory chip packaging method, memory chip and integrated circuit system |
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| CN103367188A (en) * | 2012-03-28 | 2013-10-23 | 无锡华润上华科技有限公司 | Wafer yield analysis method and system thereof |
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