CN105955385B - High pressure resistant linear voltage regulator based on standard CMOS process - Google Patents
High pressure resistant linear voltage regulator based on standard CMOS process Download PDFInfo
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- CN105955385B CN105955385B CN201610293842.XA CN201610293842A CN105955385B CN 105955385 B CN105955385 B CN 105955385B CN 201610293842 A CN201610293842 A CN 201610293842A CN 105955385 B CN105955385 B CN 105955385B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
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Abstract
The invention discloses a kind of pressure-resistant linear voltage regulator based on standard CMOS process, applied in power-supply system.The present invention includes：Pre-regulator, according to input voltage, produces burning voltage, is that band gap amplifier is powered；Band gap amplifier, according to feedback signal, output drive signal；Driver, when receiving drive signal, according to input voltage, produces output voltage；Feedback unit, according to output voltage, output feedback signal；Driver includes the PMOS transistor in N number of standard CMOS process；N number of PMOS transistor is sequentially connected in series, band gap amplifier is driven control to the grid voltage of each PMOS transistor, input voltage is uniformly distributed in the source and drain two ends of N number of PMOS transistor, the voltage undertaken needed for each PMOS transistor is unlikely to allow it to damage, and N is the positive integer more than 1.The present invention realizes the function of the special linear voltage stabilizing chips such as 7805 on standard CMOS, reduces complete machine cost.
Description
Technical field
The present invention relates to being related to a kind of linear voltage regulator, more particularly to it is a kind of high pressure resistant linear based on standard CMOS process
Voltage-stablizer.
Background technology
Linear voltage regulator is often used in a chip design, relatively low for an input D/C voltage to be converted into another
Output dc voltage, such as 5V is converted into 1.8V, to be powered to multi-power system, such as Fig. 1.Realized on standard CMOS process
Conventional linear voltage-stablizer, limited by device is pressure-resistant, 5V control sources can only be born.
Power-supply system is 9V or 12V in many applications, it is impossible to which the main control chip such as MCU manufactured directly to CMOS technology is supplied
Electricity is so increased by the cost of complete machine, it is necessary to an extra voltage stabilizing chip (such as 7805) reduces the voltage to 5V, such as Fig. 2.
The content of the invention
In view of the above-mentioned problems, now provide it is a kind of be intended to it is cost-effective high pressure resistant linear steady based on standard CMOS process
Depressor.
A kind of high pressure resistant linear voltage regulator based on standard CMOS process, including：
Pre-regulator, according to input voltage, produces burning voltage, is that band gap amplifier is powered；
Band gap amplifier, according to feedback signal, output drive signal；
Driver, when receiving the drive signal, according to input voltage, produces output voltage；
Feedback unit, according to the output voltage, exports the feedback signal；
The driver includes the PMOS transistor in N number of standard CMOS process；
N number of PMOS transistor is sequentially connected in series, and band gap amplifier drives to the grid voltage of each PMOS transistor
Dynamic control, input voltage is uniformly distributed in what is undertaken needed for the source and drain two ends of N number of PMOS transistor, each PMOS transistor
Voltage is unlikely to allow it to damage, and N is the positive integer more than 1.
It is preferred that, the linear voltage regulator also includes gate bias circuit；
The gate bias circuit, according to the drive signal of band gap amplifier, the grid for N number of PMOS transistor is provided partially
Put voltage.
It is preferred that, the gate bias circuit includes PMOS transistor MP0, N-1 voltage-stabiliser tube, current source I1 and N number of
Nmos pass transistor；
First PMOS transistor in the N number of PMOS transistor being connected in series constitutes current mirror with PMOS transistor MP0
As biasing；Connected respectively a voltage-stabiliser tube between the grid for two PMOS transistors being connected in N number of PMOS transistor；Current source
I1 provides bias current for N-1 voltage-stabiliser tube；
N number of nmos pass transistor is sequentially connected in series, wherein the drain electrode of first nmos pass transistor and first PMOS
The drain electrode of transistor and its grid are connected simultaneously；
The drive signal of band gap amplifier is inputted to the n-th of N number of nmos pass transistor of series connection
The grid of nmos pass transistor.
It is preferred that, the nmos pass transistor increases by one layer of DNW, compatibility standard CMOS technology.
It is preferred that, the pre-regulator includes N number of resistance and N voltage-stabiliser tubes；
N number of resistance is sequentially connected in series, and first resistance is additionally operable to access input voltage, and n-th resistance is additionally operable to and N
The negative electrode connection of voltage-stabiliser tube, the plus earth of N voltage-stabiliser tubes.
It is preferred that, the gate bias voltage of preceding N-1 nmos pass transistor is respectively from pre- steady in N number of nmos pass transistor of series connection
Obtained in N number of resistance of depressor in N-1 tap.
It is preferred that, the input voltage is 15V, and the output voltage that the driver is produced is 5V, 3.3V or 2.5V.
It is preferred that, the MOS transistor that the voltage-stabiliser tube is connected with diode is realized.
The beneficial effect of above-mentioned technical proposal：
The present invention realizes the function of the special linear voltage stabilizing chips such as 7805 on standard CMOS, so as to be integrated into
In the chip of the low pressure process such as MCU design.So such chip just can directly receive the high input voltages such as 12V/9V/15V, then
Reduce complete machine cost.
Brief description of the drawings
Fig. 1 is the electrical connection schematic diagram of traditional linear voltage regulator.
Fig. 2 is the principle schematic of traditional power-supply system.
Fig. 3 be embodiment in the high pressure resistant linear voltage regulator based on standard CMOS process principle schematic.
Fig. 4 is the principle schematic of gate bias circuit in embodiment.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art obtained on the premise of creative work is not made it is all its
His embodiment, belongs to the scope of protection of the invention.
It should be noted that in the case where not conflicting, the embodiment in the present invention and the feature in embodiment can phases
Mutually combination.
The invention will be further described with specific embodiment below in conjunction with the accompanying drawings, but not as limiting to the invention.
As shown in figure 3, the high pressure resistant linear voltage regulator based on standard CMOS process, including：
Pre-regulator, according to input voltage VIN, low precision, a burning voltage preg for weak driving force are produced, is band
Gap amplifier is powered；V in present embodimentIN=15V；
Band gap amplifier, according to feedback signal VFB, output drive signal；
Driver, when receiving drive signal, according to input voltage, produces output voltage VOUT；
Feedback unit, according to output voltage VOUT, output feedback signal VFB；
Further, driver includes three PMOS transistors：PMOS transistor MP1, PMOS transistor MP2 and PMOS are brilliant
Body pipe MP3；
PMOS transistor in present embodiment is the PMOS transistor in standard 5V CMOS technologies, and is four-terminal device,
Voltage between any two ends utilizes this characteristic, PMOS transistor MP1, PMOS transistor MP2 and PMOS no more than 5.5V
Transistor MP3 is sequentially connected in series, and band gap amplifier is driven control to the grid voltage of each PMOS transistor, will be inputted
Voltage is uniformly distributed in the voltage undertaken needed for the source and drain two ends of three PMOS transistors, each PMOS transistor and is unlikely to allow
It is damaged.
In theory, more PMOS transistor series connection can just bear higher input voltage, and finally that limited is PMOS
The substrate of transistor, i.e. NWELL are pressure-resistant to silicon substrate back biased diode.
In order to allow PMOS transistor MP1, PMOS transistor MP2 and PMOS transistor MP3 uniformly to share high input voltage, they
The biasing of grid be crucial.
Further, in present embodiment, linear voltage regulator also includes gate bias circuit；
Such as Fig. 4, gate bias circuit includes PMOS transistor MP0, voltage-stabiliser tube D1, voltage-stabiliser tube D2, current source I1, NMOS crystalline substance
Body pipe MN1, nmos pass transistor MN2 and nmos pass transistor MN3；
PMOS transistor MP1 and PMOS transistor MP0 constitutes current mirror biasing, it is ensured that PMOS transistor MP1 grid source
Voltage can't see high pressure；PMOS transistor MP0 drain electrode and nmos pass transistor MN1 drain electrode, voltage-stabiliser tube D1 negative electrode, PMOS are brilliant
Body pipe MP1 grid is connected simultaneously with PMOS transistor MP0 grid；
Voltage-stabiliser tube D1 anode is connected simultaneously with voltage-stabiliser tube D2 negative electrode and PMOS transistor MP2 grid；Voltage-stabiliser tube D1
Then biasing is provided for PMOS transistor MP2, it is ensured that PMOS transistor MP1 source and drain and PMOS transistor MP2 grid source be can't see
High pressure；
Voltage-stabiliser tube D2 anode is connected simultaneously with current source I1 current input terminal and PMOS transistor MP3 grid, surely
Pressure pipe D2 then provides biasing for PMOS transistor MP3, it is ensured that PMOS transistor MP2 source and drain and PMOS transistor MP3 grid source
It can't see high pressure；Current source I1 current output terminal ground connection；Current source I1 is bias current, for setting voltage-stabiliser tube D1 and voltage stabilizing
Pipe D2 voltage of voltage regulation is near 5V.
Nmos pass transistor MN1, nmos pass transistor MN2 and nmos pass transistor MN3 are sequentially connected in series, and flow through PMOS transistor
MP0 electric current controls nmos pass transistor MN3 to adjust by band gap amplifier, to complete closed-loop control.
Equally, in order to avoid nmos pass transistor MN3 sees high pressure, nmos pass transistor MN1 and nmos pass transistor are series at
Uniformly high pressure is shared above nmos pass transistor MN3.Similarly, nmos pass transistor is also four-terminal device, and the voltage at any two ends is not
Preferably more than 5.5V.For this must allow NMOS from silicon substrate it is independent, this need additionally increase by one layer of DNW (Deep N
Well), compatibility standard CMOS technology.
Further, as shown in figure 4, pre-regulator includes resistance R1, resistance R2, resistance R3 and voltage-stabiliser tube D3；
Resistance R1 one end is used to connect input voltage, and the resistance R1 other end is connected with resistance R2 one end, resistance R2
The other end be connected with resistance R3 one end, the resistance R3 other end is connected with voltage-stabiliser tube D3 negative electrode, voltage-stabiliser tube D3 anode
Ground connection.
Voltage-stabiliser tube D1, voltage-stabiliser tube D2 and voltage-stabiliser tube D3 in present embodiment also can use the MOS transistor that diode is connected
Realize.
Nmos pass transistor MN1 and nmos pass transistor MN2 grid voltage biasing are obtained from the resistor tap of pre-regulator,
Without extra circuits, the position of reasonable selection tap is that can be achieved
Nmos pass transistor MN1, nmos pass transistor MN2 and nmos pass transistor MN3 uniformly share the purpose of high pressure.
Present embodiment realizes 15V high input voltages using the 5V devices design in standard CMOS chip design technology, should
Linear voltage regulator can be converted to high input voltage the stable adjustable outputs of low pressure 5V/3.3V/2.5V.
Preferred embodiments of the present invention are the foregoing is only, embodiments of the present invention and protection model is not thereby limited
Enclose, to those skilled in the art, should can appreciate that made by all utilization description of the invention and diagramatic content
Scheme obtained by equivalent substitution and obvious change, should be included in protection scope of the present invention.
Claims (6)
1. a kind of high pressure resistant linear voltage regulator based on standard CMOS process, including：
Pre-regulator, according to input voltage, produces burning voltage, is that band gap amplifier is powered；
Band gap amplifier, according to feedback signal, output drive signal；
Driver, when receiving the drive signal, according to input voltage, produces output voltage；
Feedback unit, according to the output voltage, exports the feedback signal；
The driver includes the PMOS transistor in N number of standard CMOS process；
N number of PMOS transistor is sequentially connected in series, and band gap amplifier is driven control to the grid voltage of each PMOS transistor
System, input voltage is uniformly distributed in the voltage undertaken needed for the source and drain two ends of N number of PMOS transistor, each PMOS transistor
It is unlikely to allow it to damage, N is the positive integer more than 1；
The linear voltage regulator also includes gate bias circuit；
The gate bias circuit, according to the drive signal of band gap amplifier, the grid for N number of PMOS transistor provides biased electrical
Pressure；
Characterized in that, the gate bias circuit includes PMOS transistor MP0, N-1 voltage-stabiliser tube, current source I1 and N number of
Nmos pass transistor；
First PMOS transistor and PMOS transistor MP0 composition current mirrors in the N number of PMOS transistor being connected in series is inclined
Put；Connected respectively a voltage-stabiliser tube between the grid for two PMOS transistors being connected in N number of PMOS transistor, N-1 steady
The anode of pressure pipe is connected with the grid of n-th PMOS transistor, the negative electrode and the N-1 PMOS transistor of the N-1 voltage-stabiliser tube
Grid connection；Current source I1 provides bias current for N-1 voltage-stabiliser tube；
N number of nmos pass transistor is sequentially connected in series, wherein the drain electrode of first nmos pass transistor and first PMOS crystal
The drain electrode of pipe and its grid are connected simultaneously；
The drive signal of band gap amplifier inputs the grid of the n-th nmos pass transistor to N number of nmos pass transistor of series connection.
2. the high pressure resistant linear voltage regulator as claimed in claim 1 based on standard CMOS process, it is characterised in that the NMOS
Transistor increases by one layer of DNW, compatibility standard CMOS technology.
3. the high pressure resistant linear voltage regulator as claimed in claim 1 or 2 based on standard CMOS process, it is characterised in that described
Pre-regulator includes N number of resistance and N voltage-stabiliser tubes；
N number of resistance is sequentially connected in series, and first resistance is additionally operable to access input voltage, and n-th resistance is additionally operable to and N voltage stabilizings
The negative electrode connection of pipe, the plus earth of N voltage-stabiliser tubes.
4. the high pressure resistant linear voltage regulator as claimed in claim 3 based on standard CMOS process, it is characterised in that the N of series connection
The N-1 from N number of resistance of pre-regulator is individual respectively takes out for the gate bias voltage of N-1 nmos pass transistor before in individual nmos pass transistor
Obtained on head.
5. the high pressure resistant linear voltage regulator as claimed in claim 4 based on standard CMOS process, it is characterised in that the input
Voltage is 15V, and the output voltage that the driver is produced is 5V, 3.3V or 2.5V.
6. the high pressure resistant linear voltage regulator as claimed in claim 3 based on standard CMOS process, it is characterised in that the voltage stabilizing
The MOS transistor of Guan Junyong diodes connection is realized.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610293842.XA CN105955385B (en) | 2016-05-05 | 2016-05-05 | High pressure resistant linear voltage regulator based on standard CMOS process |
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| CN201610293842.XA CN105955385B (en) | 2016-05-05 | 2016-05-05 | High pressure resistant linear voltage regulator based on standard CMOS process |
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| CN105955385B true CN105955385B (en) | 2017-07-28 |
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| CN104821816B (en) * | 2015-05-21 | 2018-02-13 | 苏州锴威特半导体有限公司 | A kind of level displacement circuit being used in half-bridge driven |
| CN109814648B (en) * | 2018-12-27 | 2020-12-04 | 西安紫光国芯半导体有限公司 | Linear voltage stabilizer suitable for high-voltage environment and linear voltage stabilizing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103516350A (en) * | 2012-06-27 | 2014-01-15 | 三星电子株式会社 | Output driver and data output driving circuit using the same |
| CN104881070A (en) * | 2014-02-27 | 2015-09-02 | 无锡华润上华半导体有限公司 | Ultra-low power consumption LDO circuit applied to MEMS |
| CN205608579U (en) * | 2016-05-05 | 2016-09-28 | 上海铄梵电子科技有限公司 | High pressure resistant linear voltage regulator based on standard CMOS technology |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1669831A1 (en) * | 2004-12-03 | 2006-06-14 | Dialog Semiconductor GmbH | Voltage regulator output stage with low voltage MOS devices |
| US8289054B2 (en) * | 2009-08-26 | 2012-10-16 | Alfred E. Mann Foundation For Scientific Research | High voltage differential pair and op amp in low voltage process |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103516350A (en) * | 2012-06-27 | 2014-01-15 | 三星电子株式会社 | Output driver and data output driving circuit using the same |
| CN104881070A (en) * | 2014-02-27 | 2015-09-02 | 无锡华润上华半导体有限公司 | Ultra-low power consumption LDO circuit applied to MEMS |
| CN205608579U (en) * | 2016-05-05 | 2016-09-28 | 上海铄梵电子科技有限公司 | High pressure resistant linear voltage regulator based on standard CMOS technology |
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Effective date of registration: 20210402 Address after: 201600 room 404, room 1, No.10 Shanxi Road, Xiaokunshan Town, Songjiang District, Shanghai Patentee after: SHANGHAI HOLYCHIP ELECTRONIC Co.,Ltd. Address before: 201611 room 2404, room 1, No.10 Shanxi Road, Xiaokunshan Town, Songjiang District, Shanghai Patentee before: SHANGHAI SOVAN ELECTRONIC TECHNOLOGY Co.,Ltd. |