CN105931611B - A kind of array base palte horizontal drive circuit - Google Patents
A kind of array base palte horizontal drive circuit Download PDFInfo
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- CN105931611B CN105931611B CN201610539964.2A CN201610539964A CN105931611B CN 105931611 B CN105931611 B CN 105931611B CN 201610539964 A CN201610539964 A CN 201610539964A CN 105931611 B CN105931611 B CN 105931611B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Liquid Crystal Display Device Control (AREA)
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Abstract
The present invention provides a kind of array base palte horizontal drive circuit, includes multiple gate driver on array unit of cascade, and n-th grade of gate driver on array unit includes：Pull-up circuit, pull-down circuit, drop-down holding circuit, condenser network and output circuit；The condenser network is connected with the drop-down holding circuit in signal point and the n-th 1 grades of gate driver on array unit respectively, and the current potential of the signal point is controlled for the potential change of the drop-down holding circuit in the n-th 1 grades of gate driver on array unit.The array base palte horizontal drive circuit of the present invention on the premise of not increasing number of devices and not changing the potential waveform of signal point, can reduce the time delay of horizontal scanning line signal, greatly improve the display quality of liquid crystal display.
Description
Technical field
The present invention relates to technical field of liquid crystal display, more particularly to a kind of array base palte horizontal drive circuit.
Background technology
GOA (Gate-driver On Array) technology, i.e. array base palte row actuation techniques, because it can save Gate
IC cost, reduce panel border width etc. and be widely used in display panel.Existing array base palte row driving electricity
Road is formed by cascading n gate driver on array unit, and an electric capacity is designed with each gate driver on array unit,
One end of the electric capacity is connected on signal point, and the other end is connected to the level corresponding with the gate driver on array unit
In scan line, the electric capacity is used for the current potential for improving signal point so that gate driver on array unit, which is in, to be opened and export
State.
But because electric capacity is directly connected with horizontal scanning line, charged in gate driver on array unit to horizontal scanning line
When, the electric capacity is just into the parasitic capacitance of horizontal scanning line, when causing output to the signal of the horizontal scanning line to have larger
Between postpone, cause the pixel undercharge in display panel, the problems such as display quality of panel declines.
Therefore, it is necessary to a kind of array base palte horizontal drive circuit is provided, to solve the problems of prior art.
The content of the invention
It is an object of the invention to provide a kind of array base palte horizontal drive circuit, to solve in the prior art because electric capacity is direct
Signal delay problem caused by being connected with horizontal scanning line.
The embodiment of the present invention provides a kind of array base palte horizontal drive circuit, includes multiple array base palte rows driving list of cascade
Member, n-th grade of gate driver on array unit are used to charge to n-th grade of horizontal scanning line, wherein, n is positive integer, described n-th grade
Gate driver on array unit includes：Pull-up circuit, pull-down circuit, drop-down holding circuit, condenser network and output circuit；
The condenser network by a signal point and the pull-up circuit, pull-down circuit, drop-down holding circuit and
Output circuit is connected, and the condenser network is also connected with the drop-down holding circuit in (n-1)th grade of gate driver on array unit, uses
The grid is controlled to believe in the potential change of the drop-down holding circuit in (n-1)th grade of gate driver on array unit
The current potential of number point；
The pull-up circuit is also connected with (n-1)th grade of horizontal scanning line and DC high voltage source respectively；
The pull-down circuit is also connected with (n+1)th grade of horizontal scanning line and DC low-voltage source respectively；
It is described drop-down holding circuit also respectively with n-th grade of horizontal scanning line, DC high voltage source and the DC low-voltage
Source is connected；
The output circuit is also connected with n-th grade of horizontal scanning line, for receiving clock signal, and to described n-th
Level horizontal scanning line charging.
In array base palte horizontal drive circuit of the present invention, the pull-up circuit includes first film transistor, its
In, the first film transistor, its grid is connected with (n-1)th grade of horizontal scanning line, and its source electrode is believed by the grid
Number point is connected with the condenser network, and its drain electrode is connected with the DC high voltage source.
In array base palte horizontal drive circuit of the present invention, the pull-down circuit includes the second thin film transistor (TFT), its
In, second thin film transistor (TFT), its grid is connected with (n+1)th grade of horizontal scanning line, and its drain electrode is believed by the grid
Number point is connected with the condenser network, and its source electrode is connected with the DC low-voltage source.
In array base palte horizontal drive circuit of the present invention, the drop-down holding circuit includes the 3rd film crystal
Pipe, the 4th thin film transistor (TFT), the 5th thin film transistor (TFT) and the 6th thin film transistor (TFT)；
The drain electrode of the source electrode, the 5th thin film transistor (TFT) of 3rd thin film transistor (TFT), its grid and the 4th thin film transistor (TFT)
It is connected with the grid of the 6th thin film transistor (TFT), and connecting node is n-th grade of drop-down control signal point, its drain electrode passes through the grid
Signaling point is connected with the condenser network, and its source electrode is connected with the DC low-voltage source；
4th thin film transistor (TFT), its grid drains with it to be connected, and is connected on the DC high voltage source；
5th thin film transistor (TFT), its grid are connected by the signal point with the condenser network, its source electrode
It is connected with the DC low-voltage source；
6th thin film transistor (TFT), its source electrode are connected with the DC low-voltage source, and it drains and n-th grade of level
Scan line is connected.
In array base palte horizontal drive circuit of the present invention, the output circuit includes the 7th thin film transistor (TFT), institute
The 7th thin film transistor (TFT) is stated, its drain electrode is connected with clock cable, and its source electrode is connected with n-th grade of horizontal scanning line, its grid
Pole is connected by the signal point with the condenser network.
In array base palte horizontal drive circuit of the present invention, the condenser network includes the first electric capacity, and described first
One end of electric capacity is connected on the signal point, and the in the other end and (n-1)th grade of gate driver on array unit
N-1 levels drop-down control signal point is connected.
In array base palte horizontal drive circuit of the present invention, the array base palte horizontal drive circuit also includes zero level
Gate driver on array unit, for being charged to zero level horizontal scanning line, the zero level gate driver on array unit bag
Include：Zero level pull-down circuit, zero level drop-down holding circuit, zero level output circuit；
The zero level pull-down circuit, zero level drop-down holding circuit, zero level output circuit are believed with zero level grid
The connection of number point, the zero level pull-down circuit are also connected with first order horizontal scanning line, DC low-voltage source；
The zero level pulls down holding circuit electricity also low with the zero level horizontal scanning line, DC high voltage source and direct current
Potential source is connected；
The zero level output circuit is also connected with the zero level horizontal scanning line, for receiving clock signal, and to
The zero level horizontal scanning line charging.
In array base palte horizontal drive circuit of the present invention, the zero level pull-down circuit includes the 8th film crystal
Pipe, the 8th thin film transistor (TFT), its grid are connected with the first order horizontal scanning line, and its drain electrode is connected to zero level grid
On signaling point, its source electrode is connected with the DC low-voltage source.
In array base palte horizontal drive circuit of the present invention, the zero level drop-down holding circuit includes the 9th film
Transistor, the tenth thin film transistor (TFT), the 11st thin film transistor (TFT) and the 12nd thin film transistor (TFT), wherein, the 9th film is brilliant
The drain electrode of the source electrode, the 11st thin film transistor (TFT) of body pipe, its grid and the tenth thin film transistor (TFT) and the 12nd thin film transistor (TFT)
Grid is connected, and connecting node is that zero level pulls down control signal point, and its drain electrode is connected on zero level signal point, its source
Pole is connected with the DC low-voltage source；Tenth thin film transistor (TFT), its grid drains with it to be connected, and is connected to described straight
Flow on high voltage source；11st thin film transistor (TFT), its grid are connected on zero level signal point, its source electrode with it is described
DC low-voltage source is connected；12nd thin film transistor (TFT), its source electrode are connected with the DC low-voltage source, and it drains and institute
Zero level horizontal scanning line is stated to be connected.
In array base palte horizontal drive circuit of the present invention, it is brilliant that the zero level output circuit includes the 13rd film
Body pipe, the 13rd thin film transistor (TFT), its drain electrode are connected with clock cable, its source electrode and the zero level horizontal scanning line
It is connected, its grid is connected on zero level signal point.
Compared to existing array base palte horizontal drive circuit, array base palte horizontal drive circuit of the invention passes through n-th grade
Condenser network in gate driver on array unit is connected to the drop-down holding circuit in (n-1)th grade of gate driver on array unit
On, control the grid for drawing high n-th grade to believe according to the potential change for pulling down control signal point in (n-1)th grade of drop-down holding circuit
The current potential of number point so that n-th grade of gate driver on array unit charges to corresponding horizontal scanning line, is not increasing device
On the premise of, solve the horizontal scanning line signal that is brought in the prior art because condenser network is connected with horizontal scanning line
The problem of time delay, greatly improve the display quality of liquid crystal display.
Brief description of the drawings
Fig. 1 is the structural representation of n-th grade of gate driver on array unit in array base palte horizontal drive circuit of the present invention；
Fig. 2 is n-th grade of cascade Connection structural representation with (n+1)th grade of gate driver on array unit；
Fig. 3 is the timing diagram of Fig. 2 cascade Connection circuits；
Fig. 4 is the structural representation of zero level gate driver on array unit in array base palte horizontal drive circuit of the present invention.
Embodiment
The explanation of following embodiment is with reference to additional schema, to illustrate the particular implementation that the present invention can be used to implementation
Example.The direction term that the present invention is previously mentioned, such as " on ", " under ", "front", "rear", "left", "right", " interior ", " outer ", " side "
Deng being only the direction with reference to annexed drawings.Therefore, the direction term used is to illustrate and understand the present invention, and is not used to
The limitation present invention.
In figure, the similar unit of structure is represented with identical label.
Array base palte horizontal drive circuit provided by the invention includes multiple gate driver on array unit of cascade, Mei Gezhen
Row substrate row driver element is used to charge to horizontal scanning line corresponding thereto, except zero level gate driver on array unit
Outside, the structure of other grade of gate driver on array unit is identical, is said below by taking n-th grade of gate driver on array unit as an example
It is bright.
N-th grade of gate driver on array unit include pull-up circuit, pull-down circuit, drop-down holding circuit, condenser network with
And output circuit, wherein, condenser network by a signal point and pull-up circuit, pull-down circuit, drop-down holding circuit and
Output circuit is connected, and condenser network is also connected with the drop-down holding circuit in (n-1)th grade of gate driver on array unit, for root
Carry out the current potential of control gate signaling point according to the potential change of the drop-down holding circuit in (n-1)th grade of gate driver on array unit,
Pull-up circuit is also connected with (n-1)th grade of horizontal scanning line and DC high voltage source respectively, for drawing high the current potential of signal point；
Pull-down circuit is also connected with (n+1)th grade of horizontal scanning line and DC low-voltage source respectively, for dragging down the current potential of signal point；
Drop-down holding circuit is also connected with n-th grade of horizontal scanning line, DC high voltage source and DC low-voltage source respectively, for dragging down the
The current potential of n level horizontal scanning lines, while maintain signal point and n-th grade of horizontal scanning line to be in low-potential state；Output electricity
Road is also connected with n-th grade of horizontal scanning line, is charged for receiving clock signal, and to n-th grade of horizontal scanning line.
Specifically, the drop-down control in the drop-down holding circuit in condenser network and (n-1)th grade of gate driver on array unit
Signaling point processed is connected, and for convenience, the drop-down control signal point in (n-1)th grade of gate driver on array unit is referred to as into below
N-1 levels pull down control signal point, when (n-1)th grade of gate driver on array unit charges to (n-1)th grade of horizontal scanning line, i.e., the
When n-1 levels horizontal scanning line is in high potential, (n-1)th grade of drop-down control signal point is in low potential, when n-th grade of array base palte row
Driver element to n-th grade of horizontal scanning line charged when, (n-1)th grade drop-down control signal point current potential will be changed into from low potential
High potential, the condenser network in n-th grade of gate driver on array unit will be according to the potential rise of (n-1)th grade of drop-down control signal point
High situation improves the current potential of n-th grade of signal point, and then causes the output circuit in n-th grade of gate driver on array unit
Charged to n-th grade of horizontal scanning line.
And for the zero level gate driver on array unit for being charged to zero level horizontal scanning line, its circuit
Structure includes：Zero level pull-down circuit, zero level drop-down holding circuit, zero level output circuit；Wherein, zero level drop-down electricity
Road, zero level drop-down holding circuit, zero level output circuit are connected with zero level signal point, and zero level drop-down maintains electricity
Road is also connected with zero level horizontal scanning line, DC high voltage source and DC low-voltage source；Zero level output circuit is also with the 0th
Level horizontal scanning line is connected, and is charged for receiving clock signal, and to zero level horizontal scanning line；Zero level pull-down circuit also with
First order horizontal scanning line, DC low-voltage source are connected.
Because zero level gate driver on array unit is first unit of whole array base palte horizontal drive circuit, the 0th
Level signal point can not be improved by the drop-down holding circuit of upper level, accordingly, it is desirable to provide initial signal is to the
The signal point of zero level, and the waveform of the initial signal is identical with the waveform of the signal point of other grades, so that the
Zero level gate driver on array unit can charge to zero level horizontal scanning line.Wherein, initial signal can pass through drive
Dynamic chip is supplied to signal point, it is of course also possible to use other forms, it is not particularly limited herein.
Array base palte horizontal drive circuit in this preferred embodiment, by the electric capacity in n-th grade of gate driver on array unit
It is electrically connected on the drop-down holding circuit in (n-1)th grade of gate driver on array unit, is driven according to (n-1)th grade of array base palte row
The potential change of drop-down holding circuit in moving cell controls the current potential for the signal point for drawing high n-th grade so that n-th grade of battle array
Row substrate row driver element charges to n-th grade of horizontal scanning line, on the premise of device is not increased, solves prior art
The problem of middle signal time brought because condenser network is connected with horizontal scanning line postpones, greatly improves liquid crystal display
Display quality.
Fig. 1 is referred to, Fig. 1 is the knot of n-th grade of gate driver on array unit in array base palte horizontal drive circuit of the present invention
Structure schematic diagram.In this preferred embodiment, array base palte horizontal drive circuit includes multiple gate driver on array unit of cascade, often
Individual gate driver on array unit is used to charge to horizontal scanning line corresponding thereto, except zero level array base palte row drives list
First outer, the structure of other grade of gate driver on array unit is identical, is driven below in conjunction with Fig. 1 and with n-th grade of array base palte row
Illustrated exemplified by unit.
N-th grade of gate driver on array unit includes pull-up circuit 110, pull-down circuit 120, drop-down holding circuit 130, electricity
Capacitive circuit 140 and output circuit 150, wherein, pull-up circuit 110 includes first film transistor T1, and pull-down circuit 120 includes
Second thin film transistor (TFT) T2, drop-down holding circuit 130 include the 3rd thin film transistor (TFT) T3, the 4th thin film transistor (TFT) T4, the 5th thin
Film transistor T5 and the 6th thin film transistor (TFT) T6, condenser network 140 include the first electric capacity, and output circuit 150 includes the 7th film
Transistor T7.
First film transistor T1, its grid are connected with (n-1)th grade of horizontal scanning line G (n-1), and its source electrode is believed by grid
Number point Q (n) is connected with one end of the first electric capacity, and its drain electrode is connected with DC high voltage source VDD.
Second thin film transistor (TFT) T2, its grid are connected with (n+1)th grade of horizontal scanning line G (n+1), and it drains is believed by grid
Number point Q (n) is connected with one end of the first electric capacity, and its source electrode is connected with DC low-voltage source VSS.
The leakage of 3rd thin film transistor (TFT) T3, its grid and the 4th thin film transistor (TFT) T4 source electrode, the 5th thin film transistor (TFT) T5
Pole is connected with the 6th thin film transistor (TFT) T6 grid, and connecting node is the drop-down control of n-th grade of gate driver on array unit
Signaling point X (n), hereinafter referred to as n-th grade drop-down control signal point X (n), it drains by signal point Q (n) and the first electric capacity
One end be connected, its source electrode is connected with DC low-voltage source VSS.
4th thin film transistor (TFT) T4, its grid drains with it to be connected, and is connected on the VDD of DC high voltage source；5th is thin
Film transistor T5, its grid are connected by signal point Q (n) with one end of the first electric capacity, its source electrode and DC low-voltage source
VSS is connected；6th thin film transistor (TFT) T6, its source electrode are connected with DC low-voltage source VSS, and it drains and n-th grade of horizontal scanning line G
(n) it is connected.
7th thin film transistor (TFT) T7, its drain electrode are connected with clock cable CK, its source electrode and n-th grade of horizontal scanning line G (n)
It is connected, its grid is connected by signal point Q (n) with one end of the first electric capacity.
One end of first electric capacity is connected on signal point Q (n), and the other end and (n-1)th grade of array base palte row driving are single
(n-1)th grade of drop-down control signal point X (n-1) in member is connected, for the electricity according to (n-1)th grade of drop-down control signal point X (n-1)
Position rise change improves the current potential of n-th grade of signal point Q (n), so that n-th grade of gate driver on array unit can be with
Normally charged to n-th grade of horizontal scanning line G (n).
In order to more clearly illustrate connection of the signal o'clock by the first electric capacity and the drop-down control signal point of upper level
Relation, Figure of description 2 give n-th grade of cascade Connection structural representation with (n+1)th grade of gate driver on array unit, please
Referring to Fig. 2, in Fig. 2, the signal point Q (n+1) in (n+1)th grade of gate driver on array unit passes through the first electric capacity and n-th
Level drop-down control signal point X (n) is connected, and the signal point Q (n) in n-th grade of gate driver on array unit passes through the first electricity
Hold and be connected with (n-1)th grade of drop-down control signal point X (n-1), by that analogy, the annexation between other grades can be obtained.
Fig. 3 is referred to, Fig. 3 is the timing diagram of Fig. 2 cascade Connection circuits.When n-th grade of horizontal scanning line G (n) is in high electricity
Usually, i.e. n-th grade of gate driver on array unit to n-th grade of horizontal scanning line G (n) charge when, (n+1)th grade of array base palte row drives
First film transistor T1 in moving cell will be in open mode so that the current potential quilt of (n+1)th grade of signal point Q (n+1)
Drawing high for the first time, the 7th thin film transistor (TFT) T7 in (n+1)th grade of gate driver on array unit is in open mode, meanwhile,
So that the 5th thin film transistor (TFT) T5 in (n+1)th grade of gate driver on array unit will be in open mode, (n+1)th grade of drop-down control
The current potential of signaling point X (n+1) processed will be pulled low, now the 3rd thin film transistor (TFT) in (n+1)th grade of gate driver on array unit
T3 and the 6th thin film transistor (TFT) T6 are in cut-off state, and the 4th thin film transistor (TFT) T4 connection is equivalent to resistance, (n+1)th grade of battle array
In row substrate row driver element the 4th thin film transistor (TFT) T4 be used to causing electric current can only flow to n-th from DC high voltage source VDD+
1 grade of drop-down control signal point X (n+1), i.e., now the drop-down holding circuit 130 in (n+1)th grade of gate driver on array unit is not
Work.
Because the grid input low level of the second thin film transistor (TFT) T2 in (n+1)th grade of gate driver on array unit is believed
Number, it is also at cut-off state, i.e. pull-down circuit 120 in (n+1)th grade of gate driver on array unit is not to (n+1)th grade of grid
Pole signaling point Q (n+1) carries out dragging down effect.
Because when the current potential of (n+1)th grade of signal point Q (n+1) is drawn high for the first time, (n+1)th grade of array base palte row drives
The clock cable XCK of moving cell signal is low potential, therefore the current potential of (n+1)th grade of horizontal scanning line G (n+1) is low electricity
Position, the low potential of (n+1)th grade of horizontal scanning line G (n+1) also make it that the second film in n-th grade of gate driver on array unit is brilliant
Body pipe T2 is in by state, makes it not carry out dragging down effect to the current potential of n-th grade of signal point Q (n).
When the clock cable XCK of (n+1)th grade of gate driver on array unit signal fades to high potential from low potential,
(n+1)th grade of horizontal scanning line G (n+1) will export high level, and this is allowed in n-th grade of gate driver on array unit second thin
Film transistor T2 is in open mode so that the current potential of n-th grade of signal point Q (n) is pulled low, and n-th grade of array base palte row drives
The 7th thin film transistor (TFT) T7 in moving cell will be in cut-off state, simultaneously as the current potential quilt of n-th grade of signal point Q (n)
Drag down so that the 5th thin film transistor (TFT) T5 in n-th grade of gate driver on array unit is in cut-off state, n-th grade of drop-down control
Signaling point X (n) processed will be connected by the thin film transistor (TFT) T4 equivalent to resistance with DC high voltage source, i.e., n-th grade drop-down control
Signaling point X (n) fades to high potential from low potential, and this 3rd film also allowed in n-th grade of gate driver on array unit is brilliant
Body pipe T3 and the 6th thin film transistor (TFT) T6 are in opening, and now, n-th grade of horizontal scanning line G (n) current potential will be pulled low,
Because the 3rd thin film transistor (TFT) T3 in n-th grade of gate driver on array unit is in opening so that whole n-th grade of array
Drop-down holding circuit 130 in substrate row driver element will maintain n-th grade of signal point Q (n) and n-th grade of horizontal scanning line G
(n) it is in low-potential state.
Due to n-th grade of drop-down control signal point X (n) and (n+1)th grade of signal point Q (n+1) by (n+1)th grade first
Electric capacity is connected so that n-th grade drop-down control signal point X (n) current potential from low potential fade to high potential while, also further improve
The current potential of (n+1)th grade of signal point Q (n+1), and then cause the 7th film in (n+1)th grade of gate driver on array unit
Transistor T7 is in normal transmission state, i.e. (n+1)th grade of horizontal scanning line G (n+1) will be electrically charged.
Such as the dotted line position in Fig. 3, dotted line position is that n-th grade of drop-down control signal point X (n) fades to high potential from low potential
While, the current potential of (n+1)th grade of signal point Q (n+1) is drawn high for the second time so that (n+1)th grade of array base palte row drives
Moving cell can charge to (n+1)th grade of horizontal scanning line G (n+1).
Moreover, as can be seen from Figure 3, in the preferred embodiment, the electricity of the signal point in array base palte horizontal drive circuit
Digit wave form figure is identical with oscillogram of the prior art, therefore, in the case where not changing the potential waveform figure of signal point,
By being connected to the other end of the first electric capacity on the drop-down control signal point of upper level, the drop-down of upper level is made full use of to control
The potential change of signaling point improves the current potential of the signal of this grade point, when greatly reducing the signal of this grade of horizontal scanning line
Between postpone.
Fig. 4 is referred to, Fig. 4 is the knot of zero level gate driver on array unit in array base palte horizontal drive circuit of the present invention
Structure schematic diagram.Zero level gate driver on array unit includes zero level pull-down circuit 210, zero level pulls down holding circuit 220,
Zero level output circuit 230, wherein, zero level pull-down circuit 210 includes the 8th thin film transistor (TFT) T8, and zero level drop-down maintains electricity
It is brilliant that road 220 includes the 9th thin film transistor (TFT) T9, the tenth thin film transistor (TFT) T10, the 11st thin film transistor (TFT) T11 and the 12nd film
Body pipe T12, zero level output circuit 230 include the 13rd thin film transistor (TFT) T13.
8th thin film transistor (TFT) T8, its grid are connected with first order horizontal scanning line G (1), and its drain electrode is connected to zero level
On signal point Q (0), its source electrode is connected with DC low-voltage source VSS.
9th thin film transistor (TFT) T9, its grid and the tenth thin film transistor (TFT) T10 source electrode, the 11st thin film transistor (TFT) T11
Drain electrode be connected with the 12nd thin film transistor (TFT) T12 grid, and connecting node is zero level gate driver on array unit
Control signal point X (0), hereinafter referred to as zero level drop-down control signal point X (0) are pulled down, wherein, zero level drop-down control signal point
X (0) is connected with the signal point Q (1) in first order gate driver on array unit, and it, which drains, is connected to zero level grid letter
On number point Q (0), its source electrode is connected with DC low-voltage source VSS.
Tenth thin film transistor (TFT) T10, its grid drains with it to be connected, and is connected on the VDD of DC high voltage source；11st
Thin film transistor (TFT) T11, its grid are connected on zero level signal point Q (0), and its source electrode is connected with DC low-voltage source VSS；
12nd thin film transistor (TFT) T12, its source electrode are connected with DC low-voltage source VSS, and it drains and zero level horizontal scanning line G (0)
It is connected.
13rd thin film transistor (TFT) T13, its drain electrode are connected with clock cable CK, its source electrode and zero level horizontal scanning line
G (0) is connected, and its grid is connected on zero level signal point Q (0).
Because zero level gate driver on array unit is first unit of whole array base palte horizontal drive circuit, its grid
Pole signaling point Q (0) can not be connected with the drop-down control signal point X of upper level, accordingly, it is desirable to provide initial signal ST is to the
Zero level signal point Q (0), and initial signal ST waveform is identical with the waveform of other grade of signal point, in Fig. 3
Signal point Q (n+1) oscillogram, i.e. ST oscillogram include two elevated square-wave signals of ladder, so that the
Zero level gate driver on array unit can charge to zero level horizontal scanning line G (0).Wherein, initial signal ST can be with
Signal point Q (0) is supplied to by driving chip, it is of course also possible to use other forms, it is not particularly limited herein.
In order to cause DC high voltage source to be believed with grid because electric current is excessive when preventing that signal point Q (n) current potential from drawing high
The damage of circuit between number point Q (n), increases a thin film transistor (TFT) T14 in each gate driver on array unit, and film is brilliant
Body pipe T14 grid is connected with DC high voltage source, and thin film transistor (TFT) T14 source electrode is connected with signal point, film crystal
Pipe T14 drain electrode first film transistor T1 source electrode is connected.
In the preferred embodiment, thin film transistor (TFT) T1 to T14 is amorphous silicon film transistor, is implemented certainly at other
It can also be low-temperature polysilicon film transistor etc. in example, be not particularly limited herein.
Array base palte horizontal drive circuit in this preferred embodiment, by by n-th grade of gate driver on array unit
The other end of first electric capacity is connected on (n-1)th grade of drop-down control signal point, and according to the electricity of (n-1)th grade of drop-down control signal point
Position is raised to improve the current potential of n-th grade of signal point so that n-th grade of gate driver on array unit can be to n-th grade of level
Scan line is charged, and while not increasing device and not changing the potential waveform of signal point, greatly reduces water
The signal time delay of scan lines, improve the display quality and stability of liquid crystal display.
In summary, although the present invention is disclosed above with preferred embodiment, above preferred embodiment simultaneously is not used to limit
The system present invention, one of ordinary skill in the art, without departing from the spirit and scope of the present invention, it can make various changes and profit
Decorations, therefore protection scope of the present invention is defined by the scope that claim defines.
Claims (10)
1. a kind of array base palte horizontal drive circuit, include multiple gate driver on array unit of cascade, n-th grade of array base palte row
Driver element is used to charge to n-th grade of horizontal scanning line, wherein, n is positive integer, n-th grade of gate driver on array unit
Including：Pull-up circuit, pull-down circuit, drop-down holding circuit, condenser network and output circuit；The condenser network passes through a grid
Pole signaling point is connected with the pull-up circuit, pull-down circuit, drop-down holding circuit and output circuit, it is characterised in that described
Condenser network is also connected with the drop-down holding circuit in (n-1)th grade of gate driver on array unit, for according to described (n-1)th grade
The potential change of drop-down holding circuit in gate driver on array unit controls the current potential of the signal point；
The pull-up circuit is also connected with (n-1)th grade of horizontal scanning line and DC high voltage source respectively；
The pull-down circuit is also connected with (n+1)th grade of horizontal scanning line and DC low-voltage source respectively；
It is described drop-down holding circuit also respectively with n-th grade of horizontal scanning line, DC high voltage source and DC low-voltage source phase
Even；
The output circuit is also connected with n-th grade of horizontal scanning line, for receiving clock signal, and to n-th grade of water
Scan lines charge.
2. array base palte horizontal drive circuit according to claim 1, it is characterised in that it is thin that the pull-up circuit includes first
Film transistor, wherein, the first film transistor, its grid is connected with (n-1)th grade of horizontal scanning line, and its source electrode passes through
The signal point is connected with the condenser network, and its drain electrode is connected with the DC high voltage source.
3. array base palte horizontal drive circuit according to claim 1, it is characterised in that it is thin that the pull-down circuit includes second
Film transistor, wherein, second thin film transistor (TFT), its grid is connected with (n+1)th grade of horizontal scanning line, and its drain electrode passes through
The signal point is connected with the condenser network, and its source electrode is connected with the DC low-voltage source.
4. array base palte horizontal drive circuit according to claim 1, it is characterised in that the drop-down holding circuit includes the
Three thin film transistor (TFT)s, the 4th thin film transistor (TFT), the 5th thin film transistor (TFT) and the 6th thin film transistor (TFT)；
The drain electrode of the source electrode, the 5th thin film transistor (TFT) of 3rd thin film transistor (TFT), its grid and the 4th thin film transistor (TFT) and
The grid of six thin film transistor (TFT)s is connected, and connecting node is n-th grade of drop-down control signal point, and its drain electrode passes through the signal
Point is connected with the condenser network, and its source electrode is connected with the DC low-voltage source；
4th thin film transistor (TFT), its grid drains with it to be connected, and is connected on the DC high voltage source；
5th thin film transistor (TFT), its grid are connected by the signal point with the condenser network, its source electrode and institute
DC low-voltage source is stated to be connected；
6th thin film transistor (TFT), its source electrode are connected with the DC low-voltage source, and it drains and n-th grade of horizontal sweep
Line is connected.
5. array base palte horizontal drive circuit according to claim 1, it is characterised in that it is thin that the output circuit includes the 7th
Film transistor, the 7th thin film transistor (TFT), its drain electrode are connected with clock cable, its source electrode and n-th grade of horizontal sweep
Line is connected, and its grid is connected by the signal point with the condenser network.
6. array base palte horizontal drive circuit according to claim 4, it is characterised in that the condenser network includes the first electricity
Hold, one end of first electric capacity is connected on the signal point, and the other end drives with (n-1)th grade of array base palte row
(n-1)th grade of drop-down control signal point in unit is connected.
7. array base palte horizontal drive circuit according to claim 1, it is characterised in that the array base palte horizontal drive circuit
Also include zero level gate driver on array unit, for being charged to zero level horizontal scanning line, the zero level array base palte
Row driver element includes：Zero level pull-down circuit, zero level drop-down holding circuit, zero level output circuit；
The zero level pull-down circuit, zero level drop-down holding circuit, zero level output circuit with zero level signal point
Connection, the zero level pull-down circuit are also connected with first order horizontal scanning line, DC low-voltage source；
Zero level drop-down holding circuit also with zero level horizontal scanning line, DC high voltage source and the DC low-voltage source
It is connected；
The zero level output circuit is also connected with the zero level horizontal scanning line, for receiving clock signal, and to described
Zero level horizontal scanning line charges.
8. array base palte horizontal drive circuit according to claim 7, it is characterised in that the zero level pull-down circuit includes
8th thin film transistor (TFT), the 8th thin film transistor (TFT), its grid are connected with the first order horizontal scanning line, its connection that drains
On zero level signal point, its source electrode is connected with the DC low-voltage source.
9. array base palte horizontal drive circuit according to claim 7, it is characterised in that the zero level pulls down holding circuit
Including the 9th thin film transistor (TFT), the tenth thin film transistor (TFT), the 11st thin film transistor (TFT) and the 12nd thin film transistor (TFT), wherein, institute
The 9th thin film transistor (TFT) is stated, the drain electrode and the 12nd of the source electrode, the 11st thin film transistor (TFT) of its grid and the tenth thin film transistor (TFT)
The grid of thin film transistor (TFT) is connected, and connecting node is that zero level pulls down control signal point, and its drain electrode is connected to zero level grid
On signaling point, its source electrode is connected with the DC low-voltage source；Tenth thin film transistor (TFT), its grid drains with it to be connected,
And it is connected on the DC high voltage source；11st thin film transistor (TFT), its grid are connected to zero level signal point
On, its source electrode is connected with the DC low-voltage source；12nd thin film transistor (TFT), its source electrode and the DC low-voltage source
It is connected, its drain electrode is connected with the zero level horizontal scanning line.
10. array base palte horizontal drive circuit according to claim 7, it is characterised in that the zero level output circuit bag
The 13rd thin film transistor (TFT), the 13rd thin film transistor (TFT) are included, its drain electrode is connected with clock cable, its source electrode and described the
Zero level horizontal scanning line is connected, and its grid is connected on zero level signal point.
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| CN201610539964.2A CN105931611B (en) | 2016-07-08 | 2016-07-08 | A kind of array base palte horizontal drive circuit |
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| CN201610539964.2A CN105931611B (en) | 2016-07-08 | 2016-07-08 | A kind of array base palte horizontal drive circuit |
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| CN105931611B true CN105931611B (en) | 2018-03-27 |
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| CN106205558B (en) * | 2016-09-30 | 2018-09-21 | 京东方科技集团股份有限公司 | Image element driving method and device |
| CN108597431A (en) | 2018-02-12 | 2018-09-28 | 京东方科技集团股份有限公司 | Shift register cell and its control method, gate driving circuit, display device |
| CN108922488B (en) | 2018-08-31 | 2020-05-12 | 重庆惠科金渝光电科技有限公司 | Array substrate, display panel and display device |
| CN110517624B (en) * | 2019-09-27 | 2022-10-04 | 合肥京东方显示技术有限公司 | Shift register unit, gate drive circuit and display device |
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| CN103680386B (en) * | 2013-12-18 | 2016-03-09 | 深圳市华星光电技术有限公司 | For GOA circuit and the display device of flat pannel display |
| CN103680451B (en) * | 2013-12-18 | 2015-12-30 | 深圳市华星光电技术有限公司 | For GOA circuit and the display device of liquid crystal display |
| CN103928007B (en) * | 2014-04-21 | 2016-01-20 | 深圳市华星光电技术有限公司 | A kind of GOA circuit for liquid crystal display and liquid crystal indicator |
| CN103928008B (en) * | 2014-04-24 | 2016-10-05 | 深圳市华星光电技术有限公司 | A kind of GOA circuit for liquid crystal display and liquid crystal indicator |
| CN104064159B (en) * | 2014-07-17 | 2016-06-15 | 深圳市华星光电技术有限公司 | There is the gate driver circuit of self-compensating function |
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