CN105931611A - Array substrate row driving circuit - Google Patents
Array substrate row driving circuit Download PDFInfo
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- CN105931611A CN105931611A CN201610539964.2A CN201610539964A CN105931611A CN 105931611 A CN105931611 A CN 105931611A CN 201610539964 A CN201610539964 A CN 201610539964A CN 105931611 A CN105931611 A CN 105931611A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides an array substrate row driving circuit, which comprises a plurality of cascaded array substrate row driving units. The nth array substrate row driving unit comprises a pull-up circuit, a pull-down circuit, a pull-down holding circuit, a capacitive circuit and an output circuit, wherein the capacitive circuit is respectively connected with a grid signal point and a pull-down holding circuit of the (n-1)th array substrate row driving unit and used for controlling the potential o the grid signal point according to potential variations of the pull-down holding circuit of the (n-1)th array substrate row driving unit. The array substrate row driving circuit provided by the invention can reduce the time delay of horizontal scanning line signals under the premise of not increasing the number of devices and not changing the potential waveform of the grid signal point, and greatly improves the display quality of a liquid crystal display.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly relate to a kind of array base palte row
Drive circuit.
Background technology
GOA (Gate-driver On Array) technology, i.e. array base palte row cutting technology,
Due to its can save the cost of Gate IC, reduction panel border width etc. and by extensively
Apply in display floater.Existing array base palte horizontal drive circuit is by cascade n
Gate driver on array unit forms, and is designed with in each gate driver on array unit
One electric capacity, one end of this electric capacity is connected on signal point, the other end be connected to
On the horizontal scanning line that this gate driver on array unit is corresponding, this electric capacity is used for improving
The current potential of signal point so that gate driver on array unit is in be opened and exports shape
State.
But owing to electric capacity is directly connected with horizontal scanning line, at array base palte row cutting list
Unit is when horizontal scanning line charges, and this electric capacity has just become the parasitic capacitance of horizontal scanning line,
Cause the signal exported to this horizontal scanning line to have bigger time delay, cause display
Pixel undercharge in panel, degradation problem under the display quality of panel.
Therefore, it is necessary to provide a kind of array base palte horizontal drive circuit, to solve prior art
Existing problem.
Summary of the invention
It is an object of the invention to provide a kind of array base palte horizontal drive circuit, existing to solve
There is the signal delay problem caused because electric capacity is directly connected in technology with horizontal scanning line.
The embodiment of the present invention provides a kind of array base palte horizontal drive circuit, many including cascade
Individual gate driver on array unit, n-th grade of gate driver on array unit is for n-th
Level horizontal scanning line charging, wherein, n is positive integer, and described n-th grade of array base palte row drives
Moving cell includes: pull-up circuit, pull-down circuit, drop-down holding circuit, condenser network with
And output circuit；
Described condenser network by a signal point and described pull-up circuit, pull-down circuit,
Drop-down holding circuit and output circuit are connected, described condenser network also with (n-1)th grade of battle array
Drop-down holding circuit in row substrate row cutting unit is connected, for according to described (n-1)th
The potential change of the drop-down holding circuit in level gate driver on array unit controls described
The current potential of signal point；
Described pull-up circuit the most respectively with (n-1)th grade of horizontal scanning line and DC high voltage source
It is connected；
Described pull-down circuit the most respectively with (n+1)th grade of horizontal scanning line and DC low-voltage source
It is connected；
Described drop-down holding circuit is high with described n-th grade of horizontal scanning line, direct current the most respectively
Voltage source is connected with DC low-voltage source；
Described output circuit is also connected, when being used for receiving with described n-th grade of horizontal scanning line
Clock signal, and to described n-th grade of horizontal scanning line charging.
In array base palte horizontal drive circuit of the present invention, described pull-up circuit includes
The first film transistor, wherein, described the first film transistor, its grid and described the
N-1 level horizontal scanning line is connected, and its source electrode is by described signal point and described electric capacity electricity
Road is connected, and its drain electrode is connected with described DC high voltage source.
In array base palte horizontal drive circuit of the present invention, described pull-down circuit includes
Second thin film transistor (TFT), wherein, described second thin film transistor (TFT), its grid and described the
N+1 level horizontal scanning line is connected, and its drain electrode is by described signal point and described electric capacity electricity
Road is connected, and its source electrode is connected with described DC low-voltage source.
In array base palte horizontal drive circuit of the present invention, described drop-down holding circuit
Including the 3rd thin film transistor (TFT), the 4th thin film transistor (TFT), the 5th thin film transistor (TFT) and the 6th
Thin film transistor (TFT)；
Described 3rd thin film transistor (TFT), its grid and the source electrode of the 4th thin film transistor (TFT),
The drain electrode of five thin film transistor (TFT)s is connected with the grid of the 6th thin film transistor (TFT), and connects node
Being n-th grade of drop-down control signal point, its drain electrode is by described signal point and described electricity
Capacitive circuit is connected, and its source electrode is connected with described DC low-voltage source；
Described 4th thin film transistor (TFT), its grid drains with it and is connected, and is connected to described
On DC high voltage source；
Described 5th thin film transistor (TFT), its grid is by described signal point and described electricity
Capacitive circuit is connected, and its source electrode is connected with described DC low-voltage source；
Described 6th thin film transistor (TFT), its source electrode is connected with described DC low-voltage source, its
Drain electrode is connected with described n-th grade of horizontal scanning line.
In array base palte horizontal drive circuit of the present invention, described output circuit includes
7th thin film transistor (TFT), described 7th thin film transistor (TFT), its drain electrode and clock cable phase
Even, its source electrode is connected with described n-th grade of horizontal scanning line, and its grid passes through described grid
Signaling point is connected with described condenser network.
In array base palte horizontal drive circuit of the present invention, described condenser network includes
First electric capacity, one end of described first electric capacity is connected on described signal point, another
End and (n-1)th grade of drop-down control signal in described (n-1)th grade of gate driver on array unit
Point is connected.
In array base palte horizontal drive circuit of the present invention, described array base palte row drives
Galvanic electricity road also includes zero level gate driver on array unit, for sweeping zero level level
Retouching line charging, described zero level gate driver on array unit includes: the drop-down electricity of zero level
Road, the drop-down holding circuit of zero level, zero level output circuit；
Described zero level pull-down circuit, the drop-down holding circuit of zero level, zero level output electricity
Lu Junyu zero level signal point connect, described zero level pull-down circuit also with the first order
Horizontal scanning line, DC low-voltage source are connected；
The described drop-down holding circuit of zero level also with described zero level horizontal scanning line, direct current
High voltage source is connected with DC low-voltage source；
Described zero level output circuit is also connected with described zero level horizontal scanning line, is used for
Receive clock signal, and charge to described zero level horizontal scanning line.
In array base palte horizontal drive circuit of the present invention, the described drop-down electricity of zero level
Road includes the 8th thin film transistor (TFT), described 8th thin film transistor (TFT), its grid and described the
Primary plateaus scan line is connected, and its drain electrode is connected on zero level signal point, its source
Pole is connected with described DC low-voltage source.
In array base palte horizontal drive circuit of the present invention, the described drop-down dimension of zero level
Hold circuit and include the 9th thin film transistor (TFT), the tenth thin film transistor (TFT), the 11st film crystal
Pipe and the 12nd thin film transistor (TFT), wherein, described 9th thin film transistor (TFT), its grid with
The source electrode of the tenth thin film transistor (TFT), the drain electrode of the 11st thin film transistor (TFT) and the 12nd thin film
The grid of transistor is connected, and connection node is zero level drop-down control signal point, its leakage
Pole is connected on zero level signal point, and its source electrode is connected with described DC low-voltage source；
Described tenth thin film transistor (TFT), its grid drains with it and is connected, and is connected to described direct current
On high voltage source；Described 11st thin film transistor (TFT), its grid is connected to zero level grid
On signaling point, its source electrode is connected with described DC low-voltage source；Described 12nd thin film is brilliant
Body pipe, its source electrode is connected with described DC low-voltage source, its drain electrode and described zero level water
Scan lines is connected.
In array base palte horizontal drive circuit of the present invention, described zero level output electricity
Road includes the 13rd thin film transistor (TFT), described 13rd thin film transistor (TFT), its drain electrode and time
Clock holding wire is connected, and its source electrode is connected with described zero level horizontal scanning line, and its grid is even
It is connected on zero level signal point.
Compared to existing array base palte horizontal drive circuit, the array base palte row of the present invention drives
Galvanic electricity road is by being connected to the condenser network in n-th grade of gate driver on array unit
On drop-down holding circuit in (n-1)th grade of gate driver on array unit, according to (n-1)th
In the drop-down holding circuit of level, the potential change of drop-down control signal point controls to draw high n-th
The current potential of the signal point of level so that n-th grade of gate driver on array unit is to accordingly
Horizontal scanning line be charged, on the premise of not increasing device, solve existing skill
The horizontal scanning line signal brought because condenser network is connected with horizontal scanning line in art
The problem of time delay, be greatly improved the display quality of liquid crystal display.
Accompanying drawing explanation
Fig. 1 is n-th grade of array base palte row cutting in array base palte horizontal drive circuit of the present invention
The structural representation of unit；
Fig. 2 is n-th grade and is connected knot with the cascade of (n+1)th grade of gate driver on array unit
Structure schematic diagram；
Fig. 3 is that Fig. 2 cascades the sequential chart connecting circuit；
Fig. 4 is that in array base palte horizontal drive circuit of the present invention, zero level array base palte row drives
The structural representation of moving cell.
Detailed description of the invention
The explanation of following embodiment is graphic with reference to add, can in order to illustrate the present invention
In order to the specific embodiment implemented.The direction term that the present invention is previously mentioned, such as " on ",
D score, "front", "rear", "left", "right", " interior ", " outward ", " side " etc., only
It it is the direction with reference to annexed drawings.Therefore, the direction term of use is to illustrate and manage
Solve the present invention, and be not used to limit the present invention.
In the drawings, the unit that structure is similar is to represent with identical label.
The array base palte horizontal drive circuit that the present invention provides includes multiple array bases of cascade
Plate row cutting unit, each gate driver on array unit is for water corresponding thereto
Scan lines is charged, in addition to zero level gate driver on array unit, and other grade of array base
The structure of plate row cutting unit is identical, with n-th grade of gate driver on array unit is below
Example illustrates.
N-th grade of gate driver on array unit includes pull-up circuit, pull-down circuit, drop-down
Holding circuit, condenser network and output circuit, wherein, condenser network passes through a grid
Signaling point is connected with pull-up circuit, pull-down circuit, drop-down holding circuit and output circuit,
Condenser network also with the drop-down holding circuit phase in (n-1)th grade of gate driver on array unit
Even, for according to the drop-down holding circuit in (n-1)th grade of gate driver on array unit
Potential change carrys out the current potential of control gate signaling point, pull-up circuit the most respectively with (n-1)th grade
Horizontal scanning line is connected with DC high voltage source, for drawing high the current potential of signal point；
Pull-down circuit is connected with (n+1)th grade of horizontal scanning line and DC low-voltage source the most respectively, uses
In the current potential dragging down signal point；Drop-down holding circuit is swept with n-th grade of level the most respectively
Retouch line, DC high voltage source is connected with DC low-voltage source, is used for dragging down n-th grade of level
The current potential of scan line, maintains signal point and n-th grade of horizontal scanning line to be in low simultaneously
Potential state；Output circuit is also connected with n-th grade of horizontal scanning line, is used for receiving clock
Signal, and to n-th grade of horizontal scanning line charging.
Specifically, drop-down in condenser network and (n-1)th grade of gate driver on array unit
Drop-down control signal point in holding circuit is connected, for convenience, below by (n-1)th grade
Drop-down control signal point in gate driver on array unit is referred to as (n-1)th grade of drop-down control
Signaling point, when (n-1)th grade of gate driver on array unit is filled to (n-1)th grade of horizontal scanning line
During electricity, when i.e. (n-1)th grade horizontal scanning line is in high potential, (n-1)th grade of drop-down control is believed
Number point is in electronegative potential, when n-th grade of gate driver on array unit is swept to n-th grade of level
Retouching line when being charged, the current potential of (n-1)th grade of drop-down control signal point will become from electronegative potential
For high potential, the condenser network in n-th grade of gate driver on array unit will be according to (n-1)th
The current potential rising condition of the drop-down control signal point of level improves the electricity of n-th grade of signal point
Position, and then make the output circuit in n-th grade of gate driver on array unit to n-th grade
Horizontal scanning line charges.
And for for the zero level array base palte row of zero level horizontal scanning line charging is driven
For moving cell, its circuit structure includes: zero level pull-down circuit, the drop-down dimension of zero level
Hold circuit, zero level output circuit；Wherein, zero level pull-down circuit, zero level are drop-down
Holding circuit, zero level output circuit are all connected with zero level signal point, zero level
Drop-down holding circuit also with zero level horizontal scanning line, DC high voltage source and the low electricity of direct current
Potential source is connected；Zero level output circuit is also connected with zero level horizontal scanning line, is used for connecing
Receive clock signal, and charge to zero level horizontal scanning line；Zero level pull-down circuit also with
First order horizontal scanning line, DC low-voltage source are connected.
Owing to zero level gate driver on array unit is whole array base palte horizontal drive circuit
First unit, zero level signal point cannot by upper level drop-down maintenance electricity
Road is improved, accordingly, it is desirable to provide an initial signal is to the signal point of zero level,
And the waveform of this initial signal is identical with the waveform of the signal of other grades point, so that
Obtain zero level gate driver on array unit can zero level horizontal scanning line be filled
Electricity.Wherein, initial signal can be supplied to signal point by driving chip, certainly,
Other forms can also be used, be not particularly limited at this.
Array base palte horizontal drive circuit in this preferred embodiment, by n-th grade of array base palte
Condenser network in row cutting unit is connected in (n-1)th grade of gate driver on array unit
Drop-down holding circuit on, drop-down according in (n-1)th grade of gate driver on array unit
The potential change of holding circuit controls to draw high the current potential of the signal point of n-th grade, makes
Obtain n-th grade of gate driver on array unit n-th grade of horizontal scanning line is charged,
On the premise of not increasing device, solve in prior art because condenser network is swept with level
The problem that the signal time retouching line connection and bring postpones, is greatly improved liquid crystal display
Display quality.
Referring to Fig. 1, Fig. 1 is n-th grade of battle array in array base palte horizontal drive circuit of the present invention
The structural representation of row substrate row cutting unit.In this preferred embodiment, array base palte row
Drive circuit includes multiple gate driver on array unit of cascade, each array base palte row
Driver element is for charging to horizontal scanning line corresponding thereto, except zero level array base
Outside plate row cutting unit, the structure of other grade of gate driver on array unit is identical, below
To illustrate in conjunction with Fig. 1 and as a example by n-th grade of gate driver on array unit.
N-th grade of gate driver on array unit include pull-up circuit 110, pull-down circuit 120,
Drop-down holding circuit 130, condenser network 140 and output circuit 150, wherein, pull-up
Circuit 110 includes the first film transistor T1, and pull-down circuit 120 includes that the second thin film is brilliant
Body pipe T2, drop-down holding circuit 130 includes that the 3rd thin film transistor (TFT) T3, the 4th thin film are brilliant
Body pipe T4, the 5th thin film transistor (TFT) T5 and the 6th thin film transistor (TFT) T6, condenser network 140
Including the first electric capacity, output circuit 150 includes the 7th thin film transistor (TFT) T7.
The first film transistor T1, its grid and (n-1)th grade of horizontal scanning line G (n-1) phase
Even, its source electrode is connected with one end of the first electric capacity by signal point Q (n), its drain electrode
It is connected with DC high voltage source VDD.
Second thin film transistor (TFT) T2, its grid and (n+1)th grade of horizontal scanning line G (n+1)
Being connected, its drain electrode is connected by one end of signal point Q (n) with the first electric capacity, its source
Pole is connected with DC low-voltage source VSS.
3rd thin film transistor (TFT) T3, its grid and the source electrode of the 4th thin film transistor (TFT) T4,
The drain electrode of the 5th thin film transistor (TFT) T5 is connected with the grid of the 6th thin film transistor (TFT) T6, and
Connect drop-down control signal point X (n) that node is n-th grade of gate driver on array unit,
Hereinafter referred to as n-th grade drop-down control signal point X (n), its drain electrode is by signal point
Q (n) is connected with one end of the first electric capacity, and its source electrode is connected with DC low-voltage source VSS.
4th thin film transistor (TFT) T4, its grid drains with it and is connected, and it is high to be connected to direct current
On voltage source VDD；5th thin film transistor (TFT) T5, its grid passes through signal point Q (n)
Being connected with one end of the first electric capacity, its source electrode is connected with DC low-voltage source VSS；6th
Thin film transistor (TFT) T6, its source electrode is connected with DC low-voltage source VSS, its drain electrode and n-th
Level horizontal scanning line G (n) is connected.
7th thin film transistor (TFT) T7, its drain electrode is connected with clock cable CK, its source electrode
Being connected with n-th grade of horizontal scanning line G (n), its grid is by signal point Q (n) and the
One end of one electric capacity is connected.
One end of first electric capacity is connected in signal point Q (n), the other end and (n-1)th
(n-1)th grade of drop-down control signal point X (n-1) in level gate driver on array unit is connected,
For improving according to the potential rise High variation of (n-1)th grade of drop-down control signal point X (n-1)
The current potential of n-th grade of signal point Q (n), so that n-th grade of array base palte row cutting
Unit can be normally to n-th grade of horizontal scanning line G (n) charging.
In order to drop-down by the first electric capacity and upper level of signal point is more clearly described
The annexation of control signal point, Figure of description 2 gives n-th grade and (n+1)th grade
The cascade attachment structure schematic diagram of gate driver on array unit, refers to Fig. 2, Fig. 2
In, signal point Q (n+1) in (n+1)th grade of gate driver on array unit is passed through
First electric capacity and n-th grade of drop-down control signal point X (n) are connected, n-th grade of array base palte row
Signal point Q (n) in driver element passes through the first electric capacity and (n-1)th grade of drop-down control
Signaling point X (n-1) is connected, and by that analogy, just can get the annexation of other inter-stages.
Referring to Fig. 3, Fig. 3 is that Fig. 2 cascades the sequential chart connecting circuit.When n-th grade
When horizontal scanning line G (n) is in high level, i.e. n-th grade gate driver on array unit to
During n-th grade of horizontal scanning line G (n) charging, (n+1)th grade of gate driver on array unit
In the first film transistor T1 will be in open mode so that (n+1)th grade of grid letter
The current potential of number some Q (n+1) is drawn high for the first time, (n+1)th grade of array base palte row cutting list
The 7th thin film transistor (TFT) T7 in unit is in open mode, meanwhile, also makes (n+1)th
The 5th thin film transistor (TFT) T5 in level gate driver on array unit will be in and open shape
State, the current potential of (n+1)th grade of drop-down control signal point X (n+1) will be pulled low, and now
The 3rd thin film transistor (TFT) T3 in n+1 level gate driver on array unit and the 6th thin film
Transistor T6 is in cut-off state, and the connection of the 4th thin film transistor (TFT) T4 is equivalent to
Resistance, in (n+1)th grade of gate driver on array unit, the 4th thin film transistor (TFT) T4 is used for
Make electric current only can flow to (n+1)th grade of drop-down control from DC high voltage source VDD to believe
Number some X (n+1), the most now drop-down dimension in (n+1)th grade of gate driver on array unit
Hold circuit 130 not work.
Due to the second thin film transistor (TFT) T2 in (n+1)th grade of gate driver on array unit
Grid input low level signal so that it is be also at cut-off state, i.e. (n+1)th grade array
Pull-down circuit 120 in substrate row cutting unit is not to (n+1)th grade of signal point
Q (n+1) carries out dragging down effect.
Due to when the current potential of (n+1)th grade of signal point Q (n+1) is drawn high for the first time,
The signal of the clock cable XCK of (n+1)th grade of gate driver on array unit is low electricity
Position, therefore the current potential of (n+1)th grade of horizontal scanning line G (n+1) is electronegative potential, (n+1)th
The electronegative potential of level horizontal scanning line G (n+1) also makes n-th grade of array base palte row cutting list
The second thin film transistor (TFT) T2 in unit is in by state so that it is not to n-th grade of grid
The current potential of signaling point Q (n) carries out dragging down effect.
Signal as the clock cable XCK of (n+1)th grade of gate driver on array unit
When electronegative potential fades to high potential, (n+1)th grade of horizontal scanning line G (n+1) will output height
Level, this allows for the second thin film transistor (TFT) in n-th grade of gate driver on array unit
T2 is in open mode so that the current potential of n-th grade of signal point Q (n) is pulled low,
The 7th thin film transistor (TFT) T7 in n-th grade of gate driver on array unit will be in cut-off
State, simultaneously as the current potential of n-th grade of signal point Q (n) is pulled low so that the
The 5th thin film transistor (TFT) T5 in n level gate driver on array unit is in cut-off state,
N-th grade of drop-down control signal point X (n) is by the thin film transistor (TFT) T4 by being equivalent to resistance
Being connected with DC high voltage source, i.e. n-th grade drop-down control signal point X (n) becomes from electronegative potential
To high potential, this also allows for the 3rd thin film in n-th grade of gate driver on array unit
Transistor T3 and the 6th thin film transistor (TFT) T6 is in opening, now, and n-th grade
The current potential of horizontal scanning line G (n) will be pulled low, due to n-th grade of array base palte row cutting list
The 3rd thin film transistor (TFT) T3 in unit is in opening so that whole n-th grade of array
Drop-down holding circuit 130 in substrate row cutting unit will maintain n-th grade of signal point
Q (n) and n-th grade of horizontal scanning line G (n) are in low-potential state.
Due to n-th grade of drop-down control signal point X (n) and (n+1)th grade of signal point
Q (n+1) is connected by first electric capacity of (n+1)th grade so that n-th grade of drop-down control signal
Point X (n) current potential, while electronegative potential fades to high potential, also further increases (n+1)th
The current potential of level signal point Q (n+1), and then (n+1)th grade of array base palte row is driven
The 7th thin film transistor (TFT) T7 in moving cell is in normal transmission state, i.e. (n+1)th grade
Horizontal scanning line G (n+1) will be electrically charged.
Such as the dotted line position in Fig. 3, dotted line position is n-th grade of drop-down control signal point
While X (n) fades to high potential from electronegative potential, by (n+1)th grade of signal point Q (n+1)
Current potential carry out second time draw high so that (n+1)th grade of gate driver on array unit is permissible
To (n+1)th grade of horizontal scanning line G (n+1) charging.
And, as can be seen from Figure 3, in the preferred embodiment, array base palte row cutting electricity
The potential waveform figure of the signal point in road is identical with oscillogram of the prior art, because of
This, in the case of the potential waveform figure not changing signal point, by by the first electricity
The other end held is connected on the drop-down control signal point of upper level, makes full use of upper level
The potential change of drop-down control signal point improve the current potential of signal point of this grade,
The signal time greatly reducing this grade of horizontal scanning line postpones.
Referring to Fig. 4, Fig. 4 is zero level battle array in array base palte horizontal drive circuit of the present invention
The structural representation of row substrate row cutting unit.Zero level gate driver on array unit bag
Include zero level pull-down circuit 210, the drop-down holding circuit of zero level 220, zero level output electricity
Road 230, wherein, zero level pull-down circuit 210 includes the 8th thin film transistor (TFT) T8, the
The drop-down holding circuit of zero level 220 includes the 9th thin film transistor (TFT) T9, the tenth thin film transistor (TFT)
T10, the 11st thin film transistor (TFT) T11 and the 12nd thin film transistor (TFT) T12, zero level is defeated
Go out circuit 230 and include the 13rd thin film transistor (TFT) T13.
8th thin film transistor (TFT) T8, its grid is connected with first order horizontal scanning line G (1),
Its drain electrode is connected in zero level signal point Q (0), its source electrode and DC low-voltage source
VSS is connected.
9th thin film transistor (TFT) T9, its grid and the source electrode of the tenth thin film transistor (TFT) T10,
The drain electrode of the 11st thin film transistor (TFT) T11 and the grid phase of the 12nd thin film transistor (TFT) T12
Connect, and connect the drop-down control signal point that node is zero level gate driver on array unit
X (0), hereinafter referred to as zero level drop-down control signal point X (0), wherein, zero level is drop-down
Control signal point X (0) and the signal point in first order gate driver on array unit
Q (1) is connected, and its drain electrode is connected in zero level signal point Q (0), and its source electrode is with straight
Stream low-voltage source VSS is connected.
Tenth thin film transistor (TFT) T10, its grid drains with it and is connected, and it is high to be connected to direct current
On voltage source VDD；11st thin film transistor (TFT) T11, its grid is connected to zero level grid
On pole signaling point Q (0), its source electrode is connected with DC low-voltage source VSS；12nd thin film
Transistor T12, its source electrode is connected with DC low-voltage source VSS, its drain electrode and zero level
Horizontal scanning line G (0) is connected.
13rd thin film transistor (TFT) T13, its drain electrode is connected with clock cable CK, its source
Pole is connected with zero level horizontal scanning line G (0), and its grid is connected to zero level signal
On some Q (0).
Owing to zero level gate driver on array unit is whole array base palte horizontal drive circuit
First unit, its signal point Q (0) cannot be with the drop-down control signal of upper level
Point X is connected, accordingly, it is desirable to provide initial signal ST gives zero level signal point
Q (0), and the waveform of this initial signal ST is identical with the waveform of other grade of signal point,
Such as the oscillogram of signal point Q (n+1) in Fig. 3, i.e. the oscillogram of ST includes
The square-wave signal that two ladders raise, so that zero level gate driver on array unit
Zero level horizontal scanning line G (0) can be charged.Wherein, initial signal ST is permissible
It is supplied to signal point Q (0), it is of course also possible to use other shapes by driving chip
Formula, it is not particularly limited at this.
Straight in order to cause because electric current is excessive when preventing signal point Q (n) current potential from drawing high
The damage of circuit between stream high voltage source and signal point Q (n), at each array base palte
Row cutting unit increases a thin film transistor (TFT) T14, the grid of thin film transistor (TFT) T14
Being connected with DC high voltage source, the source electrode of thin film transistor (TFT) T14 is connected with signal point,
The source electrode of the drain electrode the first film transistor T1 of thin film transistor (TFT) T14 is connected.
In the preferred embodiment, thin film transistor (TFT) T1 to T14 is amorphous silicon membrane
Transistor, can also be low-temperature polysilicon film transistor the most in other embodiments
Deng, it is not particularly limited at this.
Array base palte horizontal drive circuit in this preferred embodiment, by by n-th grade of array
The other end of the first electric capacity in substrate row cutting unit is connected to (n-1)th grade of drop-down control
On signaling point, and improve n-th according to the current potential rising of (n-1)th grade of drop-down control signal point
The current potential of level signal point so that n-th grade of gate driver on array unit can be to the
N level horizontal scanning line is charged, and is not increasing device and is not changing signal point
While potential waveform, greatly reduce the signal time time delay of horizontal scanning line, improve
The display quality of liquid crystal display and stability.
In sum, although the present invention is disclosed above with preferred embodiment, but above-mentioned excellent
Select embodiment and be not used to limit the present invention, those of ordinary skill in the art, not taking off
In the spirit and scope of the present invention, all can make various change and retouching, the therefore present invention
Protection domain define in the range of standard with claim.
Claims (10)
1. an array base palte horizontal drive circuit, it is characterised in that include the multiple of cascade
Gate driver on array unit, n-th grade of gate driver on array unit is for n-th grade
Horizontal scanning line charges, and wherein, n is positive integer, described n-th grade of array base palte row cutting
Unit includes: pull-up circuit, pull-down circuit, drop-down holding circuit, condenser network and
Output circuit；
Described condenser network by a signal point and described pull-up circuit, pull-down circuit,
Drop-down holding circuit and output circuit are connected, described condenser network also with (n-1)th grade of battle array
Drop-down holding circuit in row substrate row cutting unit is connected, for according to described (n-1)th
The potential change of the drop-down holding circuit in level gate driver on array unit controls described
The current potential of signal point；
Described pull-up circuit the most respectively with (n-1)th grade of horizontal scanning line and DC high voltage source
It is connected；
Described pull-down circuit the most respectively with (n+1)th grade of horizontal scanning line and DC low-voltage source
It is connected；
Described drop-down holding circuit is high with described n-th grade of horizontal scanning line, direct current the most respectively
Voltage source is connected with DC low-voltage source；
Described output circuit is also connected, when being used for receiving with described n-th grade of horizontal scanning line
Clock signal, and to described n-th grade of horizontal scanning line charging.
Array base palte horizontal drive circuit the most according to claim 1, it is characterised in that
Described pull-up circuit includes the first film transistor, wherein, described the first film transistor,
Its grid is connected with described (n-1)th grade of horizontal scanning line, and its source electrode is believed by described grid
Number point is connected with described condenser network, and its drain electrode is connected with described DC high voltage source.
Array base palte horizontal drive circuit the most according to claim 1, it is characterised in that
Described pull-down circuit includes the second thin film transistor (TFT), wherein, described second thin film transistor (TFT),
Its grid is connected with described (n+1)th grade of horizontal scanning line, and its drain electrode is believed by described grid
Number point is connected with described condenser network, and its source electrode is connected with described DC low-voltage source.
Array base palte horizontal drive circuit the most according to claim 1, it is characterised in that
Described drop-down holding circuit include the 3rd thin film transistor (TFT), the 4th thin film transistor (TFT), the 5th
Thin film transistor (TFT) and the 6th thin film transistor (TFT)；
Described 3rd thin film transistor (TFT), its grid and the source electrode of the 4th thin film transistor (TFT),
The drain electrode of five thin film transistor (TFT)s is connected with the grid of the 6th thin film transistor (TFT), and connects node
Being n-th grade of drop-down control signal point, its drain electrode is by described signal point and described electricity
Capacitive circuit is connected, and its source electrode is connected with described DC low-voltage source；
Described 4th thin film transistor (TFT), its grid drains with it and is connected, and is connected to described
On DC high voltage source；
Described 5th thin film transistor (TFT), its grid is by described signal point and described electricity
Capacitive circuit is connected, and its source electrode is connected with described DC low-voltage source；
Described 6th thin film transistor (TFT), its source electrode is connected with described DC low-voltage source, its
Drain electrode is connected with described n-th grade of horizontal scanning line.
Array base palte horizontal drive circuit the most according to claim 1, it is characterised in that
Described output circuit includes the 7th thin film transistor (TFT), described 7th thin film transistor (TFT), its leakage
Pole is connected with clock cable, and its source electrode is connected with described n-th grade of horizontal scanning line, its
Grid is connected with described condenser network by described signal point.
Array base palte horizontal drive circuit the most according to claim 4, it is characterised in that
Described condenser network includes that the first electric capacity, one end of described first electric capacity are connected to described grid
On the signaling point of pole, the in the other end and described (n-1)th grade of gate driver on array unit
N-1 level drop-down control signal point is connected.
Array base palte horizontal drive circuit the most according to claim 1, it is characterised in that
Described array base palte horizontal drive circuit also includes zero level gate driver on array unit, uses
In zero level horizontal scanning line is charged, described zero level gate driver on array unit bag
Include: zero level pull-down circuit, the drop-down holding circuit of zero level, zero level output circuit；
Described zero level pull-down circuit, the drop-down holding circuit of zero level, zero level output electricity
Lu Junyu zero level signal point connect, described zero level pull-down circuit also with the first order
Horizontal scanning line, DC low-voltage source are connected；
The described drop-down holding circuit of zero level also with described zero level horizontal scanning line, direct current
High voltage source is connected with DC low-voltage source；
Described zero level output circuit is also connected with described zero level horizontal scanning line, is used for
Receive clock signal, and charge to described zero level horizontal scanning line.
Array base palte horizontal drive circuit the most according to claim 7, it is characterised in that
Described zero level pull-down circuit includes the 8th thin film transistor (TFT), described 8th thin film transistor (TFT),
Its grid is connected with described first order horizontal scanning line, and its drain electrode is connected to zero level grid
On signaling point, its source electrode is connected with described DC low-voltage source.
Array base palte horizontal drive circuit the most according to claim 7, it is characterised in that
The described drop-down holding circuit of zero level include the 9th thin film transistor (TFT), the tenth thin film transistor (TFT),
11st thin film transistor (TFT) and the 12nd thin film transistor (TFT), wherein, described 9th thin film is brilliant
Body pipe, its grid and the source electrode of the tenth thin film transistor (TFT), the leakage of the 11st thin film transistor (TFT)
Pole is connected with the grid of the 12nd thin film transistor (TFT), and connection node is the drop-down control of zero level
Signaling point processed, its drain electrode is connected on zero level signal point, its source electrode with described directly
Stream low-voltage source is connected；Described tenth thin film transistor (TFT), its grid drains with it and is connected,
And be connected on described DC high voltage source；Described 11st thin film transistor (TFT), its grid
Being connected on zero level signal point, its source electrode is connected with described DC low-voltage source；
Described 12nd thin film transistor (TFT), its source electrode is connected with described DC low-voltage source, its leakage
Pole is connected with described zero level horizontal scanning line.
Array base palte horizontal drive circuit the most according to claim 7, its feature exists
The 13rd thin film transistor (TFT) is included in, described zero level output circuit, described 13rd thin
Film transistor, its drain electrode is connected with clock cable, its source electrode and described zero level level
Scan line is connected, and its grid is connected on zero level signal point.
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