CN105900246B - 高电压双扩散mos(dmos)装置及其制造方法 - Google Patents

高电压双扩散mos(dmos)装置及其制造方法 Download PDF

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CN105900246B
CN105900246B CN201580003639.8A CN201580003639A CN105900246B CN 105900246 B CN105900246 B CN 105900246B CN 201580003639 A CN201580003639 A CN 201580003639A CN 105900246 B CN105900246 B CN 105900246B
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floating gate
region
control
dmos
control gate
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CN105900246A (zh
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博米·陈
索努·达里亚纳尼
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Microchip Technology Inc
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Abstract

本发明涉及一种形成集成DMOS晶体管/EEPROM单元的方法，其包含：在衬底上方形成第一掩模；使用所述第一掩模在所述衬底中形成漂移植入物以对准所述漂移植入物；同时在所述漂移植入物上方形成第一浮动栅极及与所述漂移植入物隔开的第二浮动栅极；形成覆盖所述第二浮动栅极且覆盖所述第一浮动栅极的部分的第二掩模；使用所述第一浮动栅极的边缘在所述衬底中形成基极植入物，以使所述基极植入区域自对准；且同时在所述第一浮动栅极上方形成第一控制栅极且在所述第二浮动栅极上方形成第二控制栅极。所述第一浮动栅极、第一控制栅极、漂移植入物及基极植入物形成所述DMOS晶体管的组件，且所述第二浮动栅极及第二控制栅极形成所述EEPROM单元的组件。

Description

高电压双扩散MOS(DMOS)装置及其制造方法
技术领域
本发明涉及一种高压双扩散MOS装置(HV DMOS)及其制造方法。本发明还涉及一种用于产生集成EEPROM单元及HV DMOS以用于高压应用(例如，电动机控制、照明、开关等等)的工艺流程。
背景技术
EEPROM为一类非易失性半导体存储器，其中可将信息电编程到每一存储器元件或位单元中且从每一存储器元件或位单元擦除信息。EEPROM的每一位单元包括两个金属氧化物半导体场效应晶体管(MOSFET)。所述MOSFET中的一者具有两个栅极且用于存储位信息，且另一MOSFET用于选择位单元。EEPROM通常被实现为浮动栅极晶体管的阵列。
典型EEPROM位单元包含：浮动栅极，其布置于形成于硅衬底中的源极与漏极区域之间；及控制栅极，其控制所述浮动栅极的充电，所述浮动栅极经布置(隔离)以保持电荷。在浮动栅极上无电荷的情况下，晶体管正常作用，且控制栅极上的脉冲引起电流流动。当被充电时，浮动栅极阻止控制栅极作用，且电流不流动。通过将源极及漏极端子接地且在通过氧化物到浮动栅极的控制栅极隧道上施加足够电压来完成充电。从另一晶体管通入的反向电压通过引起电荷消散到衬底中而清除电荷。
一些EEPROM设计在P型阱衬底上提供N沟道单元。其它设计在N型阱上提供P沟道单元，N型阱自身驻留于P型衬底中，例如第5,986,931号及第5,790,455号美国专利，EP2339585A1及EP2267775A2中所揭示，所述申请案的全文以引用方式并入本文中。
双扩散金属氧化物半导体(DMOS)为适用于高压应用的常见晶体管。因为扩散过程涉及产生N型掺杂区域及P型掺杂区域两者，所以DMOS被称为“双扩散”。与许多其它晶体管类型相比较，DMOS晶体管通常提供较高击穿电压及较低接通状态电阻。一些DMOS结构在源极与漏极区域之间界定横向沟道，其中所述沟道定位于栅极(例如，浮动栅极)下方。通常通过包含沟道尺寸及掺杂特性的参数来确定此类DMOS单元的性能特性(例如击穿电压及接通状态电阻)。
发明内容
根据一个实施例，双扩散金属氧化物半导体(DMOS)装置可包含：衬底；基极植入区域，其形成于所述衬底中；源极区域，其形成于所述基极植入物中；漏极区域，其形成于所述衬底中；浮动栅极，其形成于所述衬底上方；控制栅极，其在所述基极植入区域上方延伸；浮动栅极电极，其电耦合到所述浮动栅极；及控制电子器件，其经配置以控制经由所述浮动栅极电极施加到所述浮动栅极的电压，借此控制所述DMOS装置的击穿电压及源极-漏极电阻。
根据另一实施例，一种同时形成DMOS晶体管及EEPROM单元的方法可包含：在衬底上方形成第一掩模；使用所述第一掩模在所述衬底中形成漂移植入区域以对准所述漂移植入区域；同时在所述衬底中的所述漂移植入区域上方形成第一浮动栅极及在所述衬底上方与所述漂移植入区域隔开的位置处形成第二浮动栅极；形成覆盖所述第二浮动栅极且覆盖所述第一浮动栅极的部分的第二掩模；使用所述第一浮动栅极的边缘在所述衬底中形成基极植入区域以自对准所述基极植入区域；且同时在所述第一浮动栅极上方形成第一控制栅极且在所述第二浮动栅极上方形成第二控制栅极，其中所述第一浮动栅极、第一控制栅极、漂移植入区域及基极植入区域形成所述DMOS晶体管的组件，且其中所述第二浮动栅极及第二控制栅极形成所述EEPROM单元的组件。
根据另一实施例，提供一种控制DMOS晶体管的方法，所述DMOS晶体管包含：基极植入区域，其形成于衬底中；源极区域，其形成于所述基极植入物中；漏极区域，其形成于所述衬底中；浮动栅极；控制栅极，其在所述基极植入区域上方延伸；控制栅极电极，其电耦合到所述控制栅极；及浮动栅极电极，其电耦合到所述浮动栅极。所述方法包含经由所述浮动栅极电极来施加电压到所述浮动栅极，借此影响所述DMOS装置的击穿电压及源极-漏极电阻。
附图说明
下文参考图式论述实例实施例，其中：
图1到8说明根据一个实施例的用于形成包含集成高压(HV)DMOS晶体管/EEPROM单元的装置的实例工艺。
具体实施方式
图1到8说明用于形成包含集成高压HV DMOS晶体管/EEPROM单元的装置的实例工艺。在所说明的实例中，HV DMOS晶体管及EEPROM单元经形成为n型装置。然而，根据下文所揭示的工艺，通过切换整个工艺中的掺杂物，HV DMOS晶体管及EEPROM单元可替代地被形成为p型装置。
在一些实施例中，所说明的集成n型HV DMOS晶体管及n型EEPROM单元被形成为较大的半导体装置阵列的部分，所述半导体装置包含(a)多个集成n型HV DMOS晶体管及n型EEPROM单元及(b)多个集成p型HV DMOS晶体管及p型EEPROM单元两者。因此，为制造此阵列，可在切换n型/p型掺杂的条件下重复下文所论述的用于产生n型HV DMOS晶体管及n型EEPROM单元的工艺步骤，以产生所述阵列的p型HV DMOS晶体管及p型EEPROM单元，使得可通过单一工艺流程制造所述阵列。
如图1中所展示，可由任何合适材料(例如，硅、GaAs、InP等等)在半导体衬底10中形成装置。首先，使用任何合适技术在衬底10中形成高压(HV)p型阱12A及12B。HV p型阱12A被提供给DMOS晶体管，而p型阱12B则被提供给EEPROM单元，如下文所论述。作为参考，以14指示正形成的DMOS晶体管的区域且以16指示正形成的EEPROM单元的区域。如所展示，HV p型阱12A及12B可通过衬底10的区域彼此隔开。
接着，使用任何合适技术在所述衬底中形成一对隔离区域18A及18B。举例来说，隔离区域18A及18B可经形成为氧化物或任何其它合适隔离材料的浅沟槽隔离(STI)区域。如下文将展示，隔离区域18A形成于HV DMOS晶体管的后续形成的基极植入物与漏极区域之间的位置处，而隔离区域18B形成于DMOS晶体管的后续形成的漏极区域与EEPROM单元的后续形成的源极区域之间。接着，可在EEPROM单元区域上方形成光掩模20且在HV p型阱14A中形成由光掩模20对准的n型漂移植入区域22。接着，可移除光掩模20。
在一些实施例中，也可在切换n型/p型掺杂的条件下重复上文关于图1所论述的步骤，以产生集成阵列的p型HV DMOS晶体管EEPROM单元，如上文所论述。因此，对应于光掩模20的另一光掩模(未展示)可用于定位正形成于阵列中的p型DMOS晶体管的p型漂移植入区域。
接着，如图2中所展示，可同时形成HV DMOS浮动栅极结构30A及EEPROM浮动栅极结构30B，其中浮动栅极结构30A为HV DMOS晶体管的组件，且浮动栅极结构30B为EEPROM单元的组件。可以任何合适方式及由任何合适材料形成浮动栅极结构30A及30B。举例来说，可通过产生隧道氧化物层、浮动栅极层及氧化物氮化物层的堆叠且蚀刻所述堆叠以形成所说明的结构30A及30B来形成浮动栅极结构30A及30B，使得DMOS浮动栅极结构30A包括隧道氧化物区域32A、DMOS浮动栅极34A及氧化物氮化物区域36A，而EEPROM浮动栅极结构30B类似地包括隧道氧化物区域32B、EEPROM浮动栅极区域34B及氧化物氮化物区域36B。如所展示，DMOS浮动栅极结构30A可在第一隔离区域18A上方部分延伸，而EEPROM浮动栅极结构30B可经定位成与第二隔离区域18B隔开。可由多晶硅或任何其它合适材料形成浮动栅极34A及34B，其还可被称为“Poly 1”层。
在也涉及产生集成阵列的p型HV DMOS晶体管EEPROM单元的实施例中，也可在切换n型/p型掺杂的条件下重复上文关于图2所论述的步骤，以产生集成阵列的p型HV DMOS晶体管EEPROM单元，如上文所论述。
接着，如图3中所展示，光掩模40可接着形成于包含EEPROM浮动栅极结构30B的EEPROM单元区域16上方，且在HV DMOS区域14的一部分上方延伸，特定来说，在HV DMOS浮动栅极结构30A上方部分延伸。在HV n型漂移植入区域22中形成p型掺杂基极植入物或“p沟道”42，使得p型掺杂基极植入物42与HV DMOS浮动栅极结构30A的边缘44自对准。接着，可移除光掩模40。
在也涉及产生集成阵列的p型HV DMOS晶体管EEPROM单元的实施例中，可在切换n型/p型掺杂的条件下重复上文关于图3所论述的步骤，以产生集成阵列的p型HV DMOS晶体管EEPROM单元，如上文所论述。因此，对应于光掩模40的另一光掩模(未展示)可用于形成每一p型DMOS晶体管的n型掺杂基极植入区域，其中每一n型掺杂基极植入区域与相应浮动栅极结构的边缘自对准。取决于浮动栅极层的厚度，由于此为基极植入物提供自对准掩模，因此在所述植入之后可添加热驱动步骤以产生此基极层42到半导体衬底中的更大深度。
接着，如图4中所展示，氧化物层50可形成于完整结构上方。举例来说，可通过标准沉积及氧化工艺来形成HV 250A氧化物层。氧化物层50可与浮动栅极结构30A及30B的顶部上的氧化物氮化物区域36A及36B作用以界定浮动栅极34A及34B上方的氧化物-氮化物-氧化物(ONO)层。
在也涉及产生集成阵列的p型HV DMOS晶体管EEPROM单元的实施例中，氧化物层50可在n型HV DMOS晶体管EEPROM单元及p型HV DMOS晶体管EEPROM单元上方延伸。
接着，如图5中所展示，可使用任何合适技术(例如，沉积、植入、图案化及蚀刻工艺)及使用任何合适材料分别在HV DMOS浮动栅极34A及EEPROM浮动栅极34B上方同时形成HV DMOS控制栅极54A及EEPROM控制栅极54B。举例来说，可由同一多晶硅层形成控制栅极54A及54B，且其称为形成于相应“Poly 1”浮动栅极34A及34B上方的“Poly 2”结构。在一个实施例中，HV DMOS控制栅极54A仅部分延伸于浮动栅极结构30A的顶部上方，而EEPROM控制栅极54B完全覆盖浮动栅极结构30B的顶部且完全横跨浮动栅极结构30B的顶部而延伸。
接着，针对HV DMOS及EEPROM两者，可以任何合适方式(例如，通过轻掺杂漏极(LDD)掺杂装置的相应位置)植入源极区域及漏极区域。举例来说，对于HV DMOS，n型掺杂LDD源极区域60A可形成于p型掺杂基极植入物42内，且n型掺杂LDD漏极区域62A可形成于隔离区域18A的相反侧上，如所展示。LDD源极区域60A可与HV DMOS控制栅极54A(即，DMOSPoly 2)的边缘66自对准。对于EEPROM，n型掺杂LDD源极及漏极区域60B及62B可形成于EEPROM控制栅极54B(即，EEPROM Poly2)的相反两侧上。
控制栅极的栅极长度或沟道长度经指示为Lch。如所属领域中已知，对于高性能DMOS晶体管，通常希望窄沟道长度。
在也涉及产生集成阵列的p型HV DMOS晶体管EEPROM单元的实施例中，可在切换n型/p型掺杂的条件下重复上文关于图3所论述的步骤，以产生集成阵列的p型HV DMOS晶体管EEPROM单元，如上文所论述。
接着，如图6中所展示，可形成高掺杂n+插塞植入物及导电接触件(电极)。特定来说，将沉积氧化物层67形成于结构上方，且如所展示形成一系列垂直开口68。如所展示，形成垂直开口68，其向下延伸到每一源极及漏极区域，向下延伸到每一控制栅极54A及54B且还向下延伸到HV DMOS浮动栅极结构30A的顶部。接着，通过每一源极及漏极区域60A、62A、60B及62B上方的垂直开口68植入高掺杂n+插塞植入物以形成n+插塞植入物70A、72A、70B及72B。高掺杂n+插塞植入物70A、72A、70B及72B形成每一源极及漏极的低电阻接触件。
接着，用金属(例如，钨)或其它导电材料填充垂直开口68以形成与结构的相应元件接触的一系列电极。特定来说，源极/漏极电极80A、82A、80B及82B接触每一源极及漏极区域60A、62A、60B及62B；控制栅极电极84A及84B分别接触HV DMOS控制栅极54A及EEPROM控制栅极54B；且浮动栅极电极86接触HV DMOS浮动栅极34A。所得经完成的结构被指示为HVDMOS晶体管100及EEPROM单元102。浮动栅极电极86可用于施加电压到HV DMOS浮动栅极34A以用于各种目的，例如，用于控制HV DMOS装置的击穿电压(Vbd)及源极-漏极电阻(RSD)，及/或用于在HV DMOS控制栅极54A与漏极区域62A之间提供法拉第(Faraday)屏蔽，如下文更详细地论述。
图7及8专注于HV DMOS晶体管100且因此并未展示相邻EEPROM单元102。控制电子器件110可连接到源极电极80A、漏极电极82A、控制栅极电极84A及浮动栅极电极86，以将选定电压施加到源极60A、漏极62A、控制栅极54A及浮动栅极34A且按需要控制此类电压。为了控制HV DMOS 100，经由控制栅极电极84A施加电压偏压到控制栅极54A，此在基极植入(沟道)区域42中产生反向区域，此引起电子从源极电极70A流动到漏极电极72A。
图7及8说明两个不同电压偏压方案及所得效果。特定来说，两个方案说明了如何可通过施加选定电压到浮动栅极34A来控制n型漂移区域的特性，例如击穿电压(Vbd)及源极漏极电阻(RSD)或“接通状态电阻”。
在图7中所展示的方案中，浮动栅极34A被接地(经由浮动栅极电极86施加0V)，且从漏极62A到源极60A跨耗尽n型漂移区域发生相对较大的电压降。一般由虚线90指示具有电压降的场。此方案(接地浮动栅极)提供相对较高的击穿电压(Vbd)及相对较高的源极-漏极电阻(RSD)。
在图8中所展示的方案中，控制电子器件110经由浮动栅极电极86施加小的正向电压偏压(+3V)到浮动栅极34A。此在浮动栅极34A下方的衬底的表面处引起n型漂移累积，以92指示。累积区域92降低源极-漏极电阻(RSD)，但也降低跨n型漂移区域的电压降(图8的方案中36V，相较于图7的方案中的48V)且因此降低击穿电压(Vbd)。
在另一方案中，控制电子器件110可施加负向偏压到浮动栅极，此使得n型漂移区域完全耗尽，且借此提供比图7的接地方案更高的Vbd及RSD。
因此，可选择、改变或控制经由浮动栅极电极86施加到浮动栅极34A的电压以提供所要击穿电压(Vbd)及源极-漏极电阻(RSD)。举例来说，可改变浮动栅极上的偏压以在Vbd与RSD之间产生所要折衷。此外，使浮动栅极偏压来控制n型漂移区域特性允许以一个选定尺寸形成HV DMOS装置且接着将HV DMOS装置控制(例如，微调)到所要性能特性，因此减少精确设定装置尺寸的必要或制造具有不同尺寸的HV DMOS装置以实现不同性能特性的需要。
此外，施加固定电势到DMOS浮动栅极34A在控制栅极(Poly 2)54A与漏极区域62A之间提供法拉第屏蔽。在(举例来说)装置用于高频应用中的情况中，此可为尤其有用的。
上文所描述的工艺允许修改用于形成EEPROM单元的现有工艺流程，通过添加两个掩模/植入步骤以形成n型或p型DMOS晶体管或添加四个掩模/植入步骤以形成n型DMOS晶体管及p型DMOS晶体管两者(即，上文参考图1及3所论述的掩模/植入步骤)以形成同时具有EEPROM单元及HV DMOS晶体管两者的集成阵列。
尽管本发明中详细描述所揭示的实施例，但应理解，在不脱离其精神及范围的情况下可作出各种改变、替换及变更。

Claims (8)

1.一种双扩散金属氧化物半导体DMOS晶体管，其包括：
衬底；
基极植入区域，其形成于所述衬底中；
源极区域，其形成于所述基极植入区域中；
漏极区域，其形成于所述衬底中；
浮动栅极，其形成于所述衬底上方；
控制栅极，其在所述基极植入区域上方延伸；
浮动栅极电极，其电耦合到所述浮动栅极，其中所述基极植入区域与所述浮动栅极的边缘自对准；
氧化物层，其在所述浮动栅极及所述控制栅极上方；
高掺杂源极植入物，其通过所述氧化物层中的第一垂直开口植入，其中所述第一垂直开口由导电材料填充以提供接触所述源极区域的源极电极；
高掺杂漏极植入物，其通过所述氧化物层中的第二垂直开口植入，其中所述第二垂直开口由导电材料填充以提供接触所述漏极区域的漏极电极；及
控制电子器件，其经配置以控制经由所述浮动栅极电极施加到所述浮动栅极的电压，借此控制所述DMOS晶体管的击穿电压及源极-漏极电阻。
2.根据权利要求1所述的DMOS晶体管，其中所述源极区域与所述控制栅极的边缘自对准。
3.根据权利要求1所述的DMOS晶体管，其包括介于所述基极植入区域与所述漏极区域之间的在所述衬底中的沟槽隔离区域。
4.根据权利要求1所述的DMOS晶体管，其进一步包括：
控制栅极电极，其电耦合到所述控制栅极；及
其中所述控制电子器件，其经配置以独立于施加到所述浮动栅极的所述电压来控制经由所述控制栅极电极施加到所述控制栅极的电压。
5.根据权利要求1所述的DMOS晶体管，其中：
所述控制栅极的上部分在所述浮动栅极上方延伸；
所述浮动栅极位于所述控制栅极的所述上部分与所述漏极区域之间；且
所述控制电子器件经配置以经由所述浮动栅极电极施加所述电压到所述浮动栅极，从而在所述控制栅极的所述上部分与所述漏极区域之间产生法拉第屏蔽。
6.根据权利要求1所述的DMOS晶体管，其中所述控制栅极仅覆盖所述浮动栅极的部分，且所述浮动栅极电极在未被所述控制栅极覆盖的位置处电耦合到所述浮动栅极。
7.一种控制双扩散金属氧化物半导体DMOS晶体管的方法，所述DMOS晶体管包含：基极植入区域，其形成于衬底中；源极区域，其形成于所述基极植入区域中；漏极区域，其形成于所述衬底中；浮动栅极；控制栅极，其在所述基极植入区域上方延伸；控制栅极电极，其电耦合到所述控制栅极；浮动栅极电极，其电耦合到所述浮动栅极，其中所述基极植入区域与所述浮动栅极的边缘自对准；氧化物层，其在所述浮动栅极及所述控制栅极上方；高掺杂源极植入物，其通过所述氧化物层中的第一垂直开口植入，其中所述第一垂直开口由导电材料填充以提供接触所述源极区域的源极电极；高掺杂漏极植入物，其通过所述氧化物层中的第二垂直开口植入，其中所述第二垂直开口由导电材料填充以提供接触所述漏极区域的漏极电极；所述方法包括：
经由所述浮动栅极电极将电压施加到所述浮动栅极，借此影响所述DMOS晶体管的击穿电压及源极-漏极电阻。
8.根据权利要求7所述的方法，其包括调整经由所述浮动栅极电极施加到所述浮动栅极的所述电压。
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