CN105900080A - 用于经由芯片内和芯片间跳跃总线在片上***之内和之间传送信息的方法和装置 - Google Patents
用于经由芯片内和芯片间跳跃总线在片上***之内和之间传送信息的方法和装置 Download PDFInfo
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- CN105900080A CN105900080A CN201480067472.7A CN201480067472A CN105900080A CN 105900080 A CN105900080 A CN 105900080A CN 201480067472 A CN201480067472 A CN 201480067472A CN 105900080 A CN105900080 A CN 105900080A
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- chip
- adapter
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- bus
- hopping
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1072—Decentralised address translation, e.g. in distributed shared memory systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/52—Multiprotocol routers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/657—Virtual address space management
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computing Systems (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Bus Control (AREA)
- Information Transfer Systems (AREA)
- Multi Processors (AREA)
Abstract
Description
Claims (20)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201361915413P | 2013-12-12 | 2013-12-12 | |
US61/915,413 | 2013-12-12 | ||
US201461954486P | 2014-03-17 | 2014-03-17 | |
US61/954,486 | 2014-03-17 | ||
PCT/US2014/069322 WO2015089058A1 (en) | 2013-12-12 | 2014-12-09 | Method and apparatus for transferring information within and between system-on-chips via intra-chip and inter-chip hopping buses |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105900080A true CN105900080A (zh) | 2016-08-24 |
CN105900080B CN105900080B (zh) | 2019-05-14 |
Family
ID=53371758
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201480067472.7A Active CN105900080B (zh) | 2013-12-12 | 2014-12-09 | 用于经由芯片内和芯片间跳跃总线在片上***之内和之间传送信息的方法和装置 |
Country Status (7)
Country | Link |
---|---|
US (1) | US9535869B2 (zh) |
EP (1) | EP3080708B1 (zh) |
JP (1) | JP6541272B2 (zh) |
KR (1) | KR102280718B1 (zh) |
CN (1) | CN105900080B (zh) |
TW (1) | TWI664532B (zh) |
WO (1) | WO2015089058A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109690511A (zh) * | 2016-08-31 | 2019-04-26 | 株式会社索思未来 | 总线控制电路、半导体集成电路、电路基板、信息处理装置以及总线控制方法 |
CN112740191A (zh) * | 2018-06-08 | 2021-04-30 | Iot耐科特有限公司 | 通信装置 |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9959237B2 (en) | 2013-12-12 | 2018-05-01 | Marvell World Trade Ltd. | Method and apparatus for transferring information within and between system-on-chips via intra-chip and inter-chip hopping buses |
WO2017023678A1 (en) * | 2015-08-03 | 2017-02-09 | Marvell World Trade Ltd. | Systems and methods for implementing topoloby-based identification process in a mochi environment |
US10474597B2 (en) | 2015-08-03 | 2019-11-12 | Marvell World Trade Ltd. | Systems and methods for performing unknown address discovery in a MoChi space |
US9946674B2 (en) * | 2016-04-28 | 2018-04-17 | Infineon Technologies Ag | Scalable multi-core system-on-chip architecture on multiple dice for high end microcontroller |
US10372646B2 (en) * | 2017-06-30 | 2019-08-06 | Western Digital Technologies, Inc. | Programmable adapter between slow peripherals and network on-chip interfaces |
US11114138B2 (en) | 2017-09-15 | 2021-09-07 | Groq, Inc. | Data structures with multiple read ports |
US11360934B1 (en) | 2017-09-15 | 2022-06-14 | Groq, Inc. | Tensor streaming processor architecture |
US11243880B1 (en) | 2017-09-15 | 2022-02-08 | Groq, Inc. | Processor architecture |
US11868804B1 (en) | 2019-11-18 | 2024-01-09 | Groq, Inc. | Processor instruction dispatch configuration |
US11170307B1 (en) | 2017-09-21 | 2021-11-09 | Groq, Inc. | Predictive model compiler for generating a statically scheduled binary with known resource constraints |
US11789883B2 (en) * | 2018-08-14 | 2023-10-17 | Intel Corporation | Inter-die communication of programmable logic devices |
US11301546B2 (en) | 2018-11-19 | 2022-04-12 | Groq, Inc. | Spatial locality transform of matrices |
US11115147B2 (en) * | 2019-01-09 | 2021-09-07 | Groq, Inc. | Multichip fault management |
CN112084131A (zh) * | 2020-09-11 | 2020-12-15 | 深圳比特微电子科技有限公司 | 用于数字货币的计算装置和计算*** |
CN112540949B (zh) * | 2020-12-17 | 2024-07-12 | 北京航天测控技术有限公司 | 一种数据传输*** |
Citations (3)
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US20040044806A1 (en) * | 2002-05-15 | 2004-03-04 | Moll Laurent R. | Addressing scheme supporting variable local addressing and variable global addressing |
US20100269123A1 (en) * | 2009-04-21 | 2010-10-21 | International Business Machines Corporation | Performance Event Triggering Through Direct Interthread Communication On a Network On Chip |
CN102035723A (zh) * | 2009-09-28 | 2011-04-27 | 清华大学 | 一种片上网络路由及实现方法 |
Family Cites Families (8)
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TWI234943B (en) * | 2002-08-14 | 2005-06-21 | Intel Corp | Method and apparatus for mitigating radio frequency interference between transceiver systems |
US7793024B2 (en) * | 2006-06-20 | 2010-09-07 | Nvidia Corporation | Method for utilizing a PCI-Express bus to communicate between system chips |
US7936809B2 (en) * | 2006-07-11 | 2011-05-03 | Altera Corporation | Economical, scalable transceiver jitter test |
WO2008018004A2 (en) * | 2006-08-08 | 2008-02-14 | Koninklijke Philips Electronics N.V. | Electronic device and method for synchronizing a communication |
US20090109996A1 (en) | 2007-10-29 | 2009-04-30 | Hoover Russell D | Network on Chip |
US9015446B2 (en) * | 2008-12-10 | 2015-04-21 | Nvidia Corporation | Chipset support for non-uniform memory access among heterogeneous processing units |
US20100312934A1 (en) * | 2009-06-05 | 2010-12-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and Method for Multi-Protocol Bus Communications |
US20150012679A1 (en) * | 2013-07-03 | 2015-01-08 | Iii Holdings 2, Llc | Implementing remote transaction functionalities between data processing nodes of a switched interconnect fabric |
-
2014
- 2014-12-09 CN CN201480067472.7A patent/CN105900080B/zh active Active
- 2014-12-09 WO PCT/US2014/069322 patent/WO2015089058A1/en active Application Filing
- 2014-12-09 KR KR1020167018512A patent/KR102280718B1/ko active IP Right Grant
- 2014-12-09 JP JP2016531042A patent/JP6541272B2/ja active Active
- 2014-12-09 EP EP14821028.9A patent/EP3080708B1/en active Active
- 2014-12-12 TW TW103143514A patent/TWI664532B/zh active
-
2015
- 2015-05-13 US US14/711,103 patent/US9535869B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040044806A1 (en) * | 2002-05-15 | 2004-03-04 | Moll Laurent R. | Addressing scheme supporting variable local addressing and variable global addressing |
US20100269123A1 (en) * | 2009-04-21 | 2010-10-21 | International Business Machines Corporation | Performance Event Triggering Through Direct Interthread Communication On a Network On Chip |
CN102035723A (zh) * | 2009-09-28 | 2011-04-27 | 清华大学 | 一种片上网络路由及实现方法 |
Non-Patent Citations (2)
Title |
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KANGMING LEE, ET AL: "《Low-power network-on-chip for high-performance SoC design》", 《IEEE TRANSACTIONS ON VERY LARGE SCALE INTERATION (VLSI) SYSTEMSS》 * |
MIKKEL BYSTRUP STENSGAARD,ET AL: "《ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology》", 《SECOND ACM/IEEE INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS 2008)》 * |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109690511A (zh) * | 2016-08-31 | 2019-04-26 | 株式会社索思未来 | 总线控制电路、半导体集成电路、电路基板、信息处理装置以及总线控制方法 |
CN109690511B (zh) * | 2016-08-31 | 2023-05-02 | 株式会社索思未来 | 总线控制电路、半导体集成电路、电路基板、信息处理装置以及总线控制方法 |
CN112740191A (zh) * | 2018-06-08 | 2021-04-30 | Iot耐科特有限公司 | 通信装置 |
CN112740191B (zh) * | 2018-06-08 | 2023-03-28 | Iot耐科特有限公司 | 通信装置 |
Also Published As
Publication number | Publication date |
---|---|
KR102280718B1 (ko) | 2021-07-22 |
WO2015089058A1 (en) | 2015-06-18 |
TWI664532B (zh) | 2019-07-01 |
JP6541272B2 (ja) | 2019-07-10 |
JP2017504862A (ja) | 2017-02-09 |
TW201531858A (zh) | 2015-08-16 |
US20150248371A1 (en) | 2015-09-03 |
EP3080708B1 (en) | 2020-02-05 |
CN105900080B (zh) | 2019-05-14 |
EP3080708A1 (en) | 2016-10-19 |
KR20160096690A (ko) | 2016-08-16 |
US9535869B2 (en) | 2017-01-03 |
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Effective date of registration: 20200423 Address after: Singapore City Patentee after: Marvell Asia Pte. Ltd. Address before: Ford street, Grand Cayman, Cayman Islands Patentee before: Kaiwei international Co. Effective date of registration: 20200423 Address after: Ford street, Grand Cayman, Cayman Islands Patentee after: Kaiwei international Co. Address before: Hamilton, Bermuda Patentee before: Marvell International Ltd. Effective date of registration: 20200423 Address after: Hamilton, Bermuda Patentee after: Marvell International Ltd. Address before: Babado J San Mega Le Patentee before: MARVELL WORLD TRADE Ltd. |