CN105869989B - The preparation method and power device of power device - Google Patents
The preparation method and power device of power device Download PDFInfo
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- CN105869989B CN105869989B CN201510031227.7A CN201510031227A CN105869989B CN 105869989 B CN105869989 B CN 105869989B CN 201510031227 A CN201510031227 A CN 201510031227A CN 105869989 B CN105869989 B CN 105869989B
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Abstract
The present invention provides a kind of preparation method of power device and its a kind of power devices, wherein, the preparation method of power device, it include: the progress p-type injection on the substrate for sequentially forming the first N-type epitaxy layer, the second N-type epitaxy layer and third N-type epitaxy layer, gate oxide and multiple silicon gate structures, to form the area PXing Ti, the bottom in the area PXing Ti contacts second N-type epitaxy layer, wherein the region between adjacent silicon gate structure in the multiple silicon gate structure is main line；Patterned N-type injection is carried out on the substrate for forming the area PXing Ti to form source region；Dielectric layer is formed on the substrate for forming the source region；Processing successively is patterned to the dielectric layer on the substrate for forming the dielectric layer, to expose the third N-type epitaxy layer below the main line；Metal connection is formed to complete the preparation of the power device.According to the technical solution of the present invention, the breakdown voltage of power device is effectively increased.
Description
Technical field
The present invention relates to technical field of semiconductors, preparation method and a kind of function in particular to a kind of power device
Rate device.
Background technique
In related semiconductor technology, vertical bilateral diffusion field-effect tranisistor (Vertical Double-Diffused
Metal Oxide Semiconductor, abbreviation VDMOS) it is a kind of power device that purposes is very extensive, the power device
It is vertically disposed for draining between source electrode, so that electric current is circulated in power device internal vertical, current density is increased, to change
It has been apt to rated current.The most important performance parameter of vertical bilateral diffusion field-effect tranisistor is exactly working loss, and working loss can
To be divided into conduction loss, cut-off loss and switching loss three parts.
The switching loss size of power device is determined that parasitic capacitance can be divided into gate-source capacitance, grid by parasitic capacitance size
Drain capacitance and source drain capacitance three parts.Wherein, gate leakage capacitance influences the switching loss of device maximum, and gate leakage capacitance can divide
For oxidation layer capacitance and depletion-layer capacitance two parts, oxidation layer capacitance is influenced by gate oxide thickness, and depletion-layer capacitance is by technique and device
Part structure influences.Gate leakage capacitance directly influences input capacitance and the switch time of device, and input capacitance increases, to make device
Switch time extends, and then increases switching loss.
Therefore, how design power device production method and structure to improve its breakdown voltage as skill urgently to be resolved
Art problem.
Summary of the invention
The present invention is based at least one above-mentioned technical problem, propose a kind of new power device preparation method and
A kind of power device.
In view of this, an aspect of of the present present invention proposes a kind of preparation method of power device, comprising: sequentially forming
P is carried out on the substrate of one N-type epitaxy layer, the second N-type epitaxy layer and third N-type epitaxy layer, gate oxide and multiple silicon gate structures
Type injection, to form the area PXing Ti, the bottom in the area PXing Ti contacts second N-type epitaxy layer, wherein the multiple Si-gate
The region between adjacent silicon gate structure in structure is main line；Figure is carried out on the substrate for forming the area PXing Ti
The N-type of change is injected to form source region；Dielectric layer is formed on the substrate for forming the source region；Forming the dielectric layer
Processing successively is patterned to the dielectric layer on the substrate, to expose the third N-type below the main line
Epitaxial layer；Metal connection is formed to complete the preparation of the power device.
In the technical scheme, by using the substrate of three layers of epitaxial structure, increase outside substrate epitaxial layer and bottom
Prolong the impurity concentration of layer, reduce the impurity concentration of extension middle layer, keeps epitaxial layer overall thickness and doping total concentration constant, effectively
Improve the breakdown voltage of power device.
Specifically, it is less than single layer epitaxial layer by using multiple epitaxial layer, and the doping concentration of the first epitaxial layer of setting
Doping concentration, the variation of the electric field strength of power device is more uniform, therefore, improves function while reducing conducting resistance
The breakdown voltage of rate device.
In above-mentioned technical proposal, it is preferable that before forming the area PXing Ti, comprising the following specific steps on the substrate successively
Form the first N-type epitaxy layer, the second N-type epitaxy layer and third N-type epitaxy layer；The silica is formed on said epitaxial layer there
Layer；Processing is patterned to form the main line to the silicon oxide layer；Remove the oxidation Jing Guo graphical treatment
Silicon layer；The gate oxide is formed on the substrate for removing the silicon oxide layer；Polycrystalline is formed on the gate oxide
Silicon layer；Processing is patterned to the polysilicon, to form the multiple silicon gate structure.
In above-mentioned technical proposal, it is preferable that the doping concentration of first N-type epitaxy layer is greater than the second N-type extension
The doping concentration of layer.
In above-mentioned technical proposal, it is preferable that the doping concentration of the third N-type epitaxy layer is greater than the second N-type extension
The doping concentration of layer.
In above-mentioned technical proposal, it is preferable that the thickness of first N-type epitaxy layer is less than second N-type epitaxy layer
Thickness.
In above-mentioned technical proposal, it is preferable that the thickness of the third N-type epitaxy layer is less than second N-type epitaxy layer
Thickness.
In above-mentioned technical proposal, it is preferable that the thickness of first N-type epitaxy layer is less than the third N-type epitaxy layer
Thickness.
In above-mentioned technical proposal, it is preferable that the doping concentration of the doping concentration of the first N-type epitaxy layer, the second N-type epitaxy layer
The doping concentration of the substrate is above with the doping concentration of third N-type epitaxy layer.
In above-mentioned technical proposal, it is preferable that the technique of the graphical treatment is dry etch process and/or wet etching
Technique.
The second aspect of the present invention proposes a kind of power device, and the power device is used as appointed in above-mentioned technical proposal
The preparation method of power device described in one is prepared.
Increase substrate epitaxial layer and bottom by using the substrate of three layers of epitaxial structure by above technical scheme
The impurity concentration of epitaxial layer reduces the impurity concentration of extension middle layer, keeps epitaxial layer overall thickness and doping total concentration constant, has
Effect improves the breakdown voltage of power device.
Detailed description of the invention
Fig. 1 shows the schematic flow diagram of the preparation method of power device according to an embodiment of the invention；
Fig. 2 shows the schematic flow diagrams of the preparation method of power device according to another embodiment of the invention；
Fig. 3 shows the diagrammatic cross-section of the substrate of the power device of embodiment according to the present invention；
Fig. 4 shows the diagrammatic cross-section of the power device of embodiment according to the present invention；
Fig. 5 shows the electrology characteristic figure of power device according to the present invention.
Specific embodiment
To better understand the objects, features and advantages of the present invention, with reference to the accompanying drawing and specific real
Applying mode, the present invention is further described in detail.It should be noted that in the absence of conflict, the implementation of the application
Feature in example and embodiment can be combined with each other.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, still, the present invention may be used also
To be implemented using other than the one described here other modes, therefore, protection scope of the present invention is not by described below
Specific embodiment limitation.
Fig. 1 shows the schematic flow diagram of the preparation method of power device according to an embodiment of the invention.
As shown in Figure 1, a kind of preparation method of power device of embodiment according to the present invention, comprising: step 102,
Sequentially form the base of the first N-type epitaxy layer, the second N-type epitaxy layer and third N-type epitaxy layer, gate oxide and multiple silicon gate structures
On piece carries out p-type injection, and to form the area PXing Ti, the bottom in the area PXing Ti contacts second N-type epitaxy layer, wherein institute
Stating the region between the adjacent silicon gate structure in multiple silicon gate structures is main line；Step 104, the area PXing Ti is being formed
Patterned N-type injection is carried out on the substrate to form source region；Step 106, the shape on the substrate for forming the source region
At dielectric layer；Step 108, processing successively is patterned to the dielectric layer on the substrate for forming the dielectric layer,
To expose the third N-type epitaxy layer below the main line；Step 110, metal connection is formed to complete the function
The preparation of rate device.
In the technical scheme, by using the substrate of three layers of epitaxial structure, increase outside substrate epitaxial layer and bottom
Prolong the impurity concentration of layer, reduce the impurity concentration of extension middle layer, keeps epitaxial layer overall thickness and doping total concentration constant, effectively
Improve the breakdown voltage of power device.
Specifically, it is less than single layer epitaxial layer by using multiple epitaxial layer, and the doping concentration of the first epitaxial layer of setting
Doping concentration, the variation of the electric field strength of power device is more uniform, therefore, improves function while reducing conducting resistance
The breakdown voltage of rate device.
In above-mentioned technical proposal, it is preferable that before forming the area PXing Ti, comprising the following specific steps on the substrate successively
Form the first N-type epitaxy layer, the second N-type epitaxy layer and third N-type epitaxy layer；The silica is formed on said epitaxial layer there
Layer；Processing is patterned to form the main line to the silicon oxide layer；Remove the oxidation Jing Guo graphical treatment
Silicon layer；The gate oxide is formed on the substrate for removing the silicon oxide layer；Polycrystalline is formed on the gate oxide
Silicon layer；Processing is patterned to the polysilicon, to form the multiple silicon gate structure.
In above-mentioned technical proposal, it is preferable that the doping concentration of first N-type epitaxy layer is greater than the second N-type extension
The doping concentration of layer.
In above-mentioned technical proposal, it is preferable that the doping concentration of the third N-type epitaxy layer is greater than the second N-type extension
The doping concentration of layer.
In above-mentioned technical proposal, it is preferable that the thickness of first N-type epitaxy layer is less than second N-type epitaxy layer
Thickness.
In above-mentioned technical proposal, it is preferable that the thickness of the third N-type epitaxy layer is less than second N-type epitaxy layer
Thickness.
In above-mentioned technical proposal, it is preferable that the thickness of first N-type epitaxy layer is less than the third N-type epitaxy layer
Thickness.
In above-mentioned technical proposal, it is preferable that the doping concentration of the doping concentration of the first N-type epitaxy layer, the second N-type epitaxy layer
The doping concentration of the substrate is above with the doping concentration of third N-type epitaxy layer.
In above-mentioned technical proposal, it is preferable that the technique of the graphical treatment is dry etch process and/or wet etching
Technique.
As shown in Fig. 2, the preparation method of another power device of embodiment according to the present invention, comprising: step 202,
Field oxide is grown, active area is defined；Step 204, etching groove area is defined, etching forms groove；Step 206, growth is sacrificed
Oxide layer removes sacrificial oxide layer, forms gate oxide；Step 208, polysilicon layer, etches polycrystalline silicon layer are prepared；Step 210,
The injection of the area PXing Ti and annealing；Step 212, source region injection zone defines, source region injection, annealing；Step 214, preparation media layer；
Step 216, definition contact bore region, etches, and injects, annealing；Step 218, it metallizes, passivation.
The structure of power device after the preparation method of Fig. 2 to Fig. 4 includes: 1N type substrate, 2 first N-type epitaxy layers,
3 second N-type epitaxy layers, 4 body areas, 5 source regions, 6 grids.
The breakdown voltage distribution of power device after the preparation method of Fig. 2 to Fig. 4 is as shown in Figure 5.
The technical scheme of the present invention has been explained in detail above with reference to the attached drawings, it is contemplated that how the production side of design power device
The technical issues of method and structure are to improve its breakdown voltage.Therefore, the invention proposes a kind of preparation sides of new power device
Method and a kind of power device increase substrate epitaxial layer and bottom epitaxial layer by using the substrate of three layers of epitaxial structure
Impurity concentration reduces the impurity concentration of extension middle layer, keeps epitaxial layer overall thickness and doping total concentration constant, effectively increases
The breakdown voltage of power device.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of preparation method of power device characterized by comprising
Sequentially forming the first N-type epitaxy layer, the second N-type epitaxy layer and third N-type epitaxy layer, gate oxide and multiple Si-gate knots
P-type injection is carried out on the substrate of structure, to form the area PXing Ti, the bottom in the area PXing Ti contacts second N-type epitaxy layer,
In, the region between adjacent silicon gate structure in the multiple silicon gate structure is main line；
Patterned N-type injection is carried out on the substrate for forming the area PXing Ti to form source region；
Dielectric layer is formed on the substrate for forming the source region；
Processing successively is patterned to the dielectric layer on the substrate for forming the dielectric layer, to expose the master
The third N-type epitaxy layer of beneath trenches；
Metal connection is formed to complete the preparation of the power device.
2. the preparation method of power device according to claim 1, which is characterized in that before forming the area PXing Ti, including it is following
Specific steps:
The first N-type epitaxy layer, the second N-type epitaxy layer and third N-type epitaxy layer are sequentially formed on the substrate；
Silicon oxide layer is formed on said epitaxial layer there；
Processing is patterned to form the main line to the silicon oxide layer；
Remove the silicon oxide layer Jing Guo graphical treatment；
The gate oxide is formed on the substrate for removing the silicon oxide layer；
Polysilicon layer is formed on the gate oxide；
Processing is patterned to the polysilicon, to form the multiple silicon gate structure.
3. the preparation method of power device according to claim 2, which is characterized in that first N-type epitaxy layer is mixed
Miscellaneous concentration is greater than the doping concentration of second N-type epitaxy layer.
4. the preparation method of power device according to claim 3, which is characterized in that the third N-type epitaxy layer is mixed
Miscellaneous concentration is greater than the doping concentration of second N-type epitaxy layer.
5. the preparation method of power device according to claim 4, which is characterized in that the thickness of first N-type epitaxy layer
Degree is less than the thickness of second N-type epitaxy layer.
6. the preparation method of power device according to claim 5, which is characterized in that the thickness of the third N-type epitaxy layer
Degree is less than the thickness of second N-type epitaxy layer.
7. the preparation method of power device according to claim 6, which is characterized in that the thickness of first N-type epitaxy layer
Degree is less than the thickness of the third N-type epitaxy layer.
8. the preparation method of power device according to any one of claim 1 to 7, which is characterized in that the first N-type extension
The doping concentration of layer, the doping concentration of the doping concentration of the second N-type epitaxy layer and third N-type epitaxy layer are above the substrate
Doping concentration.
9. the preparation method of power device according to any one of claim 1 to 7, which is characterized in that described graphical
The technique of processing is dry etch process and/or wet-etching technology.
10. a kind of power device, which is characterized in that the power device uses function as claimed in any one of claims 1-9 wherein
The preparation method of rate device is prepared.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6586798B1 (en) * | 1998-12-09 | 2003-07-01 | Stmicroelectronics S.R.L. | High voltage MOS-gated power device |
| CN1729577A (en) * | 2002-12-20 | 2006-02-01 | 克里公司 | Silicon carbide power metal-oxide semiconductor field effect transistors and manufacturing methods |
| CN102709191A (en) * | 2012-06-07 | 2012-10-03 | 无锡市晶源微电子有限公司 | Process for manufacturing series of intermediate-voltage N-type vertical conduction double-diffused metal oxide semiconductor transistors by using composite epitaxy |
| CN103022123A (en) * | 2011-09-21 | 2013-04-03 | 上海华虹Nec电子有限公司 | Super junction semiconductor device and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1591908A (en) * | 2003-08-18 | 2005-03-09 | 谢福淵 | Junction barrier schottky device of low forward flow voltage drop and high reverse blocking voltage |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6586798B1 (en) * | 1998-12-09 | 2003-07-01 | Stmicroelectronics S.R.L. | High voltage MOS-gated power device |
| CN1729577A (en) * | 2002-12-20 | 2006-02-01 | 克里公司 | Silicon carbide power metal-oxide semiconductor field effect transistors and manufacturing methods |
| CN103022123A (en) * | 2011-09-21 | 2013-04-03 | 上海华虹Nec电子有限公司 | Super junction semiconductor device and manufacturing method thereof |
| CN102709191A (en) * | 2012-06-07 | 2012-10-03 | 无锡市晶源微电子有限公司 | Process for manufacturing series of intermediate-voltage N-type vertical conduction double-diffused metal oxide semiconductor transistors by using composite epitaxy |
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Effective date of registration: 20220719 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |
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