Detailed Description
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein is meant to encompass any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present invention. Depending on the context, moreover, the word "if" as used may be interpreted as "at … …" or "when … …" or "in response to a determination".
Referring to fig. 1, the BMC is connected to only one motherboard, and the BMC can only send serial port printing information of one motherboard to the remote console, and the remote console can only see serial port printing information of one motherboard. Moreover, the BMC cannot send serial port printing information of the BMC to the remote console. Moreover, the remote console can only send serial port control information to one mainboard through the BMC.
In order to solve the above problem, an embodiment of the present invention provides a method for transmitting serial port information, where a BMC may manage a motherboard and/or the BMC, send serial port print information of the motherboard and/or serial port print information of the BMC to a remote console, and send serial port control information from the remote console to the motherboard. As shown in fig. 2, the serial port information transmission method may specifically include the following steps:
step 201, the BMC obtains data, where the data includes serial port information and identification information to which the serial port information belongs.
Step 202, the BMC sends the data by using the identification information to which the serial port information belongs.
The serial port information can be serial port printing information of a mainboard and/or a BMC which needs to be sent to the remote control console, and can also be serial port control information from the remote control console.
Aiming at serial port printing information, the process of acquiring data by the BMC specifically comprises the following steps: the method comprises the steps that BMC obtains UART serial port data, wherein the UART serial port data comprises serial port printing information; and the BMC encapsulates the acquired UART serial port data. The process of sending data by using the identification information to which the serial port information belongs by the BMC specifically includes: and the BMC sends the packaged UART serial port data to a remote control console, wherein the packaged UART serial port data comprises serial port printing information and identification information to which the serial port printing information belongs. Therefore, the BMC sends data including the serial port printing information and the identification information to which the serial port printing information belongs to the remote console.
For the serial port control information, the process of acquiring data by the BMC specifically includes: the BMC receives the encapsulated data from the remote control console, decapsulates the encapsulated data, and the decapsulated data includes serial port control information and identification information of a motherboard to which the serial port control information belongs. The process of sending data by using the identification information to which the serial port information belongs by the BMC specifically includes: the BMC sends the serial port control information to the mainboard to which the serial port control information belongs by using the identification information of the mainboard to which the serial port control information belongs.
The following describes the processing of serial port print information and serial port control information in conjunction with a specific application scenario.
As shown in fig. 3, for a processing flow of printing information for a serial port, the process may include:
step 301, the BMC obtains UART serial data, which includes serial printing information. The UART serial port data is the UART serial port data of the mainboard and/or the UART serial port data of the BMC. For example, the UART serial data may be UART serial data of at least two motherboards, or may be UART serial data of BMC, or may be UART serial data of at least one motherboard and UART serial data of BMC.
The process of acquiring the UART serial port data of the motherboard by the BMC may include, but is not limited to, the following cases:
in the first case, as shown in fig. 4, an FPGA (Field Programmable gate array) is disposed between the BMC and the motherboard, that is, the motherboard and the BMC perform data transmission through the FPGA. And the mainboard carries out data transmission with the BMC through a UART bus. In fig. 4, each motherboard corresponds to one LPC bus, that is, each motherboard performs data transmission with the FPGA through its own LPC bus, but the FPGA performs data transmission with the BMC through only one UART bus, so that each motherboard performs data transmission with the BMC through the unique UART bus.
And the first mainboard outputs LPC serial port data to the FPGA through an LPC bus. The FPGA receives LPC serial port data from the first mainboard, converts the LPC serial port data into UART serial port data, and sends the UART serial port data of the first mainboard to the BMC through a UART bus between the BMC and the FPGA. The BMC receives UART serial port data of the first mainboard, which is sent by the FPGA through the UART bus.
In the second case, as shown in fig. 4, an FPGA is disposed between the BMC and the motherboard, that is, the motherboard and the BMC perform data transmission through the FPGA. And the mainboard carries out data transmission with the BMC through a UART bus. In fig. 4, each motherboard corresponds to a UART bus, that is, each motherboard performs data transmission with the FPGA through its own UART bus, but the FPGA performs data transmission with the BMC through only one UART bus, so that each motherboard performs data transmission with the BMC through the unique UART bus.
The first mainboard outputs UART serial port data to the FPGA through the UART bus. The FPGA receives the UART serial port data from the first mainboard, conversion operation of the serial port data is not performed any more, and the UART serial port data of the first mainboard are directly sent to the BMC through the UART bus between the BMC and the FPGA. The BMC receives UART serial port data of the first mainboard, which is sent by the FPGA through the UART bus.
In the third case, as shown in fig. 5, an FPGA is deployed between the BMC and the motherboard, that is, the motherboard and the BMC perform data transmission through the FPGA. And the mainboard performs data transmission with the BMC through a plurality of UART buses. In fig. 5, each motherboard corresponds to one LPC bus, that is, each motherboard performs data transmission with the FPGA through its own LPC bus, and the FPGA performs data transmission with the BMC through a plurality of UART buses, so that each motherboard corresponds to one UART bus and performs data transmission with the BMC through the UART bus corresponding to the motherboard.
When the number of the motherboards is the same as the number of the UART buses between the FPGA and the BMC, each motherboard can correspond to a unique UART bus, for example, the UART bus 1 between the BMC and the FPGA corresponds to the motherboard 1, the UART bus 2 corresponds to the motherboard 2, and the UART bus 3 corresponds to the motherboard 3. Or, some motherboards may correspond to the same UART bus, and the UART bus may be idle, for example, the UART bus 1 between the BMC and the FPGA corresponds to the motherboard 1 and the motherboard 2, the UART bus 2 corresponds to the motherboard 3, and the UART bus 3 is idle. When the number of the motherboards is different from the number of the UART buses between the FPGA and the BMC, each motherboard may correspond to a unique UART bus, for example, assuming that the number of the UART buses is greater than the number of the motherboards, the UART bus 1 between the BMC and the FPGA corresponds to the motherboard 1, the UART bus 2 corresponds to the motherboard 2, and the UART bus 3 corresponds to the motherboard 3, but the UART bus 4 is idle. Or, some motherboards may correspond to the same UART bus, for example, if the number of the UART buses is smaller than that of the motherboards, the UART bus 1 between the BMC and the FPGA corresponds to the motherboard 1 and the motherboard 2, and the UART bus 2 corresponds to the motherboard 3.
Of course, there may be other corresponding manners of the motherboard and the UART bus, which are not described in this embodiment.
And the second mainboard outputs LPC serial port data to the FPGA through an LPC bus. The FPGA receives LPC serial port data from the second mainboard, converts the LPC serial port data into UART serial port data, and sends the UART serial port data of the second mainboard to the BMC through a UART bus corresponding to the second mainboard. And the BMC receives UART serial port data of the second mainboard, which is sent by the FPGA through the UART bus corresponding to the second mainboard.
In the fourth case, as shown in fig. 5, an FPGA is disposed between the BMC and the motherboard, that is, the motherboard and the BMC perform data transmission through the FPGA. And the mainboard performs data transmission with the BMC through a plurality of UART buses. In fig. 5, each motherboard corresponds to a UART bus, that is, each motherboard performs data transmission with the FPGA through its own UART bus, and the FPGA performs data transmission with the BMC through a plurality of UART buses, so that each motherboard corresponds to a UART bus and performs data transmission with the BMC through the UART bus corresponding to the motherboard. For the corresponding manner between the motherboard and the UART bus, reference may be made to case three, which is not described herein again, taking, for example, that the UART bus 1 between the BMC and the FPGA corresponds to the motherboard 1, the UART bus 2 corresponds to the motherboard 2, and the UART bus 3 corresponds to the motherboard 3.
The second mainboard outputs UART serial port data to the FPGA through the UART bus. The FPGA receives the UART serial port data from the second mainboard, conversion operation of the serial port data is not carried out, and the UART serial port data of the second mainboard is sent to the BMC through the UART bus corresponding to the second mainboard. And the BMC receives UART serial port data of the second mainboard, which is sent by the FPGA through the UART bus corresponding to the second mainboard.
In the fifth case, as shown in fig. 6, an FPGA is not disposed between the BMC and the motherboard, that is, the motherboard and the BMC directly perform data transmission through the UART bus, and the motherboard performs data transmission with the BMC through a plurality of UART buses. In fig. 6, each UART bus corresponds to one motherboard. For example, the UART bus 1 corresponds to the motherboard 1, the UART bus 2 corresponds to the motherboard 2, and the UART bus 3 corresponds to the motherboard 3.
And the third mainboard outputs the UART serial port data to the BMC through the UART bus. And the BMC receives UART serial port data sent by the third mainboard through the UART bus corresponding to the third mainboard.
In a sixth case, as shown in fig. 6, an FPGA is not disposed between the BMC and the motherboard, that is, the motherboard and the BMC directly perform data transmission through the LPC bus, and the motherboard performs data transmission through the plurality of LPC buses and the BMC. In fig. 6, each LPC bus corresponds to a motherboard. For example, LPC bus 1 corresponds to motherboard 1, LPC bus 2 corresponds to motherboard 2, and LPC bus 3 corresponds to motherboard 3.
And the third mainboard outputs LPC serial port data to the BMC through the LPC bus. The BMC receives LPC serial port data sent by the third mainboard through an LPC bus corresponding to the third mainboard, converts the LPC serial port data into UART serial port data, and accordingly UART serial port data corresponding to the third mainboard are obtained.
In practical application, a networking mode between the BMC and the motherboard can be flexibly selected, and after a certain networking mode is selected, a corresponding processing mode is adopted for processing. For example, when the BMC supports conversion of LPC serial data into UART serial data and one LPC bus may be deployed between the BMC and each motherboard, a networking mode of case six may be adopted and processing may be performed by case six. For another example, when the BMC does not support conversion of LPC serial data into UART serial data and the motherboard uses an LPC bus, a networking mode of case one or case three may be adopted, and the FPGA may be deployed between the motherboard and the BMC and processed by case one or case three.
For the above cases one to six, the first main board, the second main board, and the third main board are only given as an example for distinguishing different cases. The first main board, the second main board and the third main board can be the same or different. The first main board, the second main board and the third main board can be one main board or a plurality of main boards. For example, the first motherboard is motherboard 1, motherboard 2, and motherboard 3, the second motherboard is motherboard 1, motherboard 2, and motherboard 3, and the third motherboard is motherboard 1, motherboard 2, and motherboard 3. Therefore, no matter which condition is adopted for processing, the BMC can acquire UART serial port data of the mainboard 1, the mainboard 2 and the mainboard 3.
In view of the above first and second cases, between the FPGA and the BMC, since the plurality of motherboards share one UART bus, the FPGA can only send UART serial port data of one motherboard to the BMC at a time. On this basis, the BMC may send a request message of the UART serial port data of the first motherboard to the FPGA through a Local Bus (Local Bus) so that the FPGA acquires and sends the UART serial port data of the first motherboard, and thus, the BMC may receive the UART serial port data of the first motherboard.
For example, the BMC first sends a request message of the UART serial port data of the motherboard 1 to the FPGA, and receives the UART serial port data of the motherboard 1. And then, the BMC sends a request message of the UART serial port data of the mainboard 2 to the FPGA and receives the UART serial port data of the mainboard 2. And so on.
The above process is a process in which the BMC acquires UART serial port data of the motherboard, and a process in which the BMC acquires the UART serial port data of the BMC, as shown in fig. 7, the UART serial port data output by the BMC is input back to another UART serial port of the BMC, so that the BMC is input back to another UART serial port of the BMC through the UART serial port data output by the UART serial port, thereby enabling the BMC to acquire the UART serial port data of the BMC.
The method of inputting the UART serial port output by the BMC back to another UART serial port of the BMC may include, but is not limited to: and the TX (transmitting end) of the UART serial port is butted with the RX (receiving end) of another UART serial port, and the RX of the UART serial port is butted with the TX of another UART serial port.
In step 301, the BMC may obtain UART serial port data of the motherboard and/or the UART serial port data of the BMC, and in a subsequent process, it is no longer distinguished whether the UART serial port data of the motherboard or the UART serial port data of the BMC is, and is collectively referred to as UART serial port data.
Step 302, the BMC packages the acquired UART serial port data, where the packaged UART serial port data includes serial port printing information and identification information to which the serial port printing information belongs. The packaged UART serial port data comprises identification information of a mainboard or BMC to which serial port printing information belongs.
When the acquired UART serial port data is encapsulated, the acquired UART serial port data can be encapsulated into UDP data, and the UDP data includes serial port printing information (such as serial port printing information of a motherboard) and identification information of the motherboard or BMC to which the serial port printing information belongs.
Step 303, the BMC sends the packaged UART serial data to the remote console, for example, sends the packaged UART serial data (e.g., UDP data) to the remote console through the LAN.
The LPC serial port data, the UART serial port data and the UDP data all carry serial port printing information, and only the data formats carrying the serial port printing information are different.
In the embodiment of the present invention, because the packaged UART serial data carries serial printing information of the motherboard and/or serial printing information of the BMC, the serial printing information needs to be distinguished, that is, the packaged UART serial data carries identification information of the motherboard or the BMC to which the serial printing information belongs. For example, the corresponding relation between the serial port printing information 1 and the mainboard 1, the corresponding relation between the serial port printing information 2 and the mainboard 2, the corresponding relation between the serial port printing information 3 and the BMC, and the like are carried.
In order to acquire identification information of a mainboard to which serial port printing information belongs, for the first case and the second case, because the FPGA sends UART serial port data of each mainboard to the BMC through the same UART bus, the BMC cannot distinguish the UART serial port data of each mainboard based on the UART bus. Therefore, when the FPGA sends the UART serial port data to the BMC, the identification information of the mainboard to which the serial port printing information belongs can be added into the UART serial port data, and therefore the BMC can obtain the identification information of the mainboard to which the serial port printing information belongs from the UART serial port data after receiving the UART serial port data.
Aiming at the situations from the third situation to the sixth situation, because the UART serial port data of each mainboard is sent to the BMC through different UART buses, and each UART bus corresponds to a unique mainboard, the BMC can distinguish the UART serial port data of each mainboard based on the UART buses. Based on this, after receiving the UART serial port data through a certain UART bus, the BMC can acquire that the motherboard to which the serial port printing information belongs is the motherboard corresponding to the UART bus, and then acquire the identification information of the motherboard.
Certainly, in the third to sixth cases, when the FPGA or the motherboard sends the UART serial port data to the BMC, the FPGA or the motherboard may also add the identification information of the motherboard to which the serial port printing information belongs in the UART serial port data, so that the BMC can obtain the identification information of the motherboard to which the serial port printing information belongs from the UART serial port data after receiving the UART serial port data.
The BMC may encapsulate the acquired UART serial data into UDP data according to an IPMI (Intelligent Platform Management interface specification) protocol. Based on the current IPMI protocol, the BMC only encapsulates the acquired information such as the UART serial port data (which carries serial port printing information), the user name and the password to the UDP data, but does not encapsulate the identification information of the motherboard or the BMC to which the serial port printing information belongs.
Based on this, in the embodiment of the present invention, the current IPMI protocol may be modified, so that when the UART serial port data is encapsulated based on the modified IPMI protocol, the obtained information, such as the UART serial port data, the identification information of the motherboard or BMC to which the serial port print information belongs, and the user name password, may be encapsulated in the UDP data. Or, a user-defined protocol may be adopted, and when the UART serial port data is encapsulated based on the user-defined protocol, the obtained information such as the UART serial port data, the identification information of the motherboard or BMC to which the serial port printing information belongs, and the user name and password may be encapsulated into the UDP data.
In the above embodiments of the present invention, the BMC, the FPGA, and the plurality of motherboards may be located in a server (e.g., a micro server or an ARM server), such as a server based on an Intel X86 architecture.
Based on the technical scheme, in the embodiment of the invention, the BMC can manage a plurality of mainboards, acquire the serial port printing information of the mainboards and send the serial port printing information of the mainboards to the remote console, so that maintenance personnel can check the serial port printing information of the mainboards on the remote console at the same time, and the maintenance personnel can analyze and locate problems conveniently. For example, to the problem that just can appear of certain a plurality of mainboards simultaneous boot, based on the serial ports printing information of a mainboard, maintainer can't analyze and the location problem, but, if maintainer can look over the serial ports printing information of a plurality of mainboards simultaneously, just can analyze and the location problem to can provide help for solving this problem. In addition, the BMC can also send the serial port printing information of the BMC to a remote control console, so that maintenance personnel can check the serial port printing information of the BMC on the remote control console, and the maintenance personnel can analyze and locate the problems of the BMC conveniently.
In the embodiment of the present invention, after acquiring the UART serial data (such as the UART serial data of the motherboard and/or the UART serial data of the BMC), the BMC may further analyze serial printing information from the UART serial data, and perform one or more of the following operations on the serial printing information:
and operation I, recording serial port printing information to a storage device, such as an SD card, by the BMC.
Considering that the serial port printing information is important for problem analysis and positioning under the condition that the server has errors, and plays a vital role in storing historical error information, the BMC can record the serial port printing information into the storage device. Therefore, under the condition of BMC fault, serial port printing information can be read from the storage device, and the problem analysis and positioning are greatly facilitated.
And secondly, providing a downloading function of serial port printing information on the page by the BMC.
The downloading function of the serial port printing information is provided on the page, so that maintenance personnel can download the serial port printing information on the management page of the BMC, and then the serial port printing information is utilized to analyze and position the problem.
And thirdly, the BMC sends the serial port printing information to the user equipment.
Considering that the maintainer does not necessarily like to download the serial printing information on the management page of the BMC, based on the serial printing information, the BMC can also package and compress the serial printing information and then send the serial printing information to the user equipment, such as a receiving platform of a user, e.g. a mailbox, a WeChat, a QQ and the like, so that the maintainer can locally obtain the serial printing information from the user equipment and then analyze and locate the problem by using the serial printing information.
The BMC may send the packaged and compressed serial port print information to the user equipment in an SMTP (Simple Mail Transfer Protocol) mode, an SNMP (Simple Network Management Protocol) TRAP (warning message) mode, an FTP (File Transfer Protocol) mode, or the like.
The BMC can perform packing compression according to the time period or the size of serial port printing information.
And fourthly, virtualizing a virtual storage device based on a Universal Serial Bus (USB) interface for the fourth motherboard by the BMC, and storing the Serial port printing information to the virtual storage device, so that the fourth motherboard acquires the Serial port printing information from the virtual storage device through the USB interface.
The fourth motherboard is only to distinguish from the first motherboard, the second motherboard, and the third motherboard, and the fourth motherboard may be any one motherboard in the server.
The virtual storage device is a virtual floppy disk device, a virtual optical drive device, a virtual hard disk device and the like.
In practical application, the BMC may install an operating system for the motherboard, that is, the BMC virtualizes a virtual storage device based on a USB interface for the motherboard, stores an operating system file in the virtual storage device, and the motherboard may read the operating system file in the virtual storage device, and then install the operating system.
On this basis, in the embodiment of the present invention, as shown in fig. 8, the BMC may virtualize a virtual storage device based on a USB interface, and store the serial port print information in the virtual storage device, for example, virtualize a storage device in which the serial port print information is recorded in the first operation as a virtual storage device, so that, because the motherboard has a CPU (Central processing unit) or the like that operates independently, the motherboard can read the serial port print information in the virtual storage device and analyze the location problem by using the serial port print information, thereby avoiding the participation of maintenance personnel and improving the intelligence and reliability of the server. In fig. 8, an SDIO (Secure Digital Input and Output Card) interface is taken as an example for explanation, and in practical applications, the interface may be other types of interfaces. In general, when the storage device is an SD card, the interface may be an SDIO interface, and when the storage device is Nand Flash (non-Flash), the interface may be a Nand interface.
In the embodiment of the invention, after the serial port printing information is analyzed from the UART serial port data, the BMC can also acquire the timestamp information and add the timestamp information to the serial port printing information before the serial port printing information is processed by the first operation, the second operation, the third operation and the fourth operation. In this way, the processes of the first operation, the second operation, the third operation and the fourth operation are all processes of serial port printing information added with timestamp information.
Because the serial port printing information contains the timestamp information, maintenance personnel can position the time period in which the error information is generated, and convenience is brought to accurate positioning of the time in which the error information is generated. In addition, maintenance personnel can locate associations between issues based on the timestamp information, e.g., based on the timestamp information, if issue 1 and issue 2 are generated at the same time, then it can be analyzed that an association exists between issue 1 and issue 2, otherwise, it can be analyzed that an association does not exist between issue 1 and issue 2.
As shown in fig. 9, for the processing flow of the serial port control information, the process may include:
step 901, the BMC receives encapsulated data from the remote console, where the encapsulated data includes serial port control information and identification information of a motherboard to which the serial port control information belongs.
The encapsulated data may be UDP data encapsulated by the remote console.
The serial port control information is used for acquiring RAID (Redundant array of independent disks) information, the number of hard disks, the state of the motherboard, and the like of the motherboard.
For example, when the remote console needs to check the RAID information of the motherboard 1, since the BMC is connected to the plurality of motherboards, in order to enable the BMC to know which motherboard the serial port control information should be sent to, the data sent by the remote console to the BMC includes the serial port control information used for querying the RAID information and the identification information of the motherboard 1, and thus, the BMC knows that the serial port control information should be sent to the motherboard 1.
And step 902, the BMC decapsulates the encapsulated data, wherein the decapsulated data includes serial port control information and identification information of a motherboard to which the serial port control information belongs.
The BMC can unpack the UDP data into UART serial port data, and analyze serial port control information and identification information of a mainboard to which the serial port control information belongs from the unpacked UART serial port data.
Step 903, the BMC sends the serial port control information to the motherboard to which the serial port control information belongs, by using the identification information of the motherboard to which the serial port control information belongs. For example, the BMC sends the serial port control information to the motherboard 1 to which the serial port control information belongs, by using the identification information of the motherboard 1.
The process of sending the serial port control information to the mainboard to which the serial port control information belongs by the BMC using the identification information of the mainboard to which the serial port control information belongs may include, but is not limited to, the following cases:
in case 1, as shown in fig. 4, an FPGA is deployed between the BMC and the motherboards, that is, the plurality of motherboards and the BMC perform data transmission through the FPGA. And a plurality of mainboards carry out data transmission with the BMC through a UART bus. In fig. 4, each motherboard corresponds to one LPC bus, and each motherboard performs data transmission with the FPGA through its own LPC bus, but the FPGA performs data transmission with the BMC through only one UART bus, so that each motherboard performs data transmission with the BMC through the unique UART bus.
The BMC sends the UART serial port data carrying the serial port control information and the identification information of the mainboard to which the serial port control information belongs to the FPGA through the UART bus. The FPGA converts the UART serial port data into LPC serial port data, and sends the LPC serial port data carrying the serial port control information to the mainboard to which the serial port control information belongs by using the identification information of the mainboard to which the serial port control information belongs. The LPC serial port data can only carry serial port control information and can also carry serial port control information and identification information of a mainboard.
In case 2, as shown in fig. 4, an FPGA is deployed between the BMC and the motherboards, that is, the plurality of motherboards and the BMC perform data transmission through the FPGA. And a plurality of mainboards carry out data transmission with the BMC through a UART bus. In fig. 4, each motherboard corresponds to a UART bus, and each motherboard performs data transmission with the FPGA through its own UART bus, but the FPGA performs data transmission with the BMC through only one UART bus, so that each motherboard performs data transmission with the BMC through the unique UART bus.
The BMC sends the UART serial port data carrying the serial port control information and the identification information of the mainboard to which the serial port control information belongs to the FPGA through the UART bus. And the FPGA sends the UART serial port data carrying the serial port control information to the mainboard to which the serial port control information belongs by utilizing the identification information of the mainboard to which the serial port control information belongs. The UART serial port data can only carry serial port control information and also can carry serial port control information and identification information of a mainboard.
In case 3, as shown in fig. 5, an FPGA is deployed between the BMC and the motherboards, that is, the plurality of motherboards and the BMC perform data transmission through the FPGA. And the plurality of mainboards carry out data transmission with the BMC through a plurality of UART buses. In fig. 5, each motherboard corresponds to one LPC bus, that is, each motherboard performs data transmission with the FPGA through its own LPC bus, and the FPGA performs data transmission with the BMC through a plurality of UART buses, so that each motherboard corresponds to one UART bus and performs data transmission with the BMC through the UART bus corresponding to the motherboard. When the number of the motherboards is the same as the number of the UART buses between the FPGA and the BMC, each motherboard can correspond to a unique UART bus, for example, the UART bus 1 between the BMC and the FPGA corresponds to the motherboard 1, the UART bus 2 corresponds to the motherboard 2, and the UART bus 3 corresponds to the motherboard 3. Or, some motherboards may correspond to the same UART bus, and the UART bus may be idle, for example, the UART bus 1 between the BMC and the FPGA corresponds to the motherboard 1 and the motherboard 2, the UART bus 2 corresponds to the motherboard 3, and the UART bus 3 is idle. When the number of the motherboards is different from the number of the UART buses between the FPGA and the BMC, each motherboard may correspond to a unique UART bus, for example, assuming that the number of the UART buses is greater than the number of the motherboards, the UART bus 1 between the BMC and the FPGA corresponds to the motherboard 1, the UART bus 2 corresponds to the motherboard 2, and the UART bus 3 corresponds to the motherboard 3, but the UART bus 4 is idle. Or, some motherboards may correspond to the same UART bus, for example, if the number of the UART buses is smaller than that of the motherboards, the UART bus 1 between the BMC and the FPGA corresponds to the motherboard 1 and the motherboard 2, and the UART bus 2 corresponds to the motherboard 3. Of course, there may be other corresponding manners of the motherboard and the UART bus, which are not described in this embodiment.
The BMC determines a UART bus corresponding to the mainboard to which the serial port control information belongs, and sends UART serial port data carrying the serial port control information and identification information of the mainboard to which the serial port control information belongs to the FPGA through the currently determined UART bus. The FPGA converts the UART serial port data into LPC serial port data, and sends the LPC serial port data carrying the serial port control information to the mainboard to which the serial port control information belongs by using the identification information of the mainboard to which the serial port control information belongs. The LPC serial port data can only carry serial port control information and can also carry serial port control information and identification information of a mainboard.
In case 4, as shown in fig. 5, an FPGA is deployed between the BMC and the motherboards, that is, the plurality of motherboards and the BMC perform data transmission through the FPGA. And the plurality of mainboards carry out data transmission with the BMC through a plurality of UART buses. In fig. 5, each motherboard corresponds to a UART bus, that is, each motherboard performs data transmission with the FPGA through its own UART bus, and the FPGA performs data transmission with the BMC through a plurality of UART buses, so that each motherboard corresponds to a UART bus and performs data transmission with the BMC through the UART bus corresponding to the motherboard. For the corresponding manner of the motherboard and the UART bus, reference may be made to case 3, which is not described herein again, and for example, the UART bus 1 between the BMC and the FPGA corresponds to the motherboard 1, the UART bus 2 corresponds to the motherboard 2, and the UART bus 3 corresponds to the motherboard 3.
The BMC determines a UART bus corresponding to the mainboard to which the serial port control information belongs, and sends UART serial port data carrying the serial port control information and identification information of the mainboard to which the serial port control information belongs to the FPGA through the currently determined UART bus. And the FPGA sends the UART serial port data carrying the serial port control information to the mainboard to which the serial port control information belongs by utilizing the identification information of the mainboard to which the serial port control information belongs. The UART serial port data can only carry serial port control information and also can carry serial port control information and identification information of a mainboard.
In case 5, as shown in fig. 6, an FPGA is not disposed between the BMC and the motherboards, that is, the plurality of motherboards and the BMC directly perform data transmission through the UART bus, and the plurality of motherboards perform data transmission with the BMC through the plurality of UART buses. In fig. 6, each UART bus corresponds to one motherboard. For example, the UART bus 1 corresponds to the motherboard 1, the UART bus 2 corresponds to the motherboard 2, and the UART bus 3 corresponds to the motherboard 3.
The BMC determines a UART bus corresponding to the mainboard to which the serial port control information belongs, and sends UART serial port data carrying the serial port control information to the mainboard to which the serial port control information belongs through the currently determined UART bus. The UART serial port data can only carry serial port control information and also can carry serial port control information and identification information of a mainboard.
In case 6, as shown in fig. 6, an FPGA is not disposed between the BMC and the motherboards, that is, the plurality of motherboards and the BMC directly perform data transmission through the LPC bus, and the plurality of motherboards perform data transmission with the BMC through the plurality of LPC buses. In fig. 6, each LPC bus corresponds to a motherboard. For example, LPC bus 1 corresponds to motherboard 1, LPC bus 2 corresponds to motherboard 2, and LPC bus 3 corresponds to motherboard 3.
The BMC determines an LPC bus corresponding to a mainboard to which the serial port control information belongs, converts UART serial port data carrying the serial port control information into LPC serial port data, and sends the LPC serial port data carrying the serial port control information to the mainboard to which the serial port control information belongs through the LPC bus determined at present. The LPC serial port data can only carry serial port control information and also can carry serial port control information and identification information of a mainboard.
For the above cases 1 to 6, in practical applications, a networking mode between the BMC and the motherboard may be flexibly selected, and after a certain networking mode is selected, a corresponding processing mode is adopted for processing. For example, when the BMC supports conversion of LPC serial data into UART serial data and one LPC bus may be deployed between the BMC and each motherboard, the networking mode of case 6 may be adopted and the processing may be performed by using case 6. For another example, when the BMC does not support conversion of LPC serial data into UART serial data and the motherboard uses an LPC bus, the networking mode of case 1 or case 3 may be adopted, and the FPGA may be deployed between the motherboard and the BMC and processed in case 1 or case 3.
Based on the technical scheme, in the embodiment of the invention, the BMC can manage a plurality of mainboards, can receive the serial port control information from the remote console, and can send the serial port control information to the corresponding mainboard based on the identification information of the mainboard to which the serial port control information belongs, so that when the BMC controls the plurality of mainboards, the serial port control information can be sent to the mainboard to control the mainboard.
Based on the same inventive concept as the method, the embodiment of the invention provides a serial port information transmission device, and the serial port information transmission device is applied to the BMC. The serial port information transmission device can be realized by software, or by hardware or a combination of the software and the hardware. Taking a software implementation as an example, as a logical device, the device is formed by reading a corresponding computer program instruction in a nonvolatile memory through a processor of a BMC where the device is located. From a hardware aspect, as shown in fig. 10, for a hardware structure diagram of the BMC where the serial port information transmission device provided by the present invention is located, in addition to the processor and the nonvolatile memory shown in fig. 10, the BMC may further include other hardware, such as a forwarding chip, a network interface, and a memory, which are responsible for processing a packet; from a hardware architecture perspective, the BMC may also be a distributed device, and may include multiple interface cards to facilitate expansion of message processing at the hardware level.
As shown in fig. 11, a structure diagram of a serial port information transmission device provided in the present invention is provided, where the serial port information transmission device specifically includes:
the acquisition module 11 is configured to acquire data, where the data includes serial port information and identification information to which the serial port information belongs;
and the sending module 12 is configured to send the data by using the identification information to which the serial port information belongs.
The acquisition module 11 is specifically configured to acquire UART serial port data in a data acquisition process, where the UART serial port data includes serial port printing information and encapsulates the acquired UART serial port data; the sending module 12 is specifically configured to send the packaged UART serial port data to a remote console in a process of sending the data by using the identification information to which the serial port information belongs; the packaged UART serial port data comprises serial port printing information and identification information to which the serial port printing information belongs.
The UART serial port data acquired by the acquisition module 11 is UART serial port data of a motherboard and/or UART serial port data of a BMC; the UART serial port data encapsulated by the acquisition module 11 includes identification information of a motherboard or BMC to which the serial port printing information belongs.
The obtaining module 11 is specifically configured to, in a process of obtaining UART serial port data of the motherboard,
when the mainboard and the BMC carry out data transmission through the field programmable gate array FPGA,
when the mainboard performs data transmission with the BMC through a UART bus, receiving UART serial port data of a first mainboard, which is sent by the FPGA through the UART bus; the FPGA receives UART serial port data from the first mainboard, or converts low pin count LPC serial port data from the first mainboard into UART serial port data; or the like, or, alternatively,
when the mainboard performs data transmission with the BMC through a plurality of UART buses, receiving UART serial port data of the second mainboard, which is sent by the FPGA through the UART bus corresponding to the second mainboard; the FPGA receives UART serial port data from the second mainboard, or converts LPC serial port data from the second mainboard into UART serial port data; or the like, or, alternatively,
when the mainboard and the BMC carry out data transmission through the UART bus or the LPC bus,
when the mainboard performs data transmission with the BMC through a plurality of UART buses, UART serial port data sent by a third mainboard through the UART bus corresponding to the third mainboard are received; or the like, or, alternatively,
when the mainboard performs data transmission with the BMC through a plurality of LPC buses, LPC serial port data sent by a third mainboard through an LPC bus corresponding to the third mainboard are received, and the LPC serial port data are converted into UART serial port data when the LPC serial port data are received.
The obtaining module 11 is further configured to send a request message of the UART serial port data of the first motherboard to the FPGA through a local bus before receiving the UART serial port data of the first motherboard sent by the FPGA through the UART bus, so that the FPGA obtains the UART serial port data of the first motherboard and sends the UART serial port data of the first motherboard.
The transmission device of the serial port information comprises: the processing module 13 is configured to, after the obtaining module 11 obtains the UART serial port data, parse serial port printing information from the UART serial port data, and perform one or more of the following operations on the serial port printing information: recording the serial port printing information to a storage device; providing a downloading function of the serial port printing information on a page; sending the serial port printing information to user equipment; virtualizing a virtual storage device based on a Universal Serial Bus (USB) interface for a fourth mainboard, and storing the serial port printing information into the virtual storage device, so that the fourth mainboard can acquire the serial port printing information from the virtual storage device through the USB interface.
The processing module 13 is further configured to, after analyzing serial port printing information from the UART serial port data, obtain timestamp information before performing one or more of the following operations on the serial port printing information, and add the timestamp information to the serial port printing information.
The obtaining module 11 is specifically configured to receive encapsulated data from a remote console in a data obtaining process, and decapsulate the encapsulated data, where the decapsulated data includes serial port control information and identification information of a motherboard to which the serial port control information belongs;
the sending module 12 is specifically configured to send the serial port control information to the motherboard to which the serial port control information belongs by using the identification information of the motherboard to which the serial port control information belongs in the process of sending the data by using the identification information to which the serial port information belongs.
The sending module 12 is specifically configured to, in a process of sending the serial port control information to the motherboard to which the serial port control information belongs by using the identification information of the motherboard to which the serial port control information belongs,
when a plurality of mainboards and the BMC carry out data transmission through the field programmable gate array FPGA,
when the plurality of mainboards perform data transmission with the BMC through a UART bus, the UART serial port data carrying the serial port control information and the identification information of the mainboard to which the serial port control information belongs is sent to the FPGA through the UART bus, so that the FPGA sends the UART serial port data carrying the serial port control information to the mainboard to which the serial port control information belongs by using the identification information of the mainboard to which the serial port control information belongs, or sends LPC serial port data carrying the serial port control information to the mainboard to which the serial port control information belongs; or the like, or, alternatively,
when the plurality of mainboards perform data transmission with the BMC through a plurality of UART buses, determining a UART bus corresponding to a mainboard to which the serial port control information belongs, and sending UART serial port data carrying the serial port control information and identification information of the mainboard to which the serial port control information belongs to the FPGA through the currently determined UART bus, so that the FPGA sends the UART serial port data carrying the serial port control information to the mainboard to which the serial port control information belongs by using the identification information of the mainboard to which the serial port control information belongs, or sends LPC serial port data carrying the serial port control information to the mainboard to which the serial port control information belongs; or the like, or, alternatively,
when a plurality of mainboards and the BMC carry out data transmission through the UART bus or the LPC bus,
when the plurality of mainboards perform data transmission with the BMC through a plurality of UART buses, determining a UART bus corresponding to the mainboard to which the serial port control information belongs, and sending UART serial port data carrying the serial port control information to the mainboard to which the serial port control information belongs through the currently determined UART bus; or the like, or, alternatively,
when the plurality of mainboards carry out data transmission with the BMC through the plurality of LPC buses, the LPC bus corresponding to the mainboard to which the serial port control information belongs is determined, and LPC serial port data carrying the serial port control information is sent to the mainboard to which the serial port control information belongs through the LPC bus which is currently determined.
The modules of the device can be integrated into a whole or can be separately deployed. The modules can be combined into one module, and can also be further split into a plurality of sub-modules.
Through the above description of the embodiments, those skilled in the art will clearly understand that the present invention may be implemented by software plus a necessary general hardware platform, and certainly may also be implemented by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute the methods according to the embodiments of the present invention. Those skilled in the art will appreciate that the drawings are merely schematic representations of one preferred embodiment and that the blocks or flow diagrams in the drawings are not necessarily required to practice the present invention.
Those skilled in the art will appreciate that the modules in the devices in the embodiments may be distributed in the devices in the embodiments according to the description of the embodiments, and may be correspondingly changed in one or more devices different from the embodiments. The modules of the above embodiments may be combined into one module, or further split into multiple sub-modules. The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
The above disclosure is only for a few specific embodiments of the present invention, but the present invention is not limited thereto, and any variations that can be made by those skilled in the art are intended to fall within the scope of the present invention.