CN105826373A - LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof - Google Patents
LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof Download PDFInfo
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- CN105826373A CN105826373A CN201510005958.4A CN201510005958A CN105826373A CN 105826373 A CN105826373 A CN 105826373A CN 201510005958 A CN201510005958 A CN 201510005958A CN 105826373 A CN105826373 A CN 105826373A
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Abstract
The invention discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof. According to the invention, an STI structure between a drain terminal and a grid electrode is eliminated, so that the Rdson can be greatly reduced. Meanwhile, a metal layer is prepared between the drain terminal and the grid electrode, and thus the electric leakage field can be effectively adjusted, and BV is effectively improved thereby. The manufacturing method disclosed by the invention can reduce the Rdson while effectively improving the BV, and thus the device performance is greatly improved.
Description
Technical field
The present invention relates to quasiconductor preparation field, specifically, relate to device and the manufacture method thereof of a kind of LDMOS.
Background technology
LDMOS (LaterallyDiffusedMetalOxideSemiconductor, LDMOS) compared with traditional transistor, in terms of crucial device property, as gain, the linearity, switch performance, heat dispersion and in terms of reducing progression etc. advantage it is obvious that simultaneously LDMOS be also easier to compatible with CMOS technology and be widely adopted.
LDMOS possesses following advantage: LDMOS and is able to take the standing-wave ratio higher than bipolar transistor 3 times, can be operated without destroying LDMOS equipment under higher reflection power；LDMOS equipment is compared with bearing the overdriving of input signal and be suitable for launching radiofrequency signal simultaneously.LDMOS gain curve is smoother and allows the amplification of multicarrier radiofrequency signal and distortion less.LDMOS pipe has that one low and unconverted intermodulation level is to saturation region, and unlike bipolar transistor, intermodulation level is high and changes along with the increase of power level.This key property allows ldmos transistor to perform the power higher than bipolar transistor two times, and preferable.It is negative that ldmos transistor has preferable temperature characterisitic temperature coefficient, is therefore possible to prevent the impact of heat dissipation.
In LDMOS device, breakdown voltage (breakdownvoltage, hereinafter referred to as BV) is to weigh a critically important index of its device performance.Currently in order to strengthen the breakdown voltage of conventional LDMOS device, it is usually and uses prolongation open-topped length FX of STI to realize, as shown in Figure 1.But after being to increase length FX of STI, Rdson (conducting resistance) can increase sharply；Meanwhile, the drift region (Drift) of conventional LDMOS needs to be formed overlapping with grid, and this can increase Rdson, limits the switching speed of LDMOS.
Therefore, reduce Rdson while how strengthening BV, endeavour the direction of research for those skilled in the art.
Summary of the invention
The invention provides device architecture and the manufacture method thereof of a kind of LDMOS, while reducing Rdson, also can improve BV, and then greatly improve the overall performance of device.
The technical solution adopted in the present invention is:
A kind of LDMOS device, wherein, described LDMOS device includes a substrate, it is formed with active area in described substrate, described active area includes that body district and drift region, described substrate are provided with grid, and described grid is formed overlapping with described body district and described drift region respectively；
Being positioned in described body district and the side of described grid is provided with source, Qie Gaiti district is provided with contact area away from the side of described grid, and described drift region is provided with drain terminal away from the side of described grid；
Described grid is on the portion of upper surface and sidewall of described drain terminal, and the upper surface of the substrate between described grid and drain terminal is all covered with a SAB layer, and the upper surface of this SAB layer is coated with a metal level；
Metal level between described drain terminal and described grid is interconnected with described source by an electric connection structure.
Above-mentioned LDMOS device, wherein, is formed without sti structure in the substrate between described drain terminal and described grid.
Above-mentioned LDMOS device, wherein, described source is isolated by a sti structure with described contact area.
Above-mentioned LDMOS device, wherein, is provided with a gate oxide, and the sidewall of described grid is coated with side wall between described grid and described substrate.
Above-mentioned LDMOS device, wherein, described SAB layer is oxide layer, and the thickness of this SAB layer is more than the thickness of described gate oxide.
Above-mentioned LDMOS device, wherein, described metal level is the one in Co, Ti or Ni.
Above-mentioned LDMOS device, wherein, the upper surface of described metal level is also covered with one layer of TiN.
Above-mentioned LDMOS device, wherein, the upper surface that described contact area, source, drain terminal and grid expose is formed with layer of metal silicide layer.
Plant the preparation method of LDMOS device, wherein, comprise the steps:
Thering is provided a semiconductor device to be prepared, described semiconductor device includes a substrate, is formed with active area in described substrate, and described active area includes that body district and drift region, described grid are formed overlapping with described body district and described drift region；
Being positioned in described body district and the side of described grid is provided with source, Qie Gaiti district is provided with contact area away from the side of described grid；Described drift region is formed with drain terminal away from the side of described grid, is formed without sti structure in the substrate between described drain terminal and described grid；
Prepare a SAB layer to be covered near the portion of upper surface of described drain terminal and the upper surface of sidewall and the substrate between described grid and drain terminal by described grid；
Deposition layer of metal layer also carries out self-registered technology, in described contact area, the portion of upper surface of source, the upper surface of drain terminal and grid form layer of metal silicide, remove the described metal level of part afterwards, and retain and be positioned at the metal level above described SAB layer；
Metallization medium layer also etches formation contact hole, to expose the metal level between described source and grid and described drain terminal, carries out metal filled completing interconnection technology.
The preparation method of above-mentioned LDMOS device, wherein, is formed without sti structure in the substrate between described drain terminal and described grid.
The preparation method of above-mentioned LDMOS device, wherein, described source is isolated by sti structure with described contact area.
The preparation method of above-mentioned LDMOS device, wherein, described metal level is the one in Co, Ti or Ni.
The preparation method of above-mentioned LDMOS device, wherein, after depositing described metal level, continues at described metal level upper surface one layer of TiN layer of deposition, to avoid described metal layer.
The preparation method of above-mentioned LDMOS device, wherein, is provided with a gate oxide between described grid and described substrate.
The preparation method of above-mentioned LDMOS device, wherein, described SAB layer is oxide layer, and the thickness of this SAB layer is more than the thickness of described gate oxide.
The present invention, by cancelling the sti structure between drain terminal and grid, therefore can greatly reduce Rdson, meanwhile, can form electric capacity, and then the electric field of scalable drain terminal near the metal level of drain terminal with the silicon of drain terminal, thus be conducive to being effectively improved BV；Simultaneously because the metal of source extends to drain terminal, the most also can reach the purpose of regulation drain terminal electric field, also can realize improving the technique effect of BV.Further, owing to the thickness of SAB layer is significantly larger than the thickness of gate oxide, BV is higher, so metal level can be interconnected by contact hole with the metal silicide layer on source 6 surface, and fource0 current potential, more can effectively regulate the electric field of drain terminal.Meanwhile, the metal level in the present invention also can be arranged by flaoting.
Accompanying drawing explanation
The detailed description made non-limiting example with reference to the following drawings by reading, the present invention and feature, profile and advantage will become more apparent upon.The part that labelling instruction identical in whole accompanying drawings is identical.The most deliberately it is drawn to scale accompanying drawing, it is preferred that emphasis is the purport of the present invention is shown.
Fig. 1 is that LDMOS device of the prior art uses increase STI A/F to increase the schematic diagram of BV；
A kind of LDMOS device structural representation that Fig. 2 provides for the present invention；
A kind of flow chart preparing LDMOS device that Fig. 3～7 present invention provide.
Detailed description of the invention
Below in conjunction with the accompanying drawings the detailed description of the invention of the present invention is further described:
The invention provides a kind of LDMOS device, with reference to shown in Fig. 2, specifically include: substrate 1, the present invention selects P-type silicon substrate (P-sub) in this embodiment, but does not limit to this embodiment.On substrate 1, definition has active area, this active area includes body district (Body) 2 and drift region (Drift) 3, on substrate 1, it is provided with grid 9, between this grid 9 and substrate 1, is additionally provided with one layer of gate oxide 10, and these grid 9 both sides are also covered with side wall 8；This grid 8 concurrently forms overlapping with body district 2 and drift region 3.
It is positioned in body district 2 and the side of grid 9 is provided with source (source) 6, and the side of this source 6 is also formed with a LDD doped region 7；Body district 2 is provided with contact area (pickup) 4 away from the side of grid 9；Drift region 3 is provided with drain terminal (drain) 12 away from the side of grid 9.Contact area 4 and source 6 are isolated by the first sti structure 5, and drift region 3 is provided with the second sti structure 13 away from the side of grid 9.Further, it is formed without any sti structure in the substrate 1 between drain terminal 12 and grid 9.
Grid 9 is coated with a SAB layer 14 near the portion of upper surface of drain terminal 12 and the upper surface of sidewall and the substrate between grid 9 and drain terminal 12 1, and the upper surface of this SAB layer 14 is coated with a metal level 15.In an embodiment of the present invention, this SAB layer 14 is oxide layer, and the thickness of this SAB layer is significantly larger than the thickness of gate oxide 10；The material of metal level 15 is Co (cobalt), one in Ti (titanium) or Ni (nickel), and in the present invention, this metal level is preferably Co；Upper surface at this metal level 15 is also covered with one layer of TiN (silicon nitride) layer (diagram is indicated), and this TiN layer and metal level collectively constitute a polymeric layer, and then metal level 15 can be avoided to produce oxidation.
In contact area 4, the upper surface that exposes of source 6, drain terminal 12 and grid 9 be formed with layer of metal silicide layer 16, in order to use, self-registered technology is prepared to be formed this metal silicide layer 16.Metal level 15 between drain terminal 12 and described grid 9 is interconnected with source 6 by an electric connection structure, concrete is: is respectively formed with a contact hole 17 above the metal level 15 between drain terminal 12 and grid 9 and above source 6, and is interconnected by source metal (sourcemetal) structure 18.
Owing to LDMOS device provided by the present invention possesses above structure, by cancelling the sti structure between drain terminal 12 and grid, therefore can greatly reduce Rdson, improve the switching speed of LDMOS；Meanwhile, electric capacity, and then the electric field of scalable drain terminal 12 can be formed near the metal level 15 of drain terminal 12 with the silicon of drain terminal 12, thus be conducive to being effectively improved BV；Simultaneously because the metal of source 6 extends to drain terminal, the most also can reach the purpose of regulation drain terminal 12 electric field, also can realize improving the technique effect of BV.Further, owing to the thickness of SAB oxide layer is significantly larger than the thickness of gate oxide 10, therefore cause BV higher, thus when metal level 15 is interconnected by contact hole with source 6, fource0 current potential, more can effectively regulate the electric field of drain terminal.Metal level 15 in the present invention also can be arranged by floating, chooses whether to give metal level 15 current potential, and then regulation drain terminal electric field the most according to demand.
Present invention also offers a kind of method preparing above-mentioned LDMOS device simultaneously, as shown in figure 3 to figure 7, specifically include following steps:
Step S1: first provide a semiconductor device to be prepared, as it is shown on figure 3, this semiconductor device includes substrate 1, the present invention selects P-type silicon substrate (P-sub) in this embodiment, but does not limit to this embodiment.On substrate 1, definition has active area (activearea), this active area includes body district (Body) 2 and drift region (Drift) 3, grid 9 it is provided with on substrate 1, it is additionally provided with one layer of gate oxide 10 between this grid and substrate 1, and these grid 9 both sides are also covered with side wall 8；This grid 9 concurrently forms overlapping with body district 2 and drift region 3.
It is positioned in body district 2 and the side of grid 9 is provided with source (source) 6, and the side of this source 6 is also formed with a LDD doped region 7, it should be noted that at this, this LDD doped region can carry out choosing whether that carrying out LDD doping is formed according to process requirements, LDD doping can not also be carried out in actual applications and form this LDD doped region, the inventive point of the present invention is had no effect on.Body district 2 is provided with contact area 4 away from the side of grid 9；Drift region 3 is provided with drain terminal 12 away from the side of grid 9.Contact area 4 and source 6 are isolated by the first sti structure 5, and drift region 3 is provided with the second sti structure 13 away from the side of grid 9.Further, it is formed without any sti structure in the substrate 1 between drain terminal 12 and grid 9.Preparing the technical scheme that above structure used and all use the usual technological process of prior art, the most particularly relevant flow process does not repeats them here.
Step S2: prepare a SAB layer 14 and covered near the portion of upper surface of drain terminal 12 and the upper surface of sidewall and the substrate between grid 9 and drain terminal 12 1 by grid 9, forms structure shown in Fig. 4.Concrete step is as follows: 1, the surface of device is covered by first one layer of SAB layer of deposition completely, it is preferred that this SAB layer is oxide layer.When depositing SAB layer, the SAB layer thickness controlling the reaction condition of deposition and then control deposition is needed to be greater than the thickness of gate oxide 10；2, the upper surface at SAB layer coats a layer photoetching glue, is then exposed by a mask plate with exposing patterns, developing process, and then forms patterns of openings in the photoresist；3, then carry out downwards dry etching with remaining photoresist for etch mask, will be located in the SAB layer below photoresist opening and be removed；4, finally remove residue photoresist, and ultimately form structure shown in Fig. 5.
Step S3: deposition layer of metal layer 15 also carries out self-registered technology, in contact area 4, the upper surface that exposes of source 6, drain terminal 12 and grid 9 form metal silicide 16, described metal level after removal is, and retain and be positioned at the metal level above SAB layer.Specifically comprise the following steps that
Step S3-1: the device surface after first deposition layer of metal layer 15 will complete step S2 is completely covered.In the present invention, the material of this metal level is for the one in Co, Ti or Ni, it is further preferred that the material of this metal level is Co (cobalt).Simultaneously, after depositing this metal level 15, also can be at the redeposited one layer of TiN (titanium nitride of metal level 15 upper surface, figure is represented), and then form the polymer of metal level and TiN, the metal level 15 of lower section can be prevented effectively from owing to exposing in atmosphere and then being oxidized easily, as shown in Figure 5.
Step S3-2: carry out short annealing process (RTA) so that the metal level 15 of deposition and the polysilicon that contacts produce reaction, so in contact area 4, the upper surface that exposes of source 6, the upper surface of drain terminal 12 and grid 9 form metal silicide 16.Finally use photoetching and etching technics to remove unnecessary metal level 15 again, and remove remaining photoresist, form structure shown in Fig. 6.It should be noted that at this, during the exposure technology carried out in photoetching in this step, can be selected for step S2 employed in mask plate, owing to remaining metal level 15 is in the top of SAB layer 14, therefore select same mask plate can reduce the design cost of mask plate, and simplify processing step.
Step S4: (indicated in figure) after metallization medium layer, etch this dielectric layer and form contact hole, and then expose the metal level 15 between source 12 and grid 9 and drain terminal 12, each preparation one contact hole 17 above the metal level 15 between grid 9 and drain terminal 12 and above source 6, in contact hole, prepare a source metal (sourcemetal) 18 again after filler metal (such as copper) interconnect, it is achieved source 6 and the electric connection of metal level 15.The structure formed is as shown in Figure 7.
In sum, owing to present invention employs above technical scheme, by cancelling the sti structure between drain terminal and grid, therefore can greatly reduce Rdson, and then improve the switching speed of LDMOS；Simultaneously by preparing a metal level between drain terminal and grid and then can effectively regulate electric leakage field, thus it is effectively improved BV.The present invention is possible not only to improve BV, it is also possible to effectively reduce Rdson, and then General Promotion device performance, and process variations is little simultaneously, realizability is relatively strong, and cost is relatively low.
Above presently preferred embodiments of the present invention is described.It is to be appreciated that the invention is not limited in above-mentioned particular implementation, the equipment and the structure that do not describe in detail the most to the greatest extent are construed as being practiced with the common mode in this area；Any those of ordinary skill in the art, without departing under technical solution of the present invention ambit, technical solution of the present invention is made many possible variations and modification by the method and the technology contents that all may utilize the disclosure above, or it being revised as the Equivalent embodiments of equivalent variations, this has no effect on the flesh and blood of the present invention.Therefore, every content without departing from technical solution of the present invention, the technical spirit of the foundation present invention, to any simple modification made for any of the above embodiments, equivalent variations and modification, all still falls within the range of technical solution of the present invention protection.
Claims (15)
1. a LDMOS device, it is characterised in that described LDMOS device includes a substrate, it is formed with active area in described substrate, described active area includes that body district and drift region, described substrate are provided with grid, and described grid is formed overlapping with described body district and described drift region respectively；
Being positioned in described body district and the side of described grid is provided with source, Qie Gaiti district is provided with contact area away from the side of described grid, and described drift region is provided with drain terminal away from the side of described grid；
Described grid is on the portion of upper surface and sidewall of described drain terminal, and the upper surface of the substrate between described grid and drain terminal is all covered with a SAB layer, and the upper surface of this SAB layer is coated with a metal level；
Metal level between described drain terminal and described grid is interconnected with described source by an electric connection structure.
2. LDMOS device as claimed in claim 1, it is characterised in that be formed without sti structure in the substrate between described drain terminal and described grid.
3. LDMOS device as claimed in claim 1, it is characterised in that described source is isolated by a sti structure with described contact area.
4. LDMOS device as claimed in claim 1, it is characterised in that be provided with a gate oxide between described grid and described substrate, and the sidewall of described grid is coated with side wall.
5. LDMOS device as claimed in claim 4, it is characterised in that described SAB layer is oxide layer, and the thickness of this SAB layer is more than the thickness of described gate oxide.
6. LDMOS device as claimed in claim 1, it is characterised in that described metal level is the one in Co, Ti or Ni.
7. LDMOS device as claimed in claim 1, it is characterised in that the upper surface of described metal level is also covered with one layer of TiN.
8. LDMOS device as claimed in claim 1, it is characterised in that the upper surface that described contact area, source, drain terminal and grid expose is formed with layer of metal silicide layer.
9. the preparation method of a LDMOS device, it is characterised in that comprise the steps:
Thering is provided a semiconductor device to be prepared, described semiconductor device includes a substrate, is formed with active area in described substrate, and described active area includes that body district and drift region, described grid are formed overlapping with described body district and described drift region；
Being positioned in described body district and the side of described grid is provided with source, Qie Gaiti district is provided with contact area away from the side of described grid；Described drift region is formed with drain terminal away from the side of described grid, is formed without sti structure in the substrate between described drain terminal and described grid；
Prepare a SAB layer to be covered near the portion of upper surface of described drain terminal and the upper surface of sidewall and the substrate between described grid and drain terminal by described grid；
Deposition layer of metal layer also carries out self-registered technology, in described contact area, the portion of upper surface of source, the upper surface of drain terminal and grid form layer of metal silicide, remove the described metal level of part afterwards, and retain and be positioned at the metal level above described SAB layer；
Metallization medium layer also etches formation contact hole, to expose the metal level between described source and grid and described drain terminal, carries out metal filled completing interconnection technology.
10. the preparation method of LDMOS device as claimed in claim 9, it is characterised in that be formed without sti structure in the substrate between described drain terminal and described grid.
The preparation method of 11. LDMOS device as claimed in claim 9, it is characterised in that described source is isolated by sti structure with described contact area.
The preparation method of 12. LDMOS device as claimed in claim 9, it is characterised in that described metal level is the one in Co, Ti or Ni.
The preparation method of 13. LDMOS device as claimed in claim 9, it is characterised in that after depositing described metal level, continues at described metal level upper surface one layer of TiN layer of deposition, to avoid described metal layer.
The preparation method of 14. LDMOS device as claimed in claim 9, it is characterised in that be provided with a gate oxide between described grid and described substrate.
The preparation method of 15. LDMOS device as claimed in claim 9, it is characterised in that described SAB layer is oxide layer, and the thickness of this SAB layer is more than the thickness of described gate oxide.
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| CN201510005958.4A CN105826373A (en) | 2015-01-06 | 2015-01-06 | LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof |
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| CN201510005958.4A CN105826373A (en) | 2015-01-06 | 2015-01-06 | LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof |
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| CN110867375A (en) * | 2018-08-28 | 2020-03-06 | 上海先进半导体制造股份有限公司 | LDMOS device and manufacturing method thereof |
| WO2021068647A1 (en) * | 2019-10-08 | 2021-04-15 | 无锡华润上华科技有限公司 | Ldmos device and method for preparation thereof |
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Application publication date: 20160803 |