CN105826231A - Pattern plating method for integrating two types of sheet resistance film circuits on same plane of dielectric substrate - Google Patents
Pattern plating method for integrating two types of sheet resistance film circuits on same plane of dielectric substrate Download PDFInfo
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- CN105826231A CN105826231A CN201610351452.3A CN201610351452A CN105826231A CN 105826231 A CN105826231 A CN 105826231A CN 201610351452 A CN201610351452 A CN 201610351452A CN 105826231 A CN105826231 A CN 105826231A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
- H01L21/707—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
- H01L27/016—Thin-film circuits
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Abstract
The invention provides a pattern plating method for integrating two types of sheet resistance film circuits on the same plane of a dielectric substrate, comprising the following steps: sequentially sputtering a large-sheet-resistance resistive film, a small-sheet-resistance resistive film, an adhesion layer film and a conductor layer film on the same plane of a dielectric substrate; applying photoresist and carrying out pre-baking, exposing, developing and post-baking to form a graphical photoresist area on a surface to be pattern-plated; plating a thickened metal electrode layer and a protective layer in the graphical photoresist area; stripping the graphical photoresist, fully etching the conductor layer film and the adhesion layer film in the non-plated and non-thickened area, and removing the protective metal layer; making a small-sheet-resistance film resistor through photo-etching; and making a large-sheet-resistance film resistor through photo-etching. A circuit pattern made by the method has the advantages of small lateral growth of conductor patterns, steep line edge, high pattern resolution, and the like.
Description
Technical field
The present invention relates to microwave and millimeter wave thin flm circuit manufacturing technology field, particularly to a kind of graphic plating method of integrated two kinds of sheet resistance thin flm circuits on dielectric substrate same plane.
Background technology
Electric field radiation broadband detector based on distributed thin film resistor loaded, it is adaptable to the rf broadband electric field radiation detection in nearly total space region, far field.The program uses the little probe of electricity of distributed thin film resistor loaded to carry out the broadband reception of electric field radiation, then the detection of electric field radiation is carried out by highly sensitive low barrier Schottky diode, and the low pass filter radiofrequency signal that rectified signal is consisted of meander configuration high resistant line isolated, thus reach the purpose of low distortion output.Electric field radiation broadband detector based on distributed thin film resistor loaded, its structure and each ingredient are as shown in Figure 1, this electric field radiation broadband detector is mainly made up of six parts, it is the little probe of electricity 1 of distributed thin film resistor loaded, high sensitivity detector diode 2 respectively, high resistant low pass filter 3, high resistant transmission line 4, output port 5 and low loss dielectric plate 6.Electric field radiation broadband detector receives the electric field radiation signal in space by the little probe of electricity 1 of distributed thin film resistor loaded, then carried out the detection of radiant field intensity by high sensitivity detector diode 2, the detected value of radiant field intensity is sent to output port 5 by high resistant low pass filter 3 and high resistant transmission line 4.
Power probe antenna circuit processing technology needs the film resistor by two kinds of sheet resistances of size to be integrated in same dielectric surface during realizing.Wherein, the big sheet resistance scope of both sheet resistances interconnection film resistor 180 Ω/～250 Ω/between, little sheet resistance is in 10 Ω/left and right (for thin flm circuit sheet resistance labelling unit, also referred to as square or side).The manufacture method of microwave thin film integrated circuit figure has three kinds: one is that imposite electroplates deep etch method, photoetching molding after i.e. first imposite plating, belongs to subtractive process processing technology；The second is galvanoplastic after first litho pattern, i.e. first passes through deposited seed layer, chemical wet etching figure, then electroplated metal layer and reach requirement；The third is that bottom connects galvanoplastic, the most first the substrate of vacuum coating is carried out photoetching, superficial film beyond erosion removal circuitous pattern and retain following prime coat (such as Cr, TiW, Ta or TaN), utilize prime coat to realize the electrical connection of figure, then electroplate, thus can plate metal on figure and not plate metal on prime coat, final etching removes prime coat.First method not only cost is high, and owing to electroplating film layer is thicker, wet etching exists bigger corrosion factor so that the size of band wire diminishes, deterioration in accuracy；Easily produce metal-plated point on second method resistive layer, remove metal-plated point and easily scratch circuitous pattern；The selection of the third method prime coat metal material sheet resistance scope is improper or oxidative deactivation is dealt with improperly, prime coat the most easily produces metal-plated point, the most easily scratches circuitous pattern when removing metal-plated point.Two kinds of methods next, also can be along with the increase of thickness of coating in addition to having respective shortcoming, and the growth of band line side also increases, and makes band linear dimension increase, and precision is also deteriorated.These three method brings difficulty all to the accurately control of circuitous pattern size, thus affects performance and the yield rate of thin flm circuit.
Therefore, prior art is existing defects when the plating of integrated two kinds of sheet resistance thin flm circuits on dielectric substrate same plane, needs to improve.
Summary of the invention
It is an object of the invention to provide a kind of graphic plating method of integrated two kinds of sheet resistance thin flm circuits on dielectric substrate same plane, solve existing on the same plane of dielectric substrate during the thin flm circuit plating of integrated two kinds of sheet resistances, resistive layer easily produces metal-plated point and the relatively low problem of pattern precision.
The technical scheme is that and be achieved in that:
A kind of graphic plating method of integrated two kinds of sheet resistance thin flm circuits on dielectric substrate same plane, comprises the following steps:
Step (101): sputter big sheet resistance resistance film, little sheet resistance resistance film, adhesion layer thin film and thin film conductor layer on dielectric substrate same plane successively；
Step (102): by coating photoresist, front baking, expose, develop and after bake, forms graphical photoresist district treating on graphic plating face；
Step (103): plating thickeies metal electrode layer and protective layer in above-mentioned graphical photoresist district；
Step (104): by graphical photoresist lift off, then the thin film conductor layer and adhesion layer thin film of not electroplating thicker region are etched clean, then remove described guard metal layer；
Step (105): photoengraving makes little sheet resistance film resistor；
Step (106): photoengraving makes big sheet resistance film resistor.
Alternatively, in described step (101), described big sheet resistance resistance film material is NiCr thin film, and little sheet resistance resistance film material is TaN thin film or Ta thin film, and adhesion layer thin-film material is TiW thin film or Ti thin film, and thin film conductor layer material is Au thin film.
Alternatively, in described step (101), described dielectric substrate generally circular in shape or square, thickness is 0.127mm-0.508mm.
Alternatively, in described step (101), the material of described dielectric substrate is the alumina substrate of purity 99.6%-100% or the aluminium nitride chip of purity 98% or sapphire substrate.
The invention has the beneficial effects as follows:
(1) circuitous pattern produced have conductor fig side growth little, line edge is steep, graphics resolution advantages of higher；
(2) all will not produce metal-plated point on size sheet resistance thin film resistive layer, decrease the risk scratching conductor fig, circuit yields is greatly improved, it is adaptable to the plating batch production of integrated two kinds of sheet resistance thin flm circuit figures on dielectric substrate same plane.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in describing below is only some embodiments of the present invention, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is electric field radiation broadband detector schematic diagram based on distributed thin film resistor loaded；
A kind of graphic plating method flow chart of integrated two kinds of sheet resistance thin flm circuits on dielectric substrate same plane that Fig. 2 provides for the present invention；
A kind of schematic diagram of one specific embodiment of graphic plating method of integrated two kinds of sheet resistance thin flm circuits on dielectric substrate same plane that Fig. 3 a-f provides for the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art are obtained under not making creative work premise, broadly fall into the scope of protection of the invention.
The invention provides a kind of graphic plating method of integrated two kinds of sheet resistance thin flm circuits on dielectric substrate same plane, as in figure 2 it is shown, the method for the present invention comprises the following steps:
Step 101: sputter big sheet resistance resistance film, little sheet resistance resistance film, adhesion layer thin film and thin film conductor layer on dielectric substrate same plane successively；
Step 102: by coating photoresist, front baking, expose, develop and after bake, forms graphical photoresist district treating on graphic plating face；
Step 103: plating thickeies metal electrode layer and protective layer in above-mentioned graphical photoresist district；
Step 104: by graphical photoresist lift off, then the thin film conductor layer and adhesion layer thin film of not electroplating thicker region are etched clean, then remove described guard metal layer；
Step 105: photoengraving makes little sheet resistance film resistor；
Step 106: photoengraving makes big sheet resistance film resistor.
In described step 101, described big sheet resistance resistance film material is NiCr thin film, and little sheet resistance resistance film material is TaN thin film or Ta thin film, and adhesion layer thin-film material is TiW thin film or Ti thin film, and thin film conductor layer material is Au thin film.
In described step 101, described dielectric substrate generally circular in shape or square, thickness is 0.127mm-0.508mm；The material of described dielectric substrate is the alumina substrate of purity 99.6%-100% or the aluminium nitride chip of purity 98% or sapphire substrate.
Below in conjunction with specific embodiment, and referring to the drawings 3, the graphic plating method of integrated two kinds of sheet resistance thin flm circuits on dielectric substrate same plane of the present invention is described in further detail:
Embodiment one
It is sequentially depositing NiCr/TaN/TiW/Au thin film, as a example by the thin flm circuit graphic plating making two kinds of different sheet resistances of TaN with NiCr on alumina medium substrate same plane:
First, it is provided that a dielectric substrate 401, as shown in Figure 3 a, dielectric material is 2in × 2in square alumina substrate of purity 99.6%-100%, and thickness is 0.254mm, single-sided polishing, roughness≤1 μ in.After being cleaned up by dielectric substrate 401, its burnishing surface use magnetron sputtering technique sputter NiCr/TaN/TiW/Au thin film successively.Wherein, big sheet resistance resistance film material 402 be 200 Ω/NiCr thin film, little sheet resistance resistance film material 403 be 9.5 Ω/TaN thin film, adhesion layer thin-film material 404 is TiW thin film, and thin film conductor layer material 405 is Au thin film.
It follows that electrode pattern to be made photoetching the first mask plate.One layer of BP-218 type photoresist of rotary coating on dielectric substrate 401 surface conductor layer membrane materials 405Au thin film, spin coating rotating speed 3000rpm, spin coating time is 30s, then front baking 10min in 90 DEG C of thermostatic drying chambers, use the exposure of UV contact formula, during exposure, the glued membrane of mask plate is faced down, light intensity 6mW/cm2, time of exposure 15s, use developing liquid developing after having exposed, develop under room temperature 20s, after deionized water rinsing 15s, dries up with nitrogen, then after bake 20 minutes in 120 DEG C of thermostatic drying chambers.Through coating photoresist, front baking, expose, develop and after bake series of steps, just on the thin film conductor layer material 405Au film surface of this dielectric substrate 401, obtain graphical photoresist district 406, as shown in Figure 3 b.
3rd step, immerses the dielectric substrate 401 forming graphical photoresist district 406 process 60s in 25 DEG C of degreasers, gets 30s express developed with deionized water, it is subsequently placed into microetch 60s in hydrochloric acid, get 30s express developed with deionized water, be then turn on power supply, electric current density is set to 6mA/cm2, pre-gold-plated 10s, then electric current density and electroplating time are respectively set to 4mA/cm2And 15min, prepare gold plate 3 μm.After electrogilding, followed by electroplating 2 μm copper coatings.Sequentially pass through oil removing, pickling, rack plating mode electrogilding, electro-coppering series of steps, then this dielectric substrate 401 formed graphical photoresist district 406 exterior domain achieve electrogilding coating 407 and the making of guard metal layer 408 copper coating, as shown in Figure 3 c.
4th step, uses acetone at room temperature to clean 30s, this dielectric substrate 401 is formed graphical photoresist district 406 and is stripped clean.Then with the thin film conductor layer material 405Au thin film of Wagner's reagent etching sputtering; after etching is clean; re-use hydrogen peroxide and at room temperature complete the etching of adhesion layer thin-film material 404TiW thin film; finally use liquor ferri trichloridi by clean for guard metal layer 408 copper coating etching; the plating then completing thin flm circuit electrode pattern 409 on dielectric substrate 401 makes, as shown in Figure 3 d.
5th step, by little sheet resistance film resistor graphic making photoetching the second mask plate.In the micro structure that dielectric substrate 401 surface forms electrode pattern 409, one layer of BP-218 type photoresist of rotary coating, spin coating rotating speed 3000rpm, spin coating time is 30s, then front baking 10min in 90 DEG C of thermostatic drying chambers, use the exposure of UV contact formula, during exposure, the glued membrane of mask plate is faced down, light intensity 6mW/cm2Time of exposure 15s, developing liquid developing is used after having exposed, develop under room temperature 20s, after deionized water rinsing 15s, dry up with nitrogen, then after bake 20 minutes in 120 DEG C of thermostatic drying chambers, firmly treatment followed by carries out the etching operation of little sheet resistance resistance film material 403TaN thin film, finally removes photoresist with acetone.Through coating photoresist, front baking, expose, develop, after bake, etch and remove photoresist series of steps, use positive glue photo-etching processes formed on dielectric substrate 401 surface TaN thin film and the parallel connection of NiCr thin film little sheet resistance film resistor figure 410, as shown in Figure 3 e.
Finally, by big sheet resistance film resistor graphic making photoetching the 3rd mask plate.Electrode pattern 409 is formed on dielectric substrate 401 surface, and in the micro structure of the little sheet resistance film resistor figure 410 forming TaN thin film and the parallel connection of NiCr thin film, one layer of BP-218 type photoresist of rotary coating, spin coating rotating speed 3000rpm, spin coating time is 30s, then front baking 10min in 90 DEG C of thermostatic drying chambers, uses the exposure of UV contact formula, during exposure, the glued membrane of mask plate is faced down, light intensity 6mW/cm2, time of exposure 15s, use developing liquid developing after having exposed, develop under room temperature 20s, after deionized water rinsing 15s, dries up with nitrogen, after bake 20 minutes in 120 DEG C of thermostatic drying chambers again, and then etch big sheet resistance resistance film material 402NiCr thin film, finally remove photoresist with acetone.Through coating photoresist, front baking, expose, develop, after bake, etch and remove photoresist series of steps, use positive glue photo-etching processes, NiCr big sheet resistance film resistor figure 411, TaN thin film and NiCr thin film little sheet resistance film resistor figure 410 in parallel and electrode pattern 409 is formed, as illustrated in figure 3f on dielectric substrate 401 surface.So far, on dielectric substrate same plane, the graphic plating of integrated two kinds of sheet resistance thin flm circuits makes complete.
Embodiment two
It is sequentially depositing NiCr/Ta/Ti/Au thin film, as a example by the thin flm circuit graphic plating of integrated two kinds of different sheet resistances of Ta, NiCr on sapphire dielectric substrate same plane:
First, it is provided that a dielectric substrate 401, as shown in Figure 3 a, dielectric material is the circular sapphire substrate of diameter 2in, and thickness is 0.254mm, twin polishing, roughness≤1 μ in.After being cleaned up by dielectric substrate 401, its burnishing surface use magnetron sputtering technique sputter NiCr/Ta/Ti/Au thin film successively.Wherein, big sheet resistance resistance film material 402 be 250 Ω/NiCr thin film, little sheet resistance resistance film material 403 be 10 Ω/Ta thin film, adhesion layer thin-film material 404 is Ti thin film, and thin film conductor layer material 405 is Au thin film.
It follows that electrode pattern to be made photoetching the first mask plate.One layer of RZJ-390PG type photoresist of rotary coating on the thin film conductor layer material 405Au thin film of dielectric substrate 401, spin coating rotating speed 3000rpm, spin coating time is 30s, then front baking 8min in 90 DEG C of thermostatic drying chambers, use the exposure of UV contact formula, during exposure, the glued membrane of mask plate is faced down, light intensity 6mW/cm2, time of exposure 15s, use developing liquid developing after having exposed, develop under room temperature 20s, after deionized water rinsing 15s, dries up with nitrogen, then after bake 20 minutes in 120 DEG C of thermostatic drying chambers.Through coating photoresist, front baking, expose, develop and after bake series of steps, just on the thin film conductor layer material 405Au film surface of this dielectric substrate 401, obtain graphical photoresist district 406, as shown in Figure 3 b.
3rd step, immerses the dielectric substrate 401 forming graphical photoresist district 406 process 60s in 25 DEG C of degreasers, gets 30s express developed with deionized water, it is subsequently placed into microetch 60s in hydrochloric acid, get 30s express developed with deionized water, be then turn on power supply, electric current density is set to 6mA/cm2, pre-gold-plated 10s, then electric current density and electroplating time are respectively set to 4mA/cm2And 15min, prepare gold plate 3 μm.After electrogilding, followed by electroplating 2 μm copper coatings.Sequentially pass through oil removing, pickling, rack plating mode electrogilding, electro-coppering series of steps, then this dielectric substrate 401 formed graphical photoresist district 406 exterior domain achieve electrogilding coating 407 and the making of guard metal layer 408 copper coating, as shown in Figure 3 c.
4th step, uses acetone at room temperature to clean 30s, this dielectric substrate 401 is formed graphical photoresist district 406 and is stripped clean.Then the thin film conductor layer material 405Au thin film of sputtering is at room temperature etched with Wagner's reagent; after corrosion is clean; re-use hydrogen peroxide and at room temperature complete the etching of adhesion layer thin-film material 404Ti thin film; finally use liquor ferri trichloridi by clean for guard metal layer 408 copper coating etching; the plating then completing thin flm circuit electrode pattern 409 on dielectric substrate 401 makes, as shown in Figure 3 d.
5th step, by little sheet resistance film resistor graphic making photoetching the second mask plate.In the micro structure that dielectric substrate 401 surface forms electrode pattern 409, one layer of RZJ-390PG type photoresist of rotary coating, spin coating rotating speed 3000rpm, spin coating time is 30s, then front baking 8min in 90 DEG C of thermostatic drying chambers, use the exposure of UV contact formula, during exposure, the glued membrane of mask plate is faced down, light intensity 6mW/cm2Time of exposure 15s, developing liquid developing is used after having exposed, develop under room temperature 20s, after deionized water rinsing 15s, dry up with nitrogen, then after bake 20 minutes in 120 DEG C of thermostatic drying chambers, firmly treatment followed by carries out the etching operation of little sheet resistance resistance film material 403Ta thin film, finally removes photoresist with acetone.Through coating photoresist, front baking, expose, develop, after bake, etch and remove photoresist series of steps, uses positive glue photo-etching processes to form Ta thin film and the little sheet resistance film resistor figure 410 of NiCr thin film parallel connection on dielectric substrate 401 surface, as shown in Figure 3 e.
Finally, by big sheet resistance film resistor graphic making photoetching the 3rd mask plate.Electrode pattern 409 is formed on dielectric substrate 401 surface, and in the micro structure of the little sheet resistance film resistor figure 410 forming Ta thin film and the parallel connection of NiCr thin film, one layer of RZJ-390PG type photoresist of rotary coating, spin coating rotating speed 3000rpm, spin coating time is 30s, then front baking 8min in 90 DEG C of thermostatic drying chambers, uses the exposure of UV contact formula, during exposure, the glued membrane of mask plate is faced down, light intensity 6mW/cm2, time of exposure 15s, use developing liquid developing after having exposed, develop under room temperature 20s, after deionized water rinsing 15s, dries up with nitrogen, after bake 20 minutes in 120 DEG C of thermostatic drying chambers again, and then etch big sheet resistance resistance film material 402NiCr thin film, finally remove photoresist with acetone.Through coating photoresist, front baking, expose, develop, after bake, etch and remove photoresist series of steps, use positive glue photo-etching processes, NiCr big sheet resistance film resistor figure 411, Ta thin film and NiCr thin film little sheet resistance film resistor figure 410 in parallel and electrode pattern 409 is formed, as illustrated in figure 3f on dielectric substrate 401 surface.So far, on dielectric substrate same plane, the graphic plating of integrated two kinds of sheet resistance thin flm circuits makes complete.
In sum, a kind of graphic plating method of integrated two kinds of sheet resistance thin flm circuits on dielectric substrate same plane of the present invention, the circuitous pattern produced have conductor fig side growth little, line edge is steep, graphics resolution advantages of higher；All will not produce metal-plated point on size sheet resistance thin film resistive layer, decrease the risk scratching conductor fig, circuit yields is greatly improved, it is adaptable to the plating batch production of integrated two kinds of sheet resistance thin flm circuit figures on dielectric substrate same plane.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all within the spirit and principles in the present invention, any modification, equivalent substitution and improvement etc. made, should be included within the scope of the present invention.
Claims (4)
1. the graphic plating method of integrated two kinds of sheet resistance thin flm circuits on dielectric substrate same plane, it is characterised in that comprise the following steps:
Step (101): sputter big sheet resistance resistance film, little sheet resistance resistance film, adhesion layer thin film and thin film conductor layer on dielectric substrate same plane successively；
Step (102): by coating photoresist, front baking, expose, develop and after bake, forms graphical photoresist district treating on graphic plating face；
Step (103): plating thickeies metal electrode layer and protective layer in above-mentioned graphical photoresist district；
Step (104): by graphical photoresist lift off, then the thin film conductor layer and adhesion layer thin film of not electroplating thicker region are etched clean, then remove described guard metal layer；
Step (105): photoengraving makes little sheet resistance film resistor；
Step (106): photoengraving makes big sheet resistance film resistor.
A kind of graphic plating method of integrated two kinds of sheet resistance thin flm circuits on dielectric substrate same plane, it is characterized in that, in described step (101), described big sheet resistance resistance film material is NiCr thin film, little sheet resistance resistance film material is TaN thin film or Ta thin film, adhesion layer thin-film material is TiW thin film or Ti thin film, and thin film conductor layer material is Au thin film.
A kind of graphic plating method of integrated two kinds of sheet resistance thin flm circuits on dielectric substrate same plane, it is characterized in that, in described step (101), described dielectric substrate generally circular in shape or square, thickness is 0.127mm-0.508mm.
A kind of graphic plating method of integrated two kinds of sheet resistance thin flm circuits on dielectric substrate same plane, it is characterized in that, in described step (101), the material of described dielectric substrate is the alumina substrate of purity 99.6%-100% or the aluminium nitride chip of purity 98% or sapphire substrate.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106744654A (en) * | 2016-11-30 | 2017-05-31 | 合肥工业大学 | A kind of method for preparing transverse circular micro coaxle metal structure on a silicon substrate |
| CN106848503A (en) * | 2017-03-24 | 2017-06-13 | 中国振华集团云科电子有限公司 | Film filter and film filter manufacture method |
| CN110854005A (en) * | 2019-11-22 | 2020-02-28 | 广西民族大学 | Method for manufacturing electrode with micron structure |
| CN110993556A (en) * | 2019-11-20 | 2020-04-10 | 中电国基南方集团有限公司 | Method for preparing ceramic thin film circuit with electroplated nickel layer as mask layer |
| CN112687616A (en) * | 2020-12-24 | 2021-04-20 | 中国电子科技集团公司第十三研究所 | Preparation method of radio frequency tube shell and radio frequency tube shell |
| CN114561677A (en) * | 2022-01-26 | 2022-05-31 | 蚂蚁之家(上海)健康科技有限公司 | Ruby coating process of beauty instrument and beauty instrument |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5723359A (en) * | 1995-12-14 | 1998-03-03 | Lg Information & Communications, Ltd. | Method for concurrently forming thin film resistor and thick film resistor on a hybrid integrated circuit substrate |
| CN101533693A (en) * | 2009-03-16 | 2009-09-16 | 广州翔宇微电子有限公司 | Microwave film resistor, microwave film resistor network module and manufacturing method thereof |
| CN103606520A (en) * | 2013-11-25 | 2014-02-26 | 中国电子科技集团公司第四十一研究所 | Method for manufacturing metal protective film used for film circuit test |
-
2016
- 2016-05-18 CN CN201610351452.3A patent/CN105826231B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5723359A (en) * | 1995-12-14 | 1998-03-03 | Lg Information & Communications, Ltd. | Method for concurrently forming thin film resistor and thick film resistor on a hybrid integrated circuit substrate |
| CN101533693A (en) * | 2009-03-16 | 2009-09-16 | 广州翔宇微电子有限公司 | Microwave film resistor, microwave film resistor network module and manufacturing method thereof |
| CN103606520A (en) * | 2013-11-25 | 2014-02-26 | 中国电子科技集团公司第四十一研究所 | Method for manufacturing metal protective film used for film circuit test |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106744654A (en) * | 2016-11-30 | 2017-05-31 | 合肥工业大学 | A kind of method for preparing transverse circular micro coaxle metal structure on a silicon substrate |
| CN106744654B (en) * | 2016-11-30 | 2018-03-09 | 合肥工业大学 | A kind of method for preparing transverse circular micro coaxle metal structure on a silicon substrate |
| CN106848503A (en) * | 2017-03-24 | 2017-06-13 | 中国振华集团云科电子有限公司 | Film filter and film filter manufacture method |
| CN110993556A (en) * | 2019-11-20 | 2020-04-10 | 中电国基南方集团有限公司 | Method for preparing ceramic thin film circuit with electroplated nickel layer as mask layer |
| CN110854005A (en) * | 2019-11-22 | 2020-02-28 | 广西民族大学 | Method for manufacturing electrode with micron structure |
| CN112687616A (en) * | 2020-12-24 | 2021-04-20 | 中国电子科技集团公司第十三研究所 | Preparation method of radio frequency tube shell and radio frequency tube shell |
| CN114561677A (en) * | 2022-01-26 | 2022-05-31 | 蚂蚁之家(上海)健康科技有限公司 | Ruby coating process of beauty instrument and beauty instrument |
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