CN105825887A - Memory array and operating method - Google Patents
Memory array and operating method Download PDFInfo
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- CN105825887A CN105825887A CN201510001861.6A CN201510001861A CN105825887A CN 105825887 A CN105825887 A CN 105825887A CN 201510001861 A CN201510001861 A CN 201510001861A CN 105825887 A CN105825887 A CN 105825887A
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Abstract
The invention discloses a memory array and its operating method. The memory array contains multiple memory cells which are arranged in multiple columns and rows, wherein multiple parallel memory strings are corresponding to the respective rows; multiple word lines are arranged to be vertical to the memory strings; and each word line is connected to multiple gate electrodes of a corresponding column of the columns of the memory cells. According to the method, programming operation is executed; the programming operation programs all memory cells on the multiple edge word lines, which are positioned on an opposite side of the memory array; the programming operation operates multiple selective memory cells in the memory array according to input data to be stored in the memory array; and the selective memory cells are positioned among the edge word lines. Threshold voltage of each programmed memory cell is positioned at programming verifying level.
Description
Technical field
The invention relates to a kind of memory array and operational approach thereof, and in particular to a kind of operational approach that can suppress to read the memory array of interference.
Background technology
Non-volatile (non-volatile), even if storage arrangement is a kind of when the supply of electric power is removed, remains to persistently store the semiconductor device of data.Nand flash memory device is a kind of non-volatile memory devices being developed.Nand flash memory device comprises memory array, and memory array comprises multiple memory element being arranged in parallel character string.Due to the bias mechanism applied when read operation, cause reading interference and occur among these character strings.
Summary of the invention
According to one embodiment of the invention, the operational approach of a kind of memory array is to be provided.Memory array comprises the multiple memory element (cell) being arranged in multiple row (row) with multiple row (column), the corresponding respective row to these row of plurality of parallel memory character string (memorystring), multiple wordline (wordline) are to arrange and be perpendicular to the plurality of memory character string, and each wordline is connected to multiple gate electrodes of respective column of these row of these memory element.The method includes: perform programming (program) operation, this programming operation is programmed in all these memory element on multiple limits wordline (edgewordline), these limit wordline are positioned on the limit, opposite of this memory array, and this programming operation is according to waiting that being stored in the input data among this memory array programs the multiple select storage units among this memory array, these multiple select storage units are between these limit wordline.After each programming, the threshold voltage of memory element is positioned at programming checking (programverify, a PV) level.
According to another embodiment of the present invention, a kind of integrated circuit is to be provided, and integrated circuit includes a memory array and a control circuit.Memory array comprises the multiple memory element being arranged in multiple row with multiple row, the corresponding respective row to these row of plurality of parallel memory character string, multiple wordline are to arrange and be perpendicular to the plurality of memory character string, and each wordline is connected to multiple gate electrodes of respective column of these row of these memory element.Control circuit is configured to perform this memory array one programming operation, to be programmed in all these memory element in the wordline of multiple limits, these limit wordline are positioned on the limit, opposite of this memory array, and according to waiting that being stored in the input data among this memory array programs the multiple select storage units among this memory array, these select storage units are between these limit wordline, and after each programming, the threshold voltage of memory element is positioned at a PV level.
According to further embodiment of this invention, a kind of control circuit is to be provided, and control circuit is used for operating memory array.This memory array comprises multiple memory element.This control circuit includes Circuits System (circuitry), it is configured to this memory array is performed a programming operation, to be programmed in all these memory element in the wordline of multiple limits, these limit wordline are positioned on the limit, opposite of this memory array, and according to waiting that being stored in the input data among this memory array programs the multiple select storage units among this memory array, these select storage units are between these limit wordline.After each programming, the threshold voltage of memory element is positioned at a PV level.
More preferably understand in order to the above-mentioned and other aspect of the present invention is had, preferred embodiment cited below particularly, and coordinate institute's accompanying drawings, be described in detail below:
Accompanying drawing explanation
Fig. 1 illustrates the generalized section according to exemplary embodiment one memory element.
Fig. 2 illustrates the schematic diagram of the equivalent circuit of the memory array according to an exemplary embodiment.
Fig. 3 illustrates the schematic diagram of the integrated circuit comprising memory array according to an exemplary embodiment.
Fig. 4 illustrates the schematic diagram of the programming pattern of the memory element among programmable memory array according to an exemplary embodiment.
Fig. 5 illustrates the schematic diagram according to the programming pattern in the memory character string of a comparative example.
Fig. 6 illustrates according to the exemplary embodiment selected WL signal during read operation and the schematic diagram of the waveform of non-selected WL signal.
Fig. 7 A illustrates and is programmed that according to the programming pattern of Fig. 4 memory array is listed in before pressure is read in application and the distribution schematic diagram of threshold voltage measured afterwards.
Fig. 7 B illustrates the programming pattern of foundation Fig. 4 and is programmed that memory array is listed in the distribution schematic diagram of the difference before pressure is read in application and between threshold voltage measured afterwards.
Fig. 8 illustrates the schematic diagram of the programming pattern of the memory element in programmable memory array according to a comparative example.
Fig. 9 A illustrates and is programmed that according to the programming pattern of Fig. 8 memory array is listed in before pressure is read in application and the distribution schematic diagram of threshold voltage measured afterwards.
Fig. 9 B illustrates the programming pattern of foundation Fig. 8 and is programmed that memory array is listed in the distribution schematic diagram of the difference before pressure is read in application and between threshold voltage measured afterwards.
[symbol description]
100: memory element
102: substrate
104: the first doped regions
106: the second doped regions
108: channel region
110: tunneling dielectric structure
112: lower oxide skin(coating)
114: nitride layer
116: upper oxide skin(coating)
120: electric charge storage layer
130: sealing coat
140: gate electrode
200: memory array
210-213: memory character string
220: memory element
230:BL0
240:CSL
250-253: character string select transistor
260,261: ground connection selects transistor
270: wordline
280: select line with coupling
281: strange ground connection selects line
290: character string selects line
310: controller
320: Voltage Supply Device
330: column decoder
340: line decoder
350: sensing amplifier
360: Data In-Line
370: DOL Data Output Line
Detailed description of the invention
Especially exemplified by exemplary embodiment, and institute's accompanying drawings will be coordinated now, elaborate.If if possible, the most identical reference number will be used for representing identical or similar assembly.
Fig. 1 illustrates the generalized section according to exemplary embodiment one memory element 100.Memorizer 100 comprises: substrate 102；First doped region 104 and the second doped region 106, is arranged in substrate 102；Channel region 108, is arranged between the first doped region 104 and the second doped region 108；Tunneling dielectric structure (tunneldielectricstructure) 110, is arranged on above-mentioned channel region 108；One electric charge storage layer 120, is arranged in above-mentioned tunneling dielectric structure 110；One sealing coat 130, is arranged on above-mentioned electric charge storage layer 120；One gate electrode 140, is arranged on above-mentioned sealing coat 130.Substrate 102 can be implemented as the p-type trap (P-well) being formed in semiconductor crystal wafer, and first and second doped region 104 and 106 can be N-type.Alternatively, substrate 102 can be implemented as the N-type trap (N-well) being formed in semiconductor crystal wafer, and first and second doped region 104 and 106 can be p-type.Tunneling dielectric structure 110 can be formed with any structure for tunneling dielectric structure known in this skill.In an illustrated embodiment, tunneling dielectric structure 110 is three layers of thin ONO structure, the nitride layer 114 (N) comprise lower oxide skin(coating) 112 (O), being arranged on lower oxide skin(coating) 112 and the upper oxide skin(coating) 116 (O) being arranged on nitride layer 114.The thickness that each of lower oxide skin(coating) 112, nitride layer 114 and upper oxide skin(coating) 116 has is aboutExtremelyElectric charge storage layer 120 is to be formed by silicon oxide or silicon nitride or other charge storage material, such as Al2O3、HfOx、ZrOX.The thickness of electric charge storage layer 120 is aboutExtremely
For memory cells 100, first and second doped region 104 is to be grounded with 106 and substrate 102, and program voltage such as from about 18V is to be applied in gate electrode 140.So, electronics is to be injected into electric charge storage layer 120 from channel region 108, and promotes the threshold V T of memory element 100 to programming checking (programverify, PV) level.In order to wipe data from memory element 100, gate electrode 140 is to be grounded, and first and second doped region 104 and 106 is to be grounded or suspension joint, and erasing voltage such as from about 18V is to be applied in substrate 102.So, electronics is to be removed from electric charge storage layer 120, and reduces the threshold V T of memory element 100 to wiping checking (eraseverify, EV) level.
Memory element 100 can be single-order unit (singlelevelcell, SLC) or MLC (multi-levelcell, MLC).The VT of SLC can be set to an EV level or a PV level.The VT of MLC can be set to an EV level, or one of them of multiple PV level.
Fig. 2 illustrates the schematic equivalent circuit of three-dimensional perpendicular grid (three-dimensionalverticalgate, 3DVG) memory array 200 according to an exemplary embodiment (herein with reference to for memory array 200).Memory array 200 has NAND structure, comprises multiple memory character string 210-213.Each of memory character string 210-213 comprises multiple memory element 220, such as 64 memory element 220, and memory element 220 is connected in series and corresponding a line to memory array.
Memory character string 210-213 one block array (blockarray) of composition.Each correspondence of memory character string 210-213 is to a passage bit line (bitline, BL).These passages BL of block array is that group (group) together and is connected to a global bit line (globalbitline, GBL), the BL0230 as marked in Fig. 2.Each of memory character string 210-213 be connected to BL0230 and multiple common denominator lines (commonsourceline, CSL) 240 one of them between.Adjacent memory character string 210-213 converts between the direction of bit line end in the direction of bit line end contact source line end and source line end.For example, memory character string 210 and 212 has the source line end direction toward bit line end, and remembers character string 211 and 213 and have the bit line end direction toward source line end.It is to say, for each of memory character string 210 and 212, CSL240 is connected to remember the upper end of character string, and BL0230 is connected to remember the lower end of character string, as shown in Figure 2；And for each of memory character string 211 and 213, BL0230 is connected to remember the upper end of character string, and CSL240 is connected to remember the lower end of character string, as shown in Figure 2.
Each of multiple character string select transistor 250-253 is connected between one that BL0230 is corresponding with memory character string 210-213.It is to say, character string select transistor 250 is connected between the lower end of BL0230 and memory character string 210；Character string select transistor 251 is connected between the upper end of BL0230 and memory character string 211；Character string select transistor 252 is connected between the lower end of BL0230 and memory character string 212；Character string select transistor 253 is connected between the upper end of BL0230 and memory character string 213.
Multiple ground connection select transistor 260 and 261 to be connected the two ends of memory character string 210-213.It is to say, ground connection selects transistor 260 to be connected to remember the upper end of each of character string 210-213, as shown in Figure 2.Another ground connection selects transistor 261 to be connected to remember the lower end of each of character string 210-213, as shown in Figure 2.
Multiple wordline (such as 64 wordline WL0, WL1 ..., WL63) 270 are to be arranged and be perpendicular to multiple memory character string 210-213.Each wordline 270 is connected to these a little gate electrodes of the memory element 220 of a respective column.Multiple ground connection of memory array 200 select transistor 260 to form row, and one selects line GSL (occasionally) 280 connected so far row ground connection to select the corresponding gate electrode of transistor 260 with coupling.Ground connection selects transistor 261 to form string, and a strange ground connection selects line GSL (very) 281 to be connected to the gate electrode that this journey ground connection selects the correspondence of transistor 261.Multiple character strings select line (SSL0, SSL1, SSL2, SSL3) 290 to be connected to these a little character string select transistors 250 of correspondence.
In embodiment as shown in Figure 2, memory array 200 comprises four memory character strings 210-213 and 64 WL270.But, the quantity of disclosed memory element, memory character string and wordline is not limited to this.Memory array 200 can comprise any amount of memory element, memory character string and the wordline being arranged in array.
Fig. 3 illustrates the schematic diagram of the integrated circuit 300 comprising the memory array 200 shown in Fig. 2 according to an exemplary embodiment.Integrated circuit 300 comprises controller 310, Voltage Supply Device 320, column decoder 330, line decoder 340 and sensing amplifier 350.Controller 310 is arranged to control Voltage Supply Device 320 and provides to column decoder 330 and the bias voltage of line decoder 340 or the application of ground connection.Controller 310 is also configurable to provide storage address to column decoder 330 and line decoder 340.Controller 310 can be implemented by the special purpose logic circuitry known in skill.Alternatively, controller 310 can be by being implemented with performing to be stored in the general service processor of the program of storage device.The most alternatively, controller 310 can be implemented by special purpose logic circuitry or the combination of general service processor.Column decoder 330 is coupled to be connected to these a little WL270 of the memory element 220 of respective column in memory array 200, to bias this little WL270 according to the bias mechanism different for read operation, programming operation and erasing operation etc..Line decoder 340 is coupled to be connected to these a little SSL290 of the character string select transistor 250 of corresponding row in memory array 200, to bias this little SSL290 according to different bias mechanism.Sensing amplifier 350 senses the input data received from integrated circuit 300 data source (not illustrating) interiorly or exteriorly via Data In-Line 360, and supplies input data to line decoder 340.Sensing amplifier 350 also senses the electric current of memorizer character string corresponding in these a little memorizer character strings 210-213 of memory array 200, and changes sensing electric current into digital numerical value to be provided to integrated circuit 300 device (not illustrating) interiorly or exteriorly via DOL Data Output Line 370.In more detail, sensing amplifier 350 comprises many sub-sensing amplifiers (not illustrating), a memorizer character string corresponding in each sub-sensing amplifier connection so far a little memorizer character strings, and senses the electric current of this corresponding memorizer character string.It is digital numerical value that sensing amplifier 350 then changes sensing electric current, and combines the address of a digital numerical value memorizer character string corresponding with these corresponding a little memory string 210-213, thus produces output data and supply on DOL Data Output Line 370.
Once memory array 200 is manufactured, and controller 310 is configured to memory array performs erasing/reset operation so that each memory element in the memory element 220 of memory array 200 has the threshold V T being positioned at EV level.It is as described later for performing the exemplary bias mechanism of erasing/reset operation.During the erasing/operation that resets, BL0230, these a little CSL240, these a little WL270, these a little SSL290 are to be grounded, and erasing voltage about 18V is applied to the substrate (such as p-well) that memory array 200 is formed.So, the threshold V T of all memory element 220 in memory array 200 is to be set at EV level.
After the operation that resets, controller 310 is configured to the selected memory element in the memory element 220 of memory array 200 is performed programming operation so that this is chosen each of memory element 220 a bit and has the threshold V T being positioned at PV level.It is as described later for performing the exemplary bias mechanism of programming operation.For example, controller 310 is configured to program the unit A being positioned at WL62270 with the boundary of memory character string 212, as shown in Figure 2.For programming unit A, system voltage Vcc about 3.3V is applied to SSL2290 and selects to remember character string 212 with the character string select transistor 252 in conducting memory character string 212, and other SSL (SSL0, SSL1, SSL3) 290 are to be grounded to end character string select transistor 250,251,253.And, program voltage Vprogram about 18V is applied to WL62270 with programming unit A, and conducting voltage Vpass about 7V to 12V is applied in the most a little non-selected WL (WL0, WL1, WL2 ..., WL61, WL63) 270 with other memory element 220 in conducting memory character string 212.The voltage of about 0V is applied to BL0230, and system voltage Vcc is applied to other non-selected global bit line (not being illustrated in Fig. 2).The substrate (such as p-well) that these a little CSL240, GSL (occasionally) 280 and memory array 200 are formed is to be grounded.System voltage Vcc is applied to GSL (very) 281.So, the top of the memorizer character string 212 between upper source/drain and the CSL240 of unit A and the bottom of the memorizer character string 212 between lower source/drain and the BL0230 of unit A, for conducting.Therefore, electronics is the electric charge storage layer being injected into unit A, and the VT of unit A is to be promoted to PV level.Herein, the memory element of the VT with PV level is known as " programming unit ", and have the VT of EV level memory element be known as " erasing unit ".
After a program operation, controller 310 is configured to memory array 200 is performed read operation.It is as described later for performing the exemplary bias mechanism of read operation.For example, in order to read unit A, first, all of SSL290 with GSL280 and 281 is to be cut off, and bit-line voltage VBL about 1V is applied to global bit line (GBL), as shown in the BL0230 of Fig. 2.So, GBL stray capacitance is to be precharged to a predetermined level, such as 1V.Then, system voltage Vcc about 3.3V is applied to this little GSL280 and 281, to turn on ground connection selection transistor 260 and 261.System voltage Vcc is also applied to SSL2290 and selects to remember character string 212 with the character string select transistor 250 in conducting memory character string 212.Other SSL (SSL0, SSL1, SSL3) 290 are to be grounded to end character string select transistor 250,251,253.Read voltage Vread such as from about 1V (between EV level and PV level) is applied to WL62270 (being herein known as " being chosen WL ").Conducting voltage Vpass such as from about 6V (higher than PV level) is applied in the most a little non-selected WL (WL0, WL1, WL2 ..., WL61, WL63) 270 and remembers other memory element 220 in character string 212 with conducting, and no matter they are programming unit or erasing unit.Owing to the unit A on selected WL62 has the programming unit of the PV level higher than Vread, therefore unit A is to be cut off, and remembering other unit in character string 212 is to be switched on by the Vpass higher than PV level.So, memory character string 212 not conducting, and GBL stray capacitance is not discharged.So, the corresponding bit-line voltage to GBL operation bias remains unchanged.If it addition, unit A has the erasing unit of the VT of level EV level, unit A is to be switched on by the application higher than the Vread of EV, and other unit remembered in character string 212 are also turned on.In this example, memory character string 212 is conducting, and the GBL stray capacitance remembered in character string 212 is to be discharged.So, the bit-line voltage of corresponding GLB operation bias can be changed.
Various voltages as above, comprise Vpass, Vread, Vprogram, VBL, Vcc, ground connection, are to be produced by Voltage Supply Device 320, and are applied to memory array 200 by Circuits System (not illustrating).
Fig. 4 illustrates the schematic diagram of the programming pattern 400 of the memory element 220 among programmable memory array 200 according to an exemplary embodiment.Programming pattern 400 display has multiple programming units of the VT of PV level and the distribution of multiple erasing unit of the VT with EV level.According to the exemplary embodiment of the present invention, WL0 Yu WL63 is set at redundancy (dummy) wordline, and on redundant word line, memory element is intentionally programmed and has the VT of PV ' level.It is to say, according to Fig. 4, all memory element 220 being positioned on limit WL (being i.e. positioned at wordline WL0 on limit, memory array 200 opposite and WL63) are programming units, are denoted as in the programming pattern 400 shown in Fig. 4 " PV ".It addition, the selected memory element among memory element 220 on WL1 to WL62 is based on the input data that received via Data In-Line 360 and is programmed.Therefore, these programming units are denoted as " PV ".Remaining memory element 220 is erasing unit, is denoted as in the programming pattern 400 shown in Fig. 4 " EV ".PV ' the level of the memory element in limit wordline WL0 and WL63 can be equal to the PV level of the memory cells on wordline WL1 to WL62.Alternatively, PV ' level may also differ from PV level.
Described further below, deliberately program these a little memory element 220 on limit wordline WL0 and WL63 and there is the effect of suppression reading interference.If the memory element 220 in limit wordline WL0 and WL63 is not programming unit, then reads interference and can occur in some erasing memory element, in place of these erasing memory element are positioned against near side (ns) wordline and adjacent to programming unit.
Although the programming pattern 400 shown in Fig. 4 comprises the programming unit on limit wordline WL0 and WL63, the present invention is not limited to this.It is to say, the benefit that interference is read in suppression also may be accomplished by: these a little memory element in the limit wordline more than in each on the limit, opposite of memory array are programmed." limit wordline " as used herein is with reference to the wordline at or adjacent to the limit in memory array.For example, the benefit of suppression reading interference may be accomplished by: the memory element being pointed on WL0, WL1, WL62, WL63 or WL0-WL3, WL61-WL63 is programmed.
Although the programming pattern 400 in memory element 220 between WL0 and WL63 comprises checkerboard (checkerboard) pattern in Fig. 4, that is, the nearest-neighbors of one programming unit is an erasing unit, and vice versa, and the right present invention is also not limited to this.The programming pattern in memory element 220 between WL0 and WL63 can be any pattern, depending on the data among input data memory array to be stored to 200.
Following description is about the reason of the memory element 220 on programming limit WL.Fig. 5 illustrates the schematic diagram according to the programming pattern in the memory character string 510 of a comparative example.According to Fig. 5, the memory element being positioned on WL2 and WL60 is programming unit, and the memory element being positioned on other WL (comprising limit WL, such as WL0 and WL63) is erasing unit.Furthermore, it is selected WL to be read at read operation period WL3, and WL0-WL2 and WL4-WL63 is non-selected WL.
Fig. 6 illustrates the schematic diagram of the waveform waiting to be applied to selected WL signal and the non-selected WL signal being chosen WL and non-selected WL according to an exemplary embodiment during read operation respectively.At time t1, non-selected WL signal is in initial voltage level, such as 0V.Then, at time t2, non-selected WL signal is promoted to PV level, such as 3V, and continues to lift up straight at time t3 and arrives Vpass, such as 6V.Until time t4, non-selected WL signal maintains Vpass.Then, at time t5, non-selected WL signal drops to PV level, and at time t6, continues to decline straight and arrive 0V.At time t1, selected WL signal promotes along with non-selected WL signal simultaneously, and while non-selected WL signal reaches the time t3 of Vpass, selected WL signal arrives its target voltage level, Vread.Furthermore, at time t4, selected WL signal declines along with non-selected WL signal simultaneously, and along with non-selected WL signal arrives its target voltage level while time t6.
Refer to aforesaid Fig. 5, when non-selected WL signal is promoted to 3V (i.e. PV level) at t1 to t2 from 0V, programming unit on WL2 and WL60 is to be cut off, and the erasing unit on non-selected WL (WL0, WL1, WL4-WL59 and WL61-63) is turned on.Therefore, the passage of the memory element between WL2 and WL60 is by suspension joint (that is, be not attached to voltage source, as or Vcc), and the current potential of passage is to be enhanced (boost) by electric capacity with coupling of gate voltage (voltage of non-selected WL).On the other hand, being to be grounded owing to being positioned at BL230 with CSL240 at memory character string 510 two ends, the passage of the memory element between WL2 and BL, between WL60 and CSL is to be grounded.So, among the memory element on selected WL60, the voltage level of passage offside is the most non-equilibrium, and hot carrier (hotcarrier) cannot be generated.So, because WL61 is near WL60 and between WL60 and CSL, the VT of the memory element on WL61 can disturbed one-tenth higher than a certain level of EV level.Similarly, because WL1 is near WL2 and between WL1 and BL, the VT of the memory element on WL1 can disturbed one-tenth higher than a certain level of EV level.So, the memory element on WL1 and WL61 is affected by read operation interference, implies that reading interference.
On the other hand, if the memory element on WL0 and WL63 is programming unit, when non-selected WL is promoted to 3V (i.e. PV level) at t1 to t2 from 0V, the passage of the memory element between WL0 and WL63 is by suspension joint.Therefore, the voltage level of the offside of the passage of the memory cells on WL2 and WL60 is to be balanced.So, the memory element on WL1 and WL61 is interference-free.
Example
The memory array with structure as shown in Figure 2 is to be made into.Memory array is to be reset according to the programming pattern 400 shown in Fig. 4 then to program.Then, read pressure to be applied to memory array by performing 1,000,000 read operations.It is to say, waveform as shown in Figure 6 is repeated 1,000,000 times.During read operation, WL30 is to be used as being chosen WL, other WL being non-selected WL.With afterwards before reading the application of pressure, the threshold V T of the memory element on WL0-WL3 with WL60-WL63 is measured.
The memory cell that Fig. 7 A is shown on WL0-WL3 and WL60-WL63 is applied before reading pressure and the distribution schematic diagram of threshold voltage measured afterwards.In fig. 7, x-axis represents the numerical value of threshold voltage, and y-axis represents the counting (i.e. quantity) of the memory element in each of WL0-WL3 and WL60-WL63 with particular threshold voltage.The dotted line of Fig. 7 A is with reference to threshold voltage measured in corresponding memory element before read operation, and the solid line of Fig. 7 A is with reference to threshold voltage measured in corresponding memory element after read operation.Fig. 7 B is shown in the distribution schematic diagram of the difference before pressure is read in application and between threshold voltage measured from corresponding memory element afterwards.In figure 7b, x-axis represents the numerical value of threshold voltage difference, and y-axis represents the counting (i.e. quantity) of the memory element in each of WL0-WL3 and WL60-WL63 with particular threshold voltage difference.The solid line of Fig. 7 B is with reference to threshold voltage difference measured in corresponding memory element.According to Fig. 7 B, even if after performing 1,000,000 read operations, threshold voltage difference scope in the memory element of WL0-WL3 and WL60-WL63 is from-0.2V to 0.2V, and this represents that the memory element at WL0-WL3 and WL60-WL63 is substantially to have restraint (immune) to reading interference.
Comparative example
The memory array with the structure shown in Fig. 2 is to be made into.Memory array is to be reset then to be programmed according to the programming pattern 800 shown in Fig. 8.Programming pattern 800 is similar in programming pattern 400, except the memory element on WL0 and WL63 is erasing unit, so their VT is maintained at EV level.Then, read pressure and be applied to memory array, be same as the mode that aforesaid example is used.The VT of the memory element on WL0-WL3 and WL60-WL63 is with the most measured before pressure is read in application.
Fig. 9 A is shown in before pressure is read in application and the distribution schematic diagram of threshold voltage measured afterwards.In figure 9 a, x-axis represents the numerical value of threshold voltage, and y-axis represents the counting (i.e. quantity) of the memory element in each of WL0-WL3 and WL60-WL63 with particular threshold voltage.The dotted line of Fig. 9 A is with reference to threshold voltage measured in corresponding memory element before read operation, and the solid line of Fig. 9 A is with reference to threshold voltage measured in corresponding memory element after read operation.Fig. 9 B is shown in the distribution schematic diagram of the difference before pressure is read in application and between threshold voltage measured from corresponding memory element afterwards.In figures 9 b and 9, x-axis represents the numerical value of threshold voltage difference, and y-axis represents the counting (i.e. quantity) of the memory element in each of WL0-WL3 and WL60-WL63 with particular threshold voltage difference.The solid line of Fig. 9 B is with reference to threshold voltage difference measured in corresponding memory element.According to Fig. 9 B, the threshold voltage difference scope in the memory element of WL2, WL3, WL60 and WL61 is from-0.2V to 0.2V, and the threshold voltage difference scope in the memory element of WL0, WL1, WL62 and WL63 is from-0.2V to 1V.Therefore, the memory element at WL0, WL1, WL62 and WL63 is affected by reading the interference of pressure application.
In the above-described embodiments, the programming pattern 400 of Fig. 4 comprises only one PV level.But, the present invention is not limited to this.Memory element 220 among memory array 200 has the MLC of multiple PV level, and these a little memory element (comprising limit WL (WL0 and WL63)) can be programmed and have one of them VT of various PV level.In one embodiment, after each programming on limit WL (such as WL0 and WL63), memory element is set at PV ' level, PV ' level is higher than the minimum PV level PVlowest of these a little programming units being positioned between limit WL (such as WL1 to WL62), but is less than Vpass.It is to say, PVlowest ＜ PV ' ＜ Vpass.Therefore, when non-selected WL signal is promoted to Vpass from 0V, compared with between the WL of limit and have the memory cells of minimum PV level PVlowest, the memory cells on the WL of limit can be later switched on.So, the passage of the memory element between the WL of limit can be suspension joint, thus suppresses to read interference.
In the embodiment shown in Figure 2, character string select transistor 250-253 and ground connection select transistor 260 and 261 to be formed as traditional metal-oxide semiconductor (MOS) (metal-oxide-semiconductor, MOS) structure, has gate dielectric and is formed between silicon oxide.Alternatively, character string select transistor 250-253 and ground connection select transistor 260 and 261 can be multilayered memory unit and have structure as shown in Figure 1.In the case, the memory element on SSL290 and GSL280 is to be programmed and have the VT of PV level, and this PV level, less than being applied to the Vcc of SSL290 Yu GSL280, causes them to be switched on also by the application of Vcc.
Memory array 200 as shown in Figure 2, each of memory element 330 has the charge-stroage transistor of electric charge storage layer.Alternatively, each of memory element 220 can be the floating grid transistor with floating-gate.The most alternatively, memory array 200 can comprise multiple first charge-stroage transistor and multiple second floating grid transistors.
Furthermore, the present invention is not limited to the mechanism that specifically biases for wiping/reset operation, programming operation and read operation as described in above-described embodiment.It is to say, various volume pressure situations can be implemented for, erasing/reset operation, programming operation and read operation.
In sum, although the present invention is disclosed above with preferred embodiment, and so it is not limited to the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when depending on being as the criterion that appended claims scope is defined.
Claims (21)
1. the operational approach of a memory array, this memory array comprises the multiple memory element (cell) being arranged in multiple row (row) with multiple row (column), the corresponding respective row to these row of plurality of parallel memory character string (memorystring), multiple wordline (wordline) are to arrange and be perpendicular to the plurality of memory character string, each wordline is connected to multiple gate electrodes of a respective column of these row of these memory element, and the method includes:
Perform programming (program) operation, this programming operation is programmed in all these memory element on multiple limits wordline (edgewordline), these limit wordline are positioned on the limit, opposite of this memory array, and this programming operation is according to waiting that being stored in the input data among this memory array programs the multiple select storage units among this memory array, these multiple select storage units are between these limit wordline, after each programming, the threshold voltage of memory element is positioned at programming checking (programverify, a PV) level.
Method the most according to claim 1, further include before performing this programming operation, perform a reset operation, all these memory element among this reset operation this memory array of reset, so that the threshold voltage of each memory element is positioned at an erasing checking (eraseverify, EV) level, this EV level is less than this PV level.
Method the most according to claim 1, wherein these memory element have the multi-level cell memory (multi-levelcell) of multiple PV level, and perform this programming operation and include:
Programming these select storage units between these limit wordline, to have the threshold voltage of various PV level, these PV level include a minimum PV level；And
Programming is positioned at these memory element on these limit wordline, to have higher than the threshold voltage of this minimum PV level of memory element after these programmings between these limit wordline.
Method the most according to claim 1, further includes and performs a read operation after performing this programming operation.
Method the most according to claim 4, wherein this read operation includes:
Precharge (pre-charge) global bit line stray capacitance is to a predetermined level.
Method the most according to claim 5, wherein this read operation further includes to this predetermined level in this global bit line stray capacitance of this precharge:
Apply a read voltage and be chosen wordline to one；And
Apply a conducting voltage (passvoltage) and be higher than this read voltage to these unselected word line remaining, this conducting voltage.
Method the most according to claim 6, wherein,
Apply this read voltage to this selected wordline to include improving to a read voltage level one word line voltage from an initial voltage level；And
Apply this conducting voltage to these unselected word line and include being increased to above a word line voltage from this initial voltage level one admittance voltage level of this read voltage level.
8. an integrated circuit, including:
One memory array, comprise the multiple memory element being arranged in multiple row with multiple row, the corresponding respective row to these row of plurality of parallel memory character string, multiple wordline are to arrange and be perpendicular to the plurality of memory character string, and each wordline is connected to multiple gate electrodes of respective column of these row of these memory element；And
One control circuit, it is configured to this memory array is performed a programming operation, to be programmed in all these memory element in the wordline of multiple limits, these limit wordline are positioned on the limit, opposite of this memory array, and according to waiting that being stored in the input data among this memory array programs the multiple select storage units among this memory array, these select storage units are between these limit wordline, and after each programming, the threshold voltage of memory element is positioned at a PV level.
Integrated circuit the most according to claim 8, wherein this control circuit is also configured to before performing this programming operation perform a reset operation, all these memory element among this reset operation this memory array of reset, so that the threshold voltage of each memory element is positioned at an EV level, this EV level is less than this PV level.
Integrated circuit the most according to claim 8, wherein these memory element are single-order memory element (singlelevelcell).
11. integrated circuits according to claim 8, wherein these memory element are multi-level cell memories.
12. integrated circuits according to claim 11, wherein this control circuit is configured and performs this programming operation, it is positioned at these multi-level cell memories on these limit wordline, to have higher than the threshold voltage of the threshold voltage of memory element after each programming between these limit wordline with programming.
13. integrated circuits according to claim 8, wherein these memory element are charge-stroage transistor (chargestoragetransistor).
14. integrated circuits according to claim 8, wherein these memory element are floating grid transistor (floatinggatetransistor).
15. integrated circuits according to claim 8, wherein this control circuit is more configured to after performing this programming operation perform a read operation.
16. integrated circuits according to claim 15, wherein in order to perform this read operation, this control circuit is more configured to be pre-charged a global bit line stray capacitance to a predetermined level.
17. integrated circuits according to claim 16, wherein in order to perform this read operation, after this global bit line stray capacitance of this precharge to this predetermined level, this control circuit is more configured to:
Apply a read voltage and be chosen wordline to one；And
Apply a conducting voltage (passvoltage) and be higher than this read voltage to these unselected word line remaining, this conducting voltage.
18. integrated circuits according to claim 17, wherein,
In order to apply this read voltage to this selected wordline, this control circuit is more configured to improve to a read voltage level one word line voltage from an initial voltage level；And
In order to apply this conducting voltage to these unselected word line, this control circuit is more configured to be increased to above a word line voltage from this initial voltage level one admittance voltage level of this read voltage level.
19. integrated circuits according to claim 17, wherein this memory array comprise more than one limit wordline be positioned at this memory array at least on.
20. 1 kinds of control circuits, are used for operating memory array, and this memory array comprises multiple memory element, and this control circuit includes:
Circuits System (circuitry), it is configured to this memory array is performed a programming operation, to be programmed in all these memory element in the wordline of multiple limits, these limit wordline are positioned on the limit, opposite of this memory array, and according to waiting that being stored in the input data among this memory array programs the multiple select storage units among this memory array, these select storage units are between these limit wordline, and after each programming, the threshold voltage of memory element is positioned at a PV level.
21. methods according to claim 20, wherein these memory element have the multi-level cell memory (multi-levelcell) of multiple PV level, and perform this programming operation and include:
Programming these select storage units between these limit wordline, to have the threshold voltage of various PV level, these PV level include a minimum PV level；And
Programming is positioned at these memory element on these limit wordline, to have higher than the threshold voltage of this minimum PV level of memory element after these programmings between these limit wordline.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105741872A (en) * | 2016-02-02 | 2016-07-06 | 北京时代民芯科技有限公司 | Reinforcement configuration memory array applicable to FPGA for space navigation and configuration method of reinforcement configuration memory array |
| CN108733305A (en) * | 2017-04-13 | 2018-11-02 | 旺宏电子股份有限公司 | Memory device, system and its operating method |
| CN110134367A (en) * | 2018-02-02 | 2019-08-16 | 旺宏电子股份有限公司 | Product item and array for class nerve computing system |
| CN110275694A (en) * | 2018-03-15 | 2019-09-24 | 旺宏电子股份有限公司 | For generating the device and its operating method of long-pending item sum |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201118878A (en) * | 2009-11-27 | 2011-06-01 | Macronix Int Co Ltd | Method and apparatus of performing an erase operation on a memory integrated circuit |
| CN102110474A (en) * | 2009-12-28 | 2011-06-29 | 旺宏电子股份有限公司 | Device and method for performing erasing operation on storage integrated circuit |
| US20120269000A1 (en) * | 2011-04-21 | 2012-10-25 | Mi-Sun Yoon | Non-volatile memory device and program method thereof |
-
2015
- 2015-01-04 CN CN201510001861.6A patent/CN105825887B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201118878A (en) * | 2009-11-27 | 2011-06-01 | Macronix Int Co Ltd | Method and apparatus of performing an erase operation on a memory integrated circuit |
| CN102110474A (en) * | 2009-12-28 | 2011-06-29 | 旺宏电子股份有限公司 | Device and method for performing erasing operation on storage integrated circuit |
| US20120269000A1 (en) * | 2011-04-21 | 2012-10-25 | Mi-Sun Yoon | Non-volatile memory device and program method thereof |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105741872A (en) * | 2016-02-02 | 2016-07-06 | 北京时代民芯科技有限公司 | Reinforcement configuration memory array applicable to FPGA for space navigation and configuration method of reinforcement configuration memory array |
| CN105741872B (en) * | 2016-02-02 | 2019-07-23 | 北京时代民芯科技有限公司 | Reinforcing configurable memory array and configuration method suitable for aerospace FPGA |
| CN108733305A (en) * | 2017-04-13 | 2018-11-02 | 旺宏电子股份有限公司 | Memory device, system and its operating method |
| CN110134367A (en) * | 2018-02-02 | 2019-08-16 | 旺宏电子股份有限公司 | Product item and array for class nerve computing system |
| CN110275694A (en) * | 2018-03-15 | 2019-09-24 | 旺宏电子股份有限公司 | For generating the device and its operating method of long-pending item sum |
| CN110275694B (en) * | 2018-03-15 | 2023-08-22 | 旺宏电子股份有限公司 | Apparatus for generating sum of products and method of operating the same |
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|---|---|
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