CN105789050A - Semiconductor device and manufacturing method therefor - Google Patents
Semiconductor device and manufacturing method therefor Download PDFInfo
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- CN105789050A CN105789050A CN201410822744.1A CN201410822744A CN105789050A CN 105789050 A CN105789050 A CN 105789050A CN 201410822744 A CN201410822744 A CN 201410822744A CN 105789050 A CN105789050 A CN 105789050A
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Abstract
The invention discloses a manufacturing method for a semiconductor device. The manufacturing method comprises the steps of providing an SOI (silicon-on-insulator) substrate, and forming an isolation part in the substrate; forming a device structure on the substrate; forming a cut-through etching hole in the top layer silicon of the substrate; etching and removing at least one part of a buried oxygen layer through the etching hole to at least form a cavity below the gate electrode of the device structure; and forming a back gate dielectric layer and a hole insulation layer on the inner surfaces of the cavity and the etching hole respectively to fill the cavity and the etching hole with a conductive material separately so as to form the back gate and a connecting hole separately. According to the manufacturing method, the back gate is re-formed at the position of at least one part of the buried oxygen layer of the SOI device, so that the regulation of the threshold value voltage of the device is realize; the manufacturing method is simple in process, easy to implement, and high in integration level; and the regulation of the back gate threshold value voltage can be carried out through the thickness and the k value changes of the formed back gate dielectric layer, so that the manufacturing method is high in process controllability.
Description
Technical field
The invention belongs to field of semiconductor manufacture, particularly relate to a kind of semiconductor device and manufacture method thereof.
Background technology
Along with the characteristic size of device constantly reduces, after entering nanoscale especially below 22nm size, the Limits properties closing on Semiconductor Physics device is comed one after another, such as capacity loss, leakage current increase, noise and increasing, latch-up and short-channel effect etc., in order to overcome these problems, SOI (silicon-on-insulator, Silicon-On-Insulator) technology is arisen at the historic moment.
SOI substrate divides thick-layer and thin layer SOI, the thickness of the top layer silicon of thin layer SOI device is less than the width being maximally depleted layer under grid, when the lower thickness of top layer silicon, device changes from part depletion (PartiallyDepletion) to all exhausting (FullyDepletion), when top layer silicon is less than 30nm, for ultra-thin SOI (UltrathinSOI, UTSOI), SOI device all exhausts, the device all exhausted has larger current driving force, steep sub-threshold slope, less short channel, narrow-channel effect and the advantages such as Kink effect is completely eliminated, it is particularly well-suited at a high speed, low pressure, the application of low consumption circuit, ultra-thin SOI becomes the ideal solution of below 22nm dimension process.
Summary of the invention
It is an object of the invention to overcome deficiency of the prior art, it is provided that a kind of semiconductor device and manufacture method thereof, it is achieved integrated with back grid structure SOI device.
For achieving the above object, the technical scheme is that
A kind of manufacture method of semiconductor device, including step:
SOI substrate is provided, substrate is formed isolation；
Substrate is formed device architecture；
The top layer silicon of substrate is formed through etched hole；
By at least part of oxygen buried layer of etched hole erosion removal, at least to form cavity under the grid of device architecture；
The inner surface of cavity and etched hole forms backgate dielectric layer and hole insulating barrier respectively, and carries out the filling of cavity and etched hole respectively with conductive material, to form backgate and connecting hole respectively.
Optionally, the step forming backgate and connecting hole specifically includes:
The inner surface of cavity and etched hole is formed first medium layer；
Deposit the first conductor layer, to fill cavity and to form the first conductor layer on the first medium layer of etched hole；
Etched hole is filled with the second conductor layer.
Optionally, adopt ALD technique, the inner surface of cavity and etched hole is formed first medium layer.
Optionally, described backgate dielectric layer is high K medium material.
Optionally, the device architecture formed on substrate is coated with interlayer dielectric layer；
The step forming etched hole includes: the interlayer dielectric layer of the grid both sides of etched features structure and top layer silicon, to form through etched hole in top layer silicon.
Optionally, the further through oxygen buried layer of this etched hole.
Additionally, present invention also offers a kind of semiconductor device, including:
Bottom silicon and top layer silicon；
Device architecture in top layer silicon；
Backgate between bottom silicon and top layer silicon, backgate includes the backgate dielectric layer in the cavity surface between bottom silicon and top layer silicon and fills the conductor layer of cavity；
Be positioned on backgate, the connecting hole of through top layer silicon, connecting hole includes the hole insulating barrier on hole, hole wall and fills the articulamentum in hole, conductor layer and articulamentum interconnection.
Optionally, backgate dielectric layer is high K medium material.
Optionally, described conductor layer is the first conductor layer.
Optionally, described articulamentum includes the first conductor layer on the insulating barrier of hole, and fills the second conductor layer in hole on the first conductor layer.
The semiconductor device of the present invention and manufacture method, after at least part of oxygen buried layer of SOI substrate is removed, again backgate is formed, realize the adjustment of the threshold voltage to device, simple for process and integrated level is high, and the adjustment of backgate threshold voltage can be carried out by the thickness of backgate dielectric layer formed and the change of k value, process controllability is strong.
Accompanying drawing explanation
In order to be illustrated more clearly that technical scheme of the invention process, the accompanying drawing used required in embodiment will be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 illustrates the flow chart of the manufacture method of the semiconductor device of the present invention；
Fig. 2-Figure 10 manufactures the cross section structure schematic diagram in each manufacture process of semiconductor device according to embodiments of the present invention.
Detailed description of the invention
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but the present invention can also adopt other to be different from alternate manner described here to be implemented, those skilled in the art can do similar popularization when without prejudice to intension of the present invention, and therefore the present invention is not by the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when describing the embodiment of the present invention in detail; for ease of explanation; representing that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.Additionally, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
With reference to shown in Fig. 1, the invention provides the manufacture method of a kind of semiconductor device, including: SOI substrate is provided, substrate is formed isolation；Substrate is formed device architecture；The top layer silicon of substrate is formed through etched hole；By etched hole erosion removal oxygen buried layer, to form cavity；The inner surface of cavity and etched hole forms backgate dielectric layer and hole insulating barrier respectively, and carries out the filling of cavity and etched hole respectively with conductive material, to form backgate and connecting hole respectively.
The manufacture method of the present invention, by at least part of oxygen buried layer of SOI substrate is removed, then, refill dielectric layer and conductive material, form device with back grid structure, it is achieved the adjustment to the threshold voltage of device, simple for process and integrated level is high, and the adjustment of backgate threshold voltage can be carried out by the thickness of backgate dielectric layer formed and the change of k value, process controllability is strong.
In order to be better understood from technical scheme and technique effect, flow chart Fig. 1 of manufacture method of semiconductor device and specific embodiment below with reference to the present invention are described in detail.
First, in step S01, it is provided that SOI substrate 100, substrate 100 is formed with isolation 106, with reference to shown in Fig. 2.
Common; SOI substrate 100 includes bottom silicon 100-1, oxygen buried layer 100-2 and top layer silicon 100-3 (or claiming silicon on insulator layer); bottom silicon 100-1 acts primarily as the effect supporting substrate; oxygen buried layer 100-2 is insulating barrier; it is generally silicon oxide; top layer silicon 100-3 is used for forming device architecture; in an embodiment of the present invention; this SOI substrate can select the thickness of top layer silicon 100-3 ultra-thin SOI (ETSOI) substrate less than 20nm; the thickness of oxygen buried layer 100-2 would generally at about 30nm, in order to form the device of complete depletion type.
As shown in Figure 2, in the present embodiment, in this substrate 100, have been formed with isolation 106, it is possible to by forming the first mask layer (not shown go out) in top layer silicon, hard mask layer such as silicon oxide Yu silicon nitride, and carry out the etching of substrate, it is etched in the bottom silicon 100-1 of segment thickness, then filled media material, such as silicon oxide, thus forming isolation 106.In more excellent embodiment, it is possible to before filling the dielectric material of isolation, being initially formed barrier layer (not shown go out), this barrier layer and oxygen buried layer 100-2 have Etch selectivity, in order to when subsequent etching oxygen buried layer so that isolation will not be etched.
Then, in step S02, form device architecture 110 on the substrate 100, with reference to shown in Fig. 3.
Concrete, it is possible to technique traditionally forms device architecture 110, it is possible to adopt front gate or rear grid technique.In the present embodiment, after employing, grid technique forms device architecture, first, top layer silicon 100-3 is formed gate dielectric layer and pseudo-grid (not shown go out) and side wall thereof, gate dielectric layer can be thermal oxide layer or other suitable dielectric materials, for instance silicon oxide, silicon nitride etc., in one embodiment, can be silicon dioxide, it is possible to formed by the method for CVD.Pseudo-grid can be non-crystalline silicon, polysilicon etc., in one embodiment, it is possible to for non-crystalline silicon, dummy grid is formed in the region of remaining first semiconductor layer.Side wall 114 can have single or multiple lift structure, can by silicon nitride, silicon oxide, silicon oxynitride, carborundum, fluoride-doped silica glass, low k dielectric material and combination thereof, and/or other suitable materials are formed, side wall 114 can be the double-layer structure of silicon nitride and silicon oxide in one embodiment.
Then, form source-drain area in pseudo-grid both sides, in one embodiment, on top layer silicon 100-3, formed the source-drain area 116 of extension by epi dopant, and on source-drain area 116, form metal silicide layer (not shown go out).It is of course also possible to form source-drain area in top layer silicon by ion implanting.
Then, cover interlayer dielectric layer in pseudo-grid both sides and pass through wet etching, remove pseudo-grid and gate dielectric layer, lay equal stress on and be newly formed gate dielectric layer and grid 112, this gate dielectric layer can be high K medium material (such as, compare with silicon oxide, there is the material of high-k) or other suitable dielectric materials, high K medium material such as hafnio oxide, this grid can be able to be one or more layers structure for metal gate electrode, can including metal material or polysilicon or their combination, metal material is Ti, TiAl such asx、TiN、TaNx、HfN、TiCx、TaCxEtc..In the present invention, interlayer dielectric layer can select have the material of Etch selectivity with oxygen buried layer 100-2, in the present embodiment, it is possible to for silicon nitride.
Thus, the top layer silicon 100-3 of substrate defines device architecture 110, after forming device architecture, continue dielectric layer 120 between device upper caldding layer, it it is such as silicon nitride, as it is shown on figure 3, the embodiment being here formed as device architecture is merely illustrative, it is possible to form arbitrarily required device architecture as required.
Then, in step S03, the top layer silicon 100-3 of substrate forms through etched hole 124, with reference to shown in Fig. 5.
In the present embodiment, before forming the step of contact hole, being initially formed etched hole, etched hole is formed in the top layer silicon of the grid both sides of device architecture.
Concrete, in the present embodiment, as shown in Figure 4, interlayer dielectric layer 120 forms the second mask layer 122, such as photosensitive etching agent, under the covering of the second mask layer 122, the interlayer dielectric layer 120 of the grid both sides of etched features structure, metal silicide layer (not shown go out), source-drain area 116 and top layer silicon 100-3, oxygen buried layer 100-2, it is also possible to the substrate 100-1 of over etching part further, thus forming etched hole 124, as schemed and removing the second mask layer 122, as shown in Figure 5.In other embodiments, when forming etched hole 124, it is possible to perform etching from interlayer dielectric layer, until exposing oxygen buried layer 100-2, i.e. the not through oxygen buried layer 100-2 of etched hole, whole oxygen buried layer 100-2 completes in the follow-up step removed and form vestibule.
Then, in step S04, by least part of oxygen buried layer 100-2 of etched hole 124 erosion removal, at least to form cavity 130 under the grid of device architecture, with reference to shown in Fig. 6.
In the present embodiment, it is possible to adopting wet etching selective removal part oxygen buried layer 100-2, etching agent can adopt HF or BOE.In the present embodiment, by controlling etch period, after etching, eliminate the oxygen buried layer of part under device architecture, retain the oxygen buried layer near isolation 106, between top layer silicon 100-3 and bottom silicon 100-1, define cavity 130, as shown in Figure 6.
106 have in the embodiment on barrier layer in isolation, it is also possible to all remove oxygen buried layer, whole device cavity formed below (not shown go out).
Then, in step S05, the inner surface of cavity and etched hole forms backgate dielectric layer 133 and hole insulating barrier 134 respectively, and carry out the filling of cavity and etched hole respectively with conductive material, to form backgate and connecting hole respectively, with reference to shown in Fig. 8.
nullIn the present embodiment，First，ALD (ald) technique can be passed through，Carry out the deposit of first medium layer 131，First medium layer can be high K medium material (dielectric constant higher than having with silicon oxide)、Low k dielectric materials (dielectric constant more relatively low than having with silicon oxide)、The dielectric material such as oxide or nitride，As shown in Figure 7，This first medium layer 131 is deposited on the inner surface of cavity 130 and on the inner surface of etched hole 124，Thus form respectively the backgate dielectric layer 133 of first medium layer and hole insulating barrier 134 on the inner surface of cavity and etched hole，Then，First carry out the deposit of the first conductor layer 132，ALD technique can be adopted，Material can be TIN or TiAl etc.，Cavity is filled up and is concurrently formed on the first medium layer 131 of inner surface of etched hole 214 by this first conductor layer 132，Then，Carry out the deposit of the second conductor layer 137，To fill etched hole，And planarize，Until exposing interlayer dielectric layer 120，Thus，Define backgate and connecting hole，As shown in Figure 8，Wherein，Backgate includes the backgate dielectric layer 133 on cavity inner surface and fills the first conductor layer 135 of cavity，Connecting hole includes the hole dielectric layer 134 on etched hole inwall、The first conductor layer 136 on hole dielectric layer 134 and fill the second conductor layer 137 of etched hole.
It is biased by connecting hole, thus carrying out the adjustment of backgate threshold voltage.In concrete device, can being carried out the adjustment of backgate threshold voltage by the thickness of backgate dielectric layer formed and the change of k value, process controllability is strong.In a preferred embodiment, backgate dielectric layer is high K medium material, so, defines the dielectric layer of high K medium material under the grid of device and raceway groove so that device is easier to carry out backgate adjustment.
In other embodiments, it would however also be possible to employ additive method carries out the filling of cavity, for instance thermal oxidation method can be adopted to aoxidize so that the inner surface of etched hole and cavity forms oxide, then, carries out the filling of conductor material.
Then, it is possible to carry out the formation contacted, while forming contact, form the connecting line of backgate.In specific embodiment, first, interlayer dielectric layer 120 continues deposit another dielectric layer 122, and planarize, as shown in Figure 9.Then, the etching of contact hole is carried out, then filler metal material, such as W, before filling W, it is possible to be initially formed the lamination of Ti/TiN on the sidewall of contact, and carry out flatening process, until exposing dielectric layer 122, thus, as shown in Figure 10, grid forms gate contact 140, source-drain area is formed source and drain contact 142, and on connecting hole, forms the connecting line 144 of backgate.
So far, the semiconductor device of the present embodiment is defined.In this embodiment, etched hole is formed after device architecture is formed, and before contact is formed, in other embodiments, etched hole can also be formed when other are suitable.
Additionally, present invention also offers the semiconductor device formed by said method, with reference to shown in Figure 10, it is shown that device includes: bottom silicon 100-1 and top layer silicon 100-3；Device architecture on top layer silicon 100-3；Being located at least in the backgate under the grid of device architecture, between bottom silicon 1003 and top layer silicon 100-1, backgate includes the backgate dielectric layer 133 in the cavity surface between bottom silicon and top layer silicon and fills the conductor layer of cavity；Be positioned on backgate, the connecting hole of through top layer silicon, connecting hole includes the hole insulating barrier 134 on hole, hole wall and fills the articulamentum 136,137 in hole, conductor layer 135 and articulamentum interconnection.
Wherein, described conductor layer includes the first conductor layer 135, and described articulamentum includes the first conductor layer 136 on hole insulating barrier 134 and fills the second conductor layer 137 in hole.In a preferred embodiment, backgate dielectric layer is high K medium material, so, defines the dielectric layer of high K medium material under the grid of device and raceway groove so that device is easier to carry out backgate adjustment.
In certain embodiments, in the place near isolation 106, also remaining with the oxygen buried layer 100-2 of part, with reference to shown in Fig. 8, this oxygen buried layer surrounds backgate.In further embodiments, backgate is formed in the lower section of whole device architecture, it does not have oxygen buried layer remains.
In the present invention, the conductor layer of backgate interconnects with articulamentum, namely electrically connects, and then can pass through connecting line 144 and draw, and this connecting line 144 can contact 142 with gate contact 140, source and drain and together be formed, and simple and with existing technique the integrated level of technique is high.
The above, be only presently preferred embodiments of the present invention, and the present invention not does any pro forma restriction.
Although the present invention discloses as above with preferred embodiment, but is not limited to the present invention.Any those of ordinary skill in the art, without departing from, under technical solution of the present invention ambit, may utilize the method for the disclosure above and technology contents and technical solution of the present invention is made many possible variations and modification, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content without departing from technical solution of the present invention, the technical spirit of the foundation present invention, to any simple modification made for any of the above embodiments, equivalent variations and modification, all still falls within the scope of technical solution of the present invention protection.
Claims (10)
1. the manufacture method of a semiconductor device, it is characterised in that include step:
SOI substrate is provided, substrate is formed isolation；
Substrate is formed device architecture；
The top layer silicon of substrate is formed through etched hole；
By at least part of oxygen buried layer of etched hole erosion removal, at least to form cavity under the grid of device architecture；
The inner surface of cavity and etched hole forms backgate dielectric layer and hole insulating barrier respectively, and carries out the filling of cavity and etched hole respectively with conductive material, to form backgate and connecting hole respectively.
2. manufacture method according to claim 1, it is characterised in that the step forming backgate and connecting hole specifically includes:
The inner surface of cavity and etched hole is formed first medium layer；
Deposit the first conductor layer, to fill cavity and to form the first conductor layer on the first medium layer of etched hole；
Etched hole is filled with the second conductor layer.
3. manufacture method according to claim 2, it is characterised in that adopt ALD technique, forms first medium layer on the inner surface of cavity and etched hole.
4. manufacture method according to claim 1, it is characterised in that described backgate dielectric layer is high K medium material.
5. manufacture method according to claim 1, it is characterised in that be coated with interlayer dielectric layer on the device architecture formed on substrate；
The step forming etched hole includes: the interlayer dielectric layer of the grid both sides of etched features structure and top layer silicon, to form through etched hole in top layer silicon.
6. manufacture method according to claim 5, it is characterised in that the further through oxygen buried layer of this etched hole.
7. a semiconductor device, it is characterised in that including:
Bottom silicon and top layer silicon；
Device architecture in top layer silicon；
Being located at least in the backgate under the grid of device architecture, between bottom silicon and top layer silicon, backgate includes the backgate dielectric layer in the cavity surface between bottom silicon and top layer silicon and fills the conductor layer of cavity；
Be positioned on backgate, the connecting hole of through top layer silicon, connecting hole includes the hole insulating barrier on hole, hole wall and fills the articulamentum in hole, conductor layer and articulamentum interconnection.
8. semiconductor device according to claim 7, it is characterised in that backgate dielectric layer is high K medium material.
9. semiconductor device according to claim 7, it is characterised in that described conductor layer is the first conductor layer.
10. semiconductor device according to claim 8, it is characterised in that described articulamentum includes the first conductor layer on the insulating barrier of hole, and fills the second conductor layer in hole on the first conductor layer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106449400A (en) * | 2016-11-09 | 2017-02-22 | 上海华力微电子有限公司 | Method for eliminating short circuit electricity leakage due to front metal layer inside defects |
| CN111290148A (en) * | 2020-02-19 | 2020-06-16 | 联合微电子中心有限责任公司 | Method for manufacturing modulator with SiO2 substrate formed based on wafer bonding and modulator structure thereof |
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| US20110108942A1 (en) * | 2009-11-12 | 2011-05-12 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for producing field effect transistors with a back gate and semiconductor device |
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| US20060189057A1 (en) * | 2003-05-20 | 2006-08-24 | Stmicroelectronics Sa | Integrated electronic circuit comprising superposed components |
| US20090212362A1 (en) * | 2008-02-25 | 2009-08-27 | International Business Machines Corporation | Soi field effect transistor with a back gate for modulating a floating body |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106449400A (en) * | 2016-11-09 | 2017-02-22 | 上海华力微电子有限公司 | Method for eliminating short circuit electricity leakage due to front metal layer inside defects |
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| CN111290148A (en) * | 2020-02-19 | 2020-06-16 | 联合微电子中心有限责任公司 | Method for manufacturing modulator with SiO2 substrate formed based on wafer bonding and modulator structure thereof |
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Application publication date: 20160720 |