CN105489647B - A kind of semiconductor devices and its manufacturing method - Google Patents
A kind of semiconductor devices and its manufacturing method Download PDFInfo
- Publication number
- CN105489647B CN105489647B CN201410478359.XA CN201410478359A CN105489647B CN 105489647 B CN105489647 B CN 105489647B CN 201410478359 A CN201410478359 A CN 201410478359A CN 105489647 B CN105489647 B CN 105489647B
- Authority
- CN
- China
- Prior art keywords
- semiconductor layer
- substrate
- grid
- layer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Thin Film Transistor (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a kind of manufacturing method of semiconductor devices, this method includes：Semiconductor substrate is provided；The first semiconductor layer is formed on section substrate, the second semiconductor layer is formed on substrate and the first semiconductor layer, isolation is formed on substrate, wherein, first semiconductor layer includes the first portion being located in the active area of part and the second portion extended to grid end direction, and first portion is in grid width direction with active area with wide and long more than or equal to grid in the width of grid length direction；Device architecture is formed on the active area of the second semiconductor layer, the grid of device architecture is located on first portion；The etched hole of perforation is formed in the second semiconductor layer on second portion；By the first semiconductor layer of etched hole erosion removal, to form cavity；The filled media material in cavity and etched hole, to be respectively formed buried regions and insulated hole.The present invention realizes the class SOI device with part buried regions by body substrate, and the thickness of buried regions and raceway groove is adjustable.
Description
Technical field
The invention belongs to field of semiconductor manufacture more particularly to a kind of semiconductor devices and its manufacturing methods.
Background technology
Constantly reduce with the characteristic size of device, after nanoscale especially below 22nm sizes are entered, close on
The Limits properties of Semiconductor Physics device are comed one after another, such as capacity loss, leakage current increase, noise and increasing, latch-up and short
Channelling effect etc., in order to overcome the problems, such as these, SOI (silicon-on-insulator, Silicon-On-Insulator) technology is come into being.
SOI substrate divides thick-layer and thin layer SOI, and the thickness of the top layer silicon of thin layer SOI device, which is less than under grid, is maximally depleted layer
Width, when the thickness of top layer silicon is thinning, device exhausts (Fully from part depletion (Partially Depletion) to whole
Depletion) change, be ultra-thin SOI (Ultra thin SOI, UTSOI) when top layer silicon is less than 50nm, SOI device is whole
It exhausts, the device all exhausted has larger current driving force, steep sub-threshold slope, smaller short channel, narrow raceway groove
Effect and the advantages that completely eliminating Kink effects, especially suitable for the application of high speed, low pressure, low consumption circuit, ultra-thin SOI becomes
The ideal solution of below 22nm dimension process.
However, the cost of SOI substrate is higher at present, and the specification of the SOI substrate provided is more single, can not be according to device
Need adjust the thickness of each layer.
The content of the invention
It is an object of the invention to overcome deficiency of the prior art, a kind of semiconductor devices and its manufacturing method are provided,
The class SOI device with part buried regions is realized using body substrate and channel thickness and buried regions thickness are adjustable.
To achieve the above object, the technical scheme is that：
A kind of manufacturing method of semiconductor devices, including step：
Semiconductor substrate is provided；
The first semiconductor layer is formed on section substrate, the second semiconductor layer is formed on substrate and the first semiconductor layer,
Isolation is formed on substrate, wherein, the first semiconductor layer includes the first portion being located in the active area of part and to grid end side
To the second portion of extension, first portion grid width direction and active area with it is wide and grid length direction width at least equal to grid
It is long；
Device architecture is formed on the active area of the second semiconductor layer, the grid of device architecture is located at the first semiconductor layer
On first portion；
The etched hole of perforation is formed in the second semiconductor layer on the second portion of the first semiconductor layer；
By the first semiconductor layer of etched hole erosion removal, to form cavity；
The filled media material in cavity and etched hole, to be respectively formed buried regions and insulated hole.
Optionally, the step of forming the first semiconductor layer and the second semiconductor layer specifically includes：
The first mask layer, and the substrate of etched portions thickness are formed on substrate；
The epitaxial growth of making choice property forms the first semiconductor layer；
Remove the first mask layer；
Epitaxial growth is carried out, forms the second semiconductor layer；
It performs etching, to form isolated groove；
Isolated groove is filled, to form isolation；
Wherein, the first semiconductor layer includes the first portion being located in active area and second extended to grid end
Point.
Optionally, the substrate is silicon substrate, and first semiconductor layer is GexSi1-x, wherein 0<x<1, described second
Semiconductor layer is silicon.
Optionally, by the first semiconductor layer of etched hole erosion removal, to form cavity the step of specifically includes：
Using HF, H2O2、CH3COOH and H2The etching agent of O carries out the first semiconductor layer of erosion removal, to form cavity.
Optionally, specifically included in cavity and etched hole the step of filled media material：
Using ALD techniques or CVD techniques, first medium layer is filled up in the cavities and is formed on the inner wall of etched hole
First medium layer；Second dielectric layer is filled up in etched hole.
Optionally, first semiconductor layer is extended in the part source-drain area of the device architecture in substrate.
In addition, the present invention also provides the semiconductor devices formed by the above method, including：
Semiconductor substrate；
Buried regions in Semiconductor substrate；
The second semiconductor layer on buried regions and substrate, wherein, buried regions include be located at part active area in first portion and
The second portion extended to grid end, first portion are more than with width and in grid width direction and active area in the width of grid length direction
It is or long equal to grid；
Device architecture on the active area of the second semiconductor layer, the grid of device architecture be located at buried regions first portion it
On；
The insulated hole of the second semiconductor layer of perforation on the second portion of buried regions.
Optionally, buried regions is first medium layer, and the dielectric material of the insulated hole includes the first medium layer on the inner wall of hole
With the second dielectric layer in filling hole.
Optionally, the first medium layer is high K medium material, and second dielectric layer is silica.
Optionally, the buried regions is extended in the part source-drain area of the device architecture in substrate.
The manufacturing method of the semiconductor devices of the present invention, in the active area of part and the shape along grid direction of active area
Into the first semiconductor layer of first, second part, then, by being etched in the second semiconductor layer on the second portion
Borrosion hole removes the first semiconductor layer, and filled media material again, can pass through body substrate and realize the class with part buried regions
SOI device, meanwhile, the thickness and channel thickness of buried regions can be distinguished by the thickness of the first, the second semiconductor layer of formation
It is adjusted, meets the needs of different components, it is simple for process.
Description of the drawings
It, below will be to attached drawing needed in the embodiment in order to illustrate more clearly of the technical solution that the present invention is implemented
It is briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, general for this field
For logical technical staff, without creative efforts, other attached drawings are can also be obtained according to these attached drawings.
Fig. 1 shows the flow chart of the manufacturing method of the semiconductor devices of the present invention；
Fig. 2-Figure 11 A be according to the embodiment of the present invention manufacture semiconductor devices each manufacturing process in top view and
AA, BB are to cross section structure schematic diagram.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still the present invention can be with
Implemented using other different from other manner described here, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is from the limitation of following public specific embodiment.
Secondly, combination schematic diagram of the present invention is described in detail, when describing the embodiments of the present invention, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, should not herein
Limit the scope of protection of the invention.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
Refering to what is shown in Fig. 1, the present invention provides a kind of manufacturing method of semiconductor devices, including：Semiconductor substrate is provided；
The first semiconductor layer is formed on section substrate, forms the second semiconductor layer on substrate and the first semiconductor layer, shape on substrate
Into isolation, wherein, what the first semiconductor layer extended including the first portion in the active area of part and to grid end direction
Second portion, first portion is in grid width direction with active area with wide and long more than or equal to grid in the width of grid length direction；
Form device architecture on the active area of two semiconductor layers, the grid of device architecture be located at the first semiconductor layer first portion it
On；The etched hole of perforation is formed in the second semiconductor layer on the first semiconductor layer second portion；By etching pitting corrosion
The first semiconductor layer is removed, to form cavity；The filled media material in cavity and etched hole, to be respectively formed buried regions and insulation
Hole.
In the manufacturing method of the present invention, in the active area of part and active area forms along grid direction
First, the first semiconductor layer of second portion, then, by etched in the second semiconductor layer on the second portion etched hole come
The first semiconductor layer, and filled media material again are removed, can the class SOI devices with part buried regions be realized by body substrate
Part, meanwhile, buried regions thickness and channel thickness can respectively be adjusted by the thickness of the first, the second semiconductor layer of formation
Section, meets the needs of different components, simple for process.
In order to be better understood from technical scheme and technique effect, below with reference to the semiconductor devices of the present invention
Manufacturing method flow chart Fig. 1 and specific embodiment be described in detail.
First, in step S01, Semiconductor substrate 100 is provided, with reference to figure 2, Fig. 2A (AA of Fig. 2 to schematic cross-section) institute
Show.
In embodiments of the present invention, the Semiconductor substrate 100 can be Si substrates, Ge substrates etc..In other embodiment
In, can also be the substrate for including other elements semiconductor or compound semiconductor, such as GaAs, InP or SiC etc. can be with
For laminated construction, such as Si/SiGe etc..In the present embodiment, the Semiconductor substrate 100 is body silicon substrate.
Then, in step S02, the first semiconductor layer 106 is formed on section substrate, in 100 and first semiconductor of substrate
The second semiconductor layer 108 is formed on layer 106, isolation 110 is formed on substrate, wherein, the first semiconductor layer 106 includes being located at part
First portion 106-1 in the active area and second portion 106-2 to the extension of grid end direction, first portion 106-1 is in grid
Cross direction is with width and long more than or equal to grid in the width of grid length direction with active area, with reference to figure 6, Fig. 6 A and Fig. 6 the B (AA of Fig. 6
With BB to schematic cross-section).
In the present embodiment, selective epitaxial may be employed and form the first semiconductor layer, then pass through epitaxial growth technology
The second semiconductor layer is formed, to form the semiconductor layer of crystal structure.
Specifically, first, deposit the first mask layer 102 on the substrate 100, the first mask can be silica, silicon nitride,
Silicon oxynitride or their lamination etc., and photosensitive etching agent 104 is formed on the first mask layer 102, as best seen in figs. 2 and 2；
Then, the etching of the first mask layer 102 is carried out under the cover of photosensitive etching agent 104, to form patterned first mask layer,
And photosensitive etching agent 104 is removed, under the cover of the first mask layer 102, certain thickness substrate 100 is further etched, is being served as a contrast
The forming region for being subsequently formed the first semiconductor layer is formd on bottom, such as Fig. 3 and Fig. 3 A (AA of Fig. 3 to schematic cross-section) institute
Show.
Then, making choice property epitaxial growth (EPI) forms the first semiconductor layer on the region after substrate etching, such as
Shown in Fig. 4 and Fig. 4 A (AA of Fig. 4 to schematic cross-section), which can be GexSi1-x, wherein 0<x<1, thickness
Can be 1-200nm, it typically can be with 10nm or 20nm；Then, the first mask layer 102 is removed, and carries out epitaxial growth
Two semiconductor layers, in this way, the second semiconductor layer 108 is all formd in 100 and first semiconductor layer 106 of substrate, such as Fig. 5 and Fig. 5 A
Shown (AA of Fig. 5 to schematic cross-section), second semiconductor layer 108 can be Si, and thickness can be 3-200nm, typically
Can be 10nm or 15nm.
Then, refering to what is shown in Fig. 6, forming isolation 110 on substrate, specifically, first being formed on the second semiconductor layer 108
Patterned second mask (not shown), and perform etching, subregion etches the second semiconductor layer and substrate, subregion
The first and second semiconductor layers and substrate are etched, until etching into the substrate of certain depth, isolated groove is formed, and is isolated
The filling of groove then removes the second mask, so as to form isolation 110.
In the present invention, by isolating the region of the first and second semiconductor layers limited in 110, with reference to shown in figure 6 and 6B,
Only part is active area 109, and for forming semiconductor device structure, the first semiconductor layer 106 only has first portion 106-1 and formed
In the active area 109 of part, first portion 106-1 is more than with width and in grid width direction and active area in the width of grid length direction
Or it is long equal to grid, in this way, after formation of the gate so that first portion can separate raceway groove and substrate on grid length direction, with
Continue after an action of the bowels at least square into buried regions under the channel, more preferably, it is long which in the width of grid length direction can be slightly larger than grid,
And it is extended slightly above to source-drain area.Second portion 106-2 is formed on the direction that grid end extends namely on grid width direction.
Second portion can be the end extension of the end or both ends of one end to grid, in the present embodiment, it is preferred that this second
106-2 is divided to extend to the end of one end of grid, which is the opposite end with forming gate contact.
Epitaxy technique can form the semiconductor layer of crystal, be the higher semiconductor layer of quality, to improve follow-up institute's shape
Into device performance.Of course, it is possible to according to the specific needs of device, led using other methods to form the first and second half
Body layer.
Then, in step S03, device architecture 200, device architecture are formed on the active area 109 of the second semiconductor layer 108
Grid 112 be located on first portion 106-1, with reference to shown in figure 7 and Fig. 7 A (AA of Fig. 7 to schematic cross-section).
Device architecture 200 can be formed according to traditional technique, front gate or rear grid technique may be employed.In the present embodiment
In, device architecture is formed using rear grid technique, first, gate dielectric layer is formed on the second semiconductor layer 108 and pseudo- grid (are schemed not
Show) and its side wall, gate dielectric layer can be thermal oxide layer or other suitable dielectric materials, such as silica, silicon nitride etc.,
In one embodiment, it can be silica, can be formed by the method for thermal oxide.Pseudo- grid can be non-crystalline silicon, more
Crystal silicon or silica etc. can be non-crystalline silicon in one embodiment.Side wall 114 can be with single or multiple lift structure, can be with
By silicon nitride, silica, silicon oxynitride, carborundum, fluoride-doped silica glass, low k dielectric material and combinations thereof and/or
Other suitable materials are formed, and side wall 114 can be the double-layer structure of silicon nitride and silica in one embodiment.
Then, source-drain area is formed in pseudo- grid both sides, in one embodiment, in the present embodiment, according to desired device class
Type carries out ion implanting and activates, forms source-drain area 116, certainly, in other embodiments, can also pass through epi dopant
Mode forms source-drain area on the second semiconductor.And metal silicide layer 118 is formed on source-drain area 116.
Then, cover interlayer dielectric layer in pseudo- grid both sides and pass through wet etching, remove pseudo- grid and gate dielectric layer, and again
Formed grid stack 112, grid stack 112 include gate dielectric layer and grid, the gate dielectric layer can be high K medium material (for example, and
Silica is compared, and has the material of high-k) or other suitable dielectric materials, such as hafnium base oxidation of high K medium material
Object, the grid can be that metal gate electrode can be one or more layers structure, can include metal material or polysilicon or they
Combination, metal material such as Ti, TiAlx、TiN、TaNx、HfN、TiCx、TaCxEtc..
So as to, device architecture is formd on the second semiconductor layer, it is merely illustrative to be here formed as the embodiment of device architecture,
Arbitrary required device architecture can be formed as needed.
So as to form device architecture on the active area of the second semiconductor layer, as shown in Fig. 7 and 7A, be here formed as device
The embodiment of part structure is merely illustrative, can form arbitrary required device architecture as needed.
Then, in step S04, the etched hole of perforation is formed in the second semiconductor layer 108 on second portion 106-2
124, with reference to shown in figure 8 and Fig. 8 B (BB of Fig. 8 to schematic cross-section).
After device architecture is formed, continue the dielectric layer 120 between device upper caldding layer, (AA of Fig. 8 is to section with reference to figure 8A
Schematic diagram) shown in.In the present invention, before the step of forming contact hole, it is initially formed etched hole 124.In the present embodiment, should
Etched hole is formed in the second semiconductor layer 108 on second portion 106-2, penetrates through entire second semiconductor layer, in order to
The etched hole of the later use perforation removes the first semiconductor layer.Specifically, the 3rd mask is formed on interlayer dielectric layer 120
Layer (not shown), such as photosensitive etching agent, under the cover of the 3rd mask layer, etching interlayer dielectric layer 120, the second semiconductor layer
108 and first semiconductor layer 106, can also further over etching part substrate 100, so as to form etched hole 124, and remove
3rd mask, as shown in Figure 8 B.In other embodiments, when forming etched hole, can also be carved from interlayer dielectric layer 120
Erosion, until exposing the first semiconductor layer, i.e., and without the etching of the first semiconductor layer 106, but in follow-up removal first
Semiconductor layer is formed in the step of cavity and removed together.
Then, in step S05,124 the first semiconductor layer of erosion removal 106 of etched hole, to form cavity 130, ginseng are passed through
It examines (to schematic cross-section, top view is with reference to Fig. 8 by AA and BB) shown in Fig. 9 A and 9B.
In the present embodiment, wet etching may be employed and remove the first semiconductor layer, HF, H may be employed in etching agent2O2、
CH3COOH and H2The mixed solution of O, in one embodiment, using HF (49%):H2O2(30%):CH3COOH (99.8%):
H2O=1:18:27:8 etching agent, until remove all the first semiconductor layer, so as to below device architecture, the second half lead
Cavity 130 is formd between body layer 108 and substrate 100, as illustrated in figures 9a and 9b.
Then, in step S06, the filled media material in cavity 130 and etched hole 124, be respectively formed buried regions 131 and
Insulated hole 133, with reference to shown in figure 10A and 10B (to schematic cross-section, top view omits by AA and BB).
In the present embodiment, it is possible, firstly, to by ALD (atomic layer deposition) or CVD (chemical vapor deposition) technique, carry out
The filling of first medium material, the first medium material can be Jie of oxide material or high K medium material or other insulation
Material, when filling up cavity formation first medium layer 131, also deposition has the first medium layer on the inner wall of etched hole 124, such as
(BB is omitted to schematic cross-section, top view) shown in Figure 10 B；Then, etched hole 124 is filled with second medium material, second is situated between
Material can be the dielectric materials such as silica, and be planarized, until exposure interlayer dielectric layer 120, the shape in etched hole
Into second dielectric layer 132, so as to form buried regions 131 with first medium material filling cavity, with the first and second dielectric materials
Filling etched hole 124 forms insulated hole 133, as shown in Figure 10 B.
In an embodiment of the present invention, the first semiconductor layer 106 of formation is extending to source-drain area 116 along grid length direction
In, in this way, after first semiconductor layer and filled media material formation buried regions 131 is removed, buried regions extends to the portion in substrate
Divide in source-drain area 116.The advantages of this causes, which possesses part ETSOI, but can to avoid in ETSOI flows because of RSD
The process complexity and parasitic capacitance that (promoting source and drain, Raised Source Drain) brings, and reduce the first semiconductor
The area of layer corrosion is easier to control for etching process.
In other embodiments, the filling of cavity can also be carried out using other methods, such as thermal oxide may be employed
Method is aoxidized so that the oxide material of substrate and the second semiconductor layer fills up cavity, then, performs etching the filling in hole.
Then, other necessary techniques can be carried out.
The 5th mask layer (not shown) can be formed on interlayer dielectric layer 120, in the 5th mask according to common process
Under the masking of layer, the etching of interlayer dielectric layer is performed etching, forms contact hole (not shown)；Then, metal material is carried out
Filling, and planarized, until exposure interlayer dielectric layer 120, to form source and drain contact 142 and gate contact 144, reference chart
Shown in 11 and Figure 11 A (AA of Figure 11 to schematic cross-section).
So far the semiconductor devices of method constructed in accordance is formd.It, should with reference to shown in figure 11, Figure 11 A and Figure 10 B
Semiconductor devices includes：Semiconductor substrate 100；Buried regions 131 in Semiconductor substrate 100；On buried regions 131 and substrate 100
Two semiconductor layers 108, wherein, buried regions 131 includes the first portion 106-1 being located in the active area of part and extends to grid end
Second portion 106-2, first portion is in grid width direction and active area with wide and be greater than or equal to grid in the width of grid length direction
It is long；Device architecture 200 on the active area of the second semiconductor layer 108, the grid 112 of device architecture are located at first of buried regions
Divide on 106-1；The insulated hole 133 of the second semiconductor layer of perforation 108 on the second portion 106-2 of buried regions.
In an embodiment of the present invention, buried regions 131 be first medium layer, the medium of the dielectric material of the insulated hole 133
Material includes the second dielectric layer 132 of the first medium layer 131 and filling etched hole on etched hole inner wall, such as first medium layer
Can be high K medium material, second dielectric layer can be silica.
In an embodiment of the present invention, buried regions 131 is extended in the part source-drain area 116 of the device architecture in substrate 100.
The above described is only a preferred embodiment of the present invention, not make limitation in any form to the present invention.
Although the present invention has been disclosed in the preferred embodiments as above, the present invention is not limited to.It is any to be familiar with ability
The technical staff in domain, without departing from the scope of the technical proposal of the invention, all using in the methods and techniques of the disclosure above
Appearance makes technical solution of the present invention many possible changes and modifications or is revised as the equivalent embodiment of equivalent variations.Therefore,
Every content without departing from technical solution of the present invention, technical spirit according to the invention is to made for any of the above embodiments any simple
Modification, equivalent variations and modification, in the range of still falling within technical solution of the present invention protection.
Claims (10)
1. a kind of manufacturing method of semiconductor devices, which is characterized in that including step：
Semiconductor substrate is provided；
The first semiconductor layer is formed on section substrate, the second semiconductor layer, substrate are formed on substrate and the first semiconductor layer
It is upper to form isolation, wherein, the first semiconductor layer includes the first portion being located in the active area of part and prolongs to grid end direction
The second portion stretched, first portion is in grid width direction with active area with wide and long more than or equal to grid in the width of grid length direction；
Device architecture is formed on the active area of the second semiconductor layer, the grid of device architecture is located at the first of the first semiconductor layer
On part；
The etched hole of perforation is formed in the second semiconductor layer on the second portion of the first semiconductor layer；
By the first semiconductor layer of etched hole erosion removal, to form cavity；
The filled media material in cavity and etched hole, to be respectively formed buried regions and insulated hole.
2. manufacturing method according to claim 1, which is characterized in that form the first semiconductor layer and the second semiconductor layer
Step specifically includes：
The first mask layer, and the substrate of etched portions thickness are formed on substrate；
The epitaxial growth of making choice property forms the first semiconductor layer；
Remove the first mask layer；
Epitaxial growth is carried out, forms the second semiconductor layer；
It performs etching, to form isolated groove；
Isolated groove is filled, to form isolation；
Wherein, the first semiconductor layer includes the first portion being located in active area and the second portion extended to grid end.
3. manufacturing method according to claim 2, which is characterized in that the substrate be silicon substrate, first semiconductor
Layer is GexSi1-x, wherein 0<x<1, second semiconductor layer is silicon.
4. manufacturing method according to claim 3, which is characterized in that by the first semiconductor layer of etched hole erosion removal,
The step of to form cavity, specifically includes：
Using HF, H2O2、CH3COOH and H2The etching agent of O carries out the first semiconductor layer of erosion removal, to form cavity.
5. manufacturing method according to claim 1, which is characterized in that the step of filled media material in cavity and etched hole
Suddenly specifically include：
Using ALD techniques or CVD techniques, first medium layer is filled up in the cavities and forms first on the inner wall of etched hole
Dielectric layer；Second dielectric layer is filled up in etched hole.
6. manufacturing method according to claim 1, which is characterized in that first semiconductor layer extends to the device in substrate
In the part source-drain area of part structure.
7. a kind of semiconductor devices, which is characterized in that including：
Semiconductor substrate；
Buried regions in Semiconductor substrate；
The second semiconductor layer on buried regions and substrate, wherein, buried regions includes the first portion being located in the active area of part and to grid
The second portion of extreme portion's extension, first portion with width and are more than or wait in the width of grid length direction in grid width direction and active area
It is long in grid；
Device architecture on the active area of the second semiconductor layer, the grid of device architecture are located on the first portion of buried regions；
The insulated hole of the second semiconductor layer of perforation on the second portion of buried regions.
8. semiconductor devices according to claim 7, which is characterized in that buried regions is first medium layer, the insulated hole
Dielectric material includes the first medium layer on the inner wall of hole and the second dielectric layer in filling hole.
9. semiconductor devices according to claim 8, which is characterized in that the first medium layer is high K medium material, the
Second medium layer is silica.
10. semiconductor devices according to claim 7, which is characterized in that the buried regions extends to the device junction in substrate
In the part source-drain area of structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410478359.XA CN105489647B (en) | 2014-09-18 | 2014-09-18 | A kind of semiconductor devices and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410478359.XA CN105489647B (en) | 2014-09-18 | 2014-09-18 | A kind of semiconductor devices and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105489647A CN105489647A (en) | 2016-04-13 |
| CN105489647B true CN105489647B (en) | 2018-06-01 |
Family
ID=55676516
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410478359.XA Active CN105489647B (en) | 2014-09-18 | 2014-09-18 | A kind of semiconductor devices and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105489647B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111370306B (en) * | 2018-12-26 | 2023-04-28 | 中芯集成电路（宁波）有限公司上海分公司 | Manufacturing method of transistor and full-surrounding grid electrode device structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1901228A (en) * | 2005-07-22 | 2007-01-24 | 精工爱普生株式会社 | Semiconductor device and semiconductor device manufacturing method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2952472B1 (en) * | 2009-11-12 | 2012-09-28 | Commissariat Energie Atomique | METHOD FOR PRODUCING FIELD-EFFECT TRANSISTORS WITH A COUNTER-ELECTRODE AND SEMICONDUCTOR DEVICE |
| US8629008B2 (en) * | 2012-01-11 | 2014-01-14 | International Business Machines Corporation | Electrical isolation structures for ultra-thin semiconductor-on-insulator devices |
| US9105577B2 (en) * | 2012-02-16 | 2015-08-11 | International Business Machines Corporation | MOSFET with work function adjusted metal backgate |
-
2014
- 2014-09-18 CN CN201410478359.XA patent/CN105489647B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1901228A (en) * | 2005-07-22 | 2007-01-24 | 精工爱普生株式会社 | Semiconductor device and semiconductor device manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105489647A (en) | 2016-04-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7879675B2 (en) | Field effect transistor with metal source/drain regions | |
| KR101474100B1 (en) | Integrated circuit having a vertical power mos transistor | |
| US9461174B2 (en) | Method for the formation of silicon and silicon-germanium fin structures for FinFET devices | |
| JP5728444B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN112530943A (en) | Semiconductor device and method for manufacturing the same | |
| TW201334184A (en) | Semiconductor devices and methods for manufacturing the same and PMOS transistors | |
| JP2011199287A (en) | Fin field-effect transistor, and method of manufacturing the same | |
| US9142673B2 (en) | Devices and methods of forming bulk FinFETS with lateral seg for source and drain on dielectrics | |
| CN103165459B (en) | Fin formula field effect transistor and preparation method thereof | |
| KR20140008225A (en) | Apparatus and method for power mos transistor | |
| JP2009004425A (en) | Semiconductor device and method of manufacturing semiconductor device | |
| JP2014042008A (en) | Method for manufacturing field-effect semiconductor device | |
| US8609508B2 (en) | Method of fabricating an integrated circuit having a strain inducing hollow trench isolation region | |
| CN105702680B (en) | A kind of semiconductor devices and its manufacturing method | |
| CN105702618B (en) | A kind of semiconductor devices and its manufacturing method | |
| CN106298665B (en) | The manufacturing method of semiconductor devices | |
| CN105489647B (en) | A kind of semiconductor devices and its manufacturing method | |
| CN106328501B (en) | The manufacturing method of semiconductor devices | |
| CN105336624B (en) | The manufacturing method of fin formula field effect transistor and its false grid | |
| CN105489492B (en) | A kind of semiconductor devices and its manufacturing method | |
| CN110211882B (en) | Method and structure for fabricating enhanced UTBB FDSOI device | |
| CN105575804B (en) | Fin formula field effect transistor and its manufacturing method | |
| CN105428303B (en) | A kind of manufacturing method of semiconductor devices | |
| CN104347413B (en) | A kind of method making FinFET semiconductor device | |
| CN105489477B (en) | A kind of semiconductor devices and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220317 Address after: Room 108, floor 1, building 4, No. 2 dacuodeng Hutong, Dongcheng District, Beijing 100010 Patentee after: Beijing Zhongke micro Investment Management Co.,Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |