CN105762252B - LED chip structure and a method of manufacturing the same - Google Patents
LED chip structure and a method of manufacturing the same Download PDFInfo
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- CN105762252B CN105762252B CN201410774774.XA CN201410774774A CN105762252B CN 105762252 B CN105762252 B CN 105762252B CN 201410774774 A CN201410774774 A CN 201410774774A CN 105762252 B CN105762252 B CN 105762252B
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Abstract
The invention discloses an LED chip structure, which comprises a first type semiconductor layer, a light-emitting layer and a second type semiconductor layer which are sequentially stacked, wherein the second type semiconductor layer is provided with an exposure area, and part of the first type semiconductor layer is exposed out of the exposure area; a first electrode extension layer on the first semiconductor layer of the exposed region; the second type semiconductor layer is provided with a second electrode extension layer; a transparent insulating layer is connected to the second semiconductor layer, and the transparent insulating layer is filled in the exposed area; the end face of the transparent insulating layer is provided with a first type electrode and a second type electrode; the first type electrode and the second type electrode are respectively connected with the first electrode extension layer and the second electrode extension layer through a first through hole and a second through hole which are arranged on the transparent insulating layer through the first electrode connection layer and the second electrode connection layer; the invention optimizes the arrangement of the electrodes, reduces the working voltage of the chip, increases the effective light-emitting area of the chip and improves the light-emitting efficiency of the chip.
Description
Technical Field
The invention relates to an LED chip structure and a manufacturing method thereof.
Background
The LED has the characteristics of low energy consumption and long service life, and is widely applied to various fields. Recently, with the great improvement of the lighting performance index of the light emitting diode, the LED light emitting diode is rapidly applied and developed in the lighting field.
However, the conventional gallium nitride-based light emitting diode is usually grown on a sapphire substrate, and in the process of manufacturing an electrode, particularly in the process of manufacturing an N-type electrode, a part of P-type semiconductor layer and light emitting layer are required to be etched, and then the N-type electrode is connected to the N-type semiconductor layer.
Disclosure of Invention
The invention aims to solve the technical problem of providing an LED chip structure, which optimizes the arrangement of electrodes, reduces the working voltage of the chip, can increase the effective light-emitting area and effectively improves the light-emitting efficiency of the chip.
In order to achieve the above purpose, the technical scheme of the invention is as follows: an LED chip structure comprises a first type semiconductor layer, a light-emitting layer and a second type semiconductor layer which are sequentially stacked, wherein the second type semiconductor layer is provided with an exposure area, and part of the first type semiconductor layer is exposed by the exposure area;
a first electrode extension layer on the first semiconductor layer of the exposed region;
the second type semiconductor layer is provided with a second electrode extension layer;
a transparent insulating layer is connected to the second semiconductor layer, and the transparent insulating layer is filled in the exposed area;
a first through hole and a second through hole are formed on the transparent insulating layer, the first through hole is positioned in the transparent insulating layer of the exposed area and is communicated with the first electrode extension layer, and the second through hole is communicated with the second electrode extension layer;
at the transparent insulating layer away from the second semiconductor layer the end face is provided with a first type electrode and a second type electrode;
a first electrode connecting layer is arranged in the first through hole and is connected with the first type electrode and the first type electrode; the second through hole is provided with a second electrode connecting layer which is connected with the second electrode extending layer and the second type electrode.
Preferably, the first type semiconductor layer is an N type semiconductor layer, and the second type semiconductor layer is a P type semiconductor layer.
Further improving the structure, a transparent current diffusion layer is arranged between the second semiconductor layer and the transparent insulating layer, and the second electrode extension layer is connected to the transparent current diffusion layer. It can effectively improve the expansion performance of current.
Further improving the structure, there is a reflective layer in the transparent insulating layer under the first type electrode and/or in the transparent insulating layer under the second type electrode. Light emitted from the light emitting layer can be preferably reflected to the outside, and blocking of light by the first type electrode and the second type electrode can be reduced.
Preferably, there are at least two first through holes and/or at least two second through holes.
Preferably, the first electrode extension layer and/or the second electrode extension layer are/is considered to be circular, elongated or annular.
Preferably, the first electrode extension layer and the second electrode extension layer are arranged in a staggered manner.
Preferably, the first electrode extension layer and the second electrode extension layer are arranged in another way, and the first electrode extension layer is regarded as surrounding the second electrode extension layer.
Preferably, the transparent insulating layer has a thickness of greater than 1.2um. The emergent angle of light can be increased by increasing the thickness of the transparent insulating layer, the blocking of the electrode part is reduced, and the light efficiency is further improved.
Preferably, the first type electrode and the second type electrode are substantially the same in height. Is beneficial to flip-chip mounting and mounting.
Preferably, the first type electrode and/or the second type electrode comprises a wire bonding part and an extension part. To facilitate manufacturing.
Preferably, the first electrode connection layer connects the first type electrode extension layer and the extension portion of the first type electrode and/or the second electrode connection layer connects the second electrode extension layer and the extension portion of the second type electrode.
The invention also provides a manufacturing method of the LED chip structure, which comprises the following steps:
sequentially growing a first type semiconductor layer, a light emitting layer and a second type semiconductor layer on a substrate;
removing part of the second type semiconductor layer, the light-emitting layer and the first type semiconductor layer to expose part of the first type semiconductor layer and form an exposed region;
forming a first electrode extension layer on the first semiconductor layer in the exposed region; and generating a second electrode extension layer on the second type semiconductor layer;
generating a transparent insulating layer on the second type semiconductor layer and in the exposed region;
a first through hole and a second through hole are formed on the end face of the transparent insulating layer far away from the second type semiconductor layer, the first through hole exposes the first electrode extension layer to the outside, and the second through hole exposes the second electrode extension layer to the outside;
generating a first electrode connecting layer in the first through hole, wherein the first electrode connecting layer is connected to the first electrode extending layer, generating a second electrode connecting layer in the second through hole, and the second electrode connecting layer is connected to the second electrode extending layer; and generating a first type electrode and a second type electrode on the transparent insulating layer, wherein the first type electrode and the second type electrode are respectively and electrically connected with the first electrode connecting layer and the second electrode connecting layer.
The invention has the following beneficial effects:
1. the first type electrode and the second type electrode are arranged on the end face, far away from the second type semiconductor layer, of the transparent insulating layer, then the first type electrode is connected with the first type semiconductor layer through the first electrode connecting layer and the first electrode extending layer, and the second type electrode is connected with the second type semiconductor layer through the second electrode connecting layer and the second electrode extending layer, so that bridging of the electrodes and the equal heights of the first type electrode and the second type electrode can be conveniently realized, the arrangement positions of the electrodes are very flexible, and the arrangement of the first type electrode and the second type electrode is greatly optimized; meanwhile, the etching area of the second semiconductor layer and the etching area of the light-emitting layer can be reduced, the light-emitting area can be reserved as much as possible, and the light-emitting efficiency of the chip is improved.
2. Through transparent insulating layer, become the electrode setting of single planarization into the three-dimensional electrode setting of multilayer, improve current distribution's wire design, also can increase effective light emitting area, improve the luminous efficacy of chip.
3. Under the condition of limited chip area and etching the semiconductor layer with the same area, more metal wires can be arranged due to the arrangement of the bridging and three-dimensional electrodes, the current diffusion area is increased, the maximum current diffusion effect is achieved, the working voltage of the chip is reduced, the working current is increased, and the luminous efficiency of the chip can be improved.
Drawings
FIG. 1 is a perspective view of a first embodiment of the present invention;
FIG. 2 is a top view of FIG. 1;
FIG. 3 is a cross-sectional view A-A of FIG. 2;
FIG. 4 is a perspective view of a first embodiment of the present invention with the first electrode connecting layer, the first type electrode, the second electrode connecting layer, and the second type electrode hidden;
FIG. 5 is a perspective view of a hidden transparent insulating layer according to a first embodiment of the present invention;
FIG. 6 is a top view of FIG. 5;
FIG. 7 is a perspective view of a first embodiment of the present invention with the transparent insulating layer hidden and without the reflective layer;
FIG. 8 is a perspective view of a second embodiment of the present invention;
FIG. 9 is a perspective view of a hidden transparent insulating layer according to a second embodiment of the present invention;
FIG. 10 is a top view of FIG. 9;
FIG. 11 is a perspective view of a second embodiment of the present invention with the transparent insulating layer hidden and without the reflective layer;
FIG. 12 is a perspective view of a third embodiment of the present invention;
FIG. 13 is a perspective view of a hidden transparent insulating layer according to a third embodiment of the present invention;
FIG. 14 is a top view of FIG. 13;
fig. 15 is a perspective view of a third embodiment of the present invention in which the transparent insulating layer is hidden and the reflective layer is not provided.
Detailed Description
The invention will be described in further detail with reference to the drawings and the detailed description.
In a first embodiment of the present invention, shown in fig. 1 to 6. Fig. 1 is a perspective view of an LED chip structure according to a first embodiment of the present invention, and fig. 2 is a top view of fig. 1. An LED chip structure includes a substrate 10 and a semiconductor stack formed on the substrate 10 by an epitaxial process. The semiconductor laminate includes a first type semiconductor layer 1, a light emitting layer 2, and a second type semiconductor layer 3 stacked in this order, and the substrate 10 may be a Sapphire (Sapphire) substrate, a Silicon (Silicon) substrate, a Silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate. The material of the first type semiconductor layer 1, the light emitting layer 2 and the second type semiconductor layer 3 In the semiconductor laminate comprises at least one element selected from the group consisting of aluminum (Al), gallium (Ga), indium (In), nitrogen (N), phosphorus (P), arsenic (As) and silicon (Si), for example, a semiconductor compound such As AlGaInP, alN, gaN, alGaN, inGaN or AlInGaN. The structure of the light emitting layer 2 may be a single heterostructure (single heterostructure; SH), a double heterostructure (double heterostructure; DH), a double-sided double heterostructure (double-side double heterostructure; DDH) or a multiple quantum well structure (multi-quantum well structure; MQW). The first type semiconductor layer 1 and the second type semiconductor layer 3 are different in electrical property, and in this embodiment, the first type semiconductor layer 1 is an N type semiconductor layer and the second type semiconductor layer 3 is a P type semiconductor layer. Fig. 3 is a cross-sectional view taken along A-A of fig. 2, wherein in fig. 3, the semiconductor stack has an exposed region 30, and the exposed region 30 is formed by removing a portion of the second type semiconductor layer 3, the light emitting layer 2 and the first type semiconductor layer 1 to expose a portion of the first type semiconductor layer 1;
a transparent current diffusion layer 7 is selectively formed over the second semiconductor layer 3, the transparent current diffusion layer 7 being transparent to light emitted from the light emitting layer 2 and increasing current conduction and diffusion. The material may be a conductive material including, but not limited to, indium Tin Oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium Tin Oxide (CTO), antimony Tin Oxide (ATO), aluminum Zinc Oxide (AZO), zinc Tin Oxide (ZTO), gallium Zinc Oxide (GZO), zinc oxide (ZnO), magnesium oxide (MgO), graphene (graphene), or Indium Zinc Oxide (IZO); or a semiconductor material including, but not limited to, aluminum gallium arsenide (AlGaAs), gallium nitride (GaN), or gallium phosphide (GaP).
The first electrode extension layer 11 is formed on the first semiconductor layer 1 of the exposed region 30; the second type semiconductor layer 3 has a second electrode extension layer 31 thereon; for clarity of illustration of the structure of this embodiment, fig. 5 is a perspective view of hiding the transparent insulating layer of fig. 1, and fig. 6 is a top view of fig. 5. Referring to fig. 3 and 6, in the present embodiment, the number of the exposed regions 30 and the first electrode extension layers 11 is considered to be round and two, the number of the exposed regions 30 and the first electrode extension layers 11 may be increased to be plural, and the number of the second electrode extension layers 31 is considered to be elongated and two, and may be increased to be plural according to the purpose of current dispersion. The second electrode extension layer 31 may be provided in a circular or annular shape. The materials of the first electrode extension 11 and the second electrode extension 31 may be metals, such as gold (Au), silver (Ag), copper (Cu), chromium (Cr), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), tin (Sn), and their alloys or their laminated combinations.
A transparent insulating layer 4 is connected to the second semiconductor layer 3, and the transparent insulating layer 4 fills the exposed region 30; preferably, the transparent insulating layer 4 may be Polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), magnesium oxide (MgO), su8, epoxy (Epoxy), acrylic Resin (Acrylic Resin), cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (polyethylenimide), fluorocarbon polymer (Fluorocarbon Polymer), glass (Glass), alumina (Al 2O 3), silicon oxide (SiOx), titanium oxide (TiO 2), tantalum oxide (Ta 2O 5), silicon nitride (SiNx), spin-on Glass (SOG), tetraethoxysilane (TEOS), magnesium fluoride (MgF 2), or a combination of the above materials. The transparent insulating layer 4 may have a single-layer or multi-layer structure composed of the above materials; a first type electrode 5 and a second type electrode 6 are disposed above the transparent insulating layer 4 for electrically connecting with an external power source and a circuit component, and the first type electrode 5 and the second type electrode 6 may each include a wire bonding portion and extension portions 55, 66 extending from the wire bonding portion, respectively.
For clarity of illustration of the structure of this embodiment, FIG. 4 is a perspective view of the first type electrode 5 and the second type electrode 6 of FIG. 1 hidden. In fig. 4, the transparent insulating layer 4 has two first through holes 41 and two second through holes 42, the first through holes 41 are located in the transparent insulating layer 4 of the exposed region 30 and extend to communicate with the first electrode extension layer 11, and the second through holes 42 penetrate through the transparent insulating layer 4 and communicate with the second electrode extension layer 31. That is, the first via 41 and the second via 42 are defined by the transparent insulating layer 4, and the transparent insulating layer 4 surrounds the first via 41 and the second via 42. The diameter of the first through hole 41 and/or the second through hole 42 may be 3um to 20um. The thickness of the transparent insulating layer 4 is preferably larger than 1.2um to reduce the blocking angle of light by the first type electrode 5 and the second type electrode 6 and to radiate as much light to the outside as possible.
Preferably, the heights of the first type electrode 5 and the second type electrode 6 are approximately the same so as to facilitate the flip-chip mounting and the mounting of the LED chip;
referring to fig. 3, a first electrode connection layer 51 is disposed in the first through hole 41, and the first electrode connection layer 51 connects the first type electrode 5 with the first type electrode extension layer 11; a second electrode connection layer 61 is disposed in the second through hole 42, and the second electrode connection layer 61 connects the second electrode extension layer 31 and the second electrode 6; in the present embodiment, the first electrode connection layer 51 is an extension 55 connecting the first type electrode 5, and the second electrode connection layer 61 is an extension 66 connecting the second type electrode 6; the number of the first through holes 41 and the corresponding first electrode connection layers 51 or the second through holes 42 and the corresponding second electrode connection layers 61 is not limited to two, and a better current transmission and current dispersion effect can be achieved through the arrangement of a plurality of through holes and electrode connection layers.
Further optimizing structure, a reflecting layer 52 is arranged in the transparent insulating layer 4 under the first type electrode 5, the shape of the reflecting layer 52 corresponds to the first type electrode 5 and the area is not larger than that of the first type electrode 5, the reflecting layer 52 can be connected with the transparent current diffusion layer 7, and the transparent current diffusion layer 7 at the corresponding position under the first type electrode 5 can be removed, so that the reflecting layer 52 is connected with the second type semiconductor layer 3; similarly, a reflective layer 62 is disposed in the transparent insulating layer under the second type electrode 6, the reflective layer 62 has a shape corresponding to the second type electrode 6 and has an area not larger than that of the first type electrode 6, the reflective layer 62 can be connected to the transparent current diffusion layer 7, and the transparent current diffusion layer 7 at a corresponding position under the second type electrode 6 can be removed to connect the reflective layer 62 to the second type semiconductor layer 3; this can prevent total reflection due to the difference in refractive index between the second semiconductor layer 3 and the transparent current diffusion layer 7, and reflect as much light as possible to the outside.
Of course, the reflective layer may not be provided under the first type electrode 5 and the second type electrode 6, as shown in fig. 7, and fig. 7 is a perspective view of hiding the transparent insulating layer 4 of fig. 1.
In a second embodiment of the present invention, as shown in fig. 8 to 10. For clarity of illustration of the structure of this embodiment, fig. 9 is a perspective view of hiding the transparent insulating layer 4 of fig. 8, and fig. 10 is a top view of fig. 9. The difference from the first embodiment is the arrangement of the electrode extension layer and the via. The exposed region 30 is elongated and is also elongated when viewed from above the first electrode extension layer 11 on the first semiconductor layer 1 in the exposed region 30, and is electrically connected to the extension portion 55 of the first type electrode 5 through the first electrode connection layer 51 in the first via hole; the first electrode extension layer 11 and the second electrode extension layer 31 are alternately arranged, so that current diffusion is enhanced and luminous efficiency of the LED chip is improved.
Similarly, as further shown in fig. 9, a reflective layer 52 may be disposed in the transparent insulating layer 4 under the first type electrode 5, the reflective layer 52 may be shaped corresponding to the first type electrode 5 and have an area not larger than the first type electrode 5, the reflective layer 52 may be connected to the transparent current diffusion layer 7, or the transparent current diffusion layer 7 at a corresponding position under the first type electrode 5 may be removed, so that the reflective layer 52 may be connected to the second type semiconductor layer 3; a reflective layer 62 is disposed in the transparent insulating layer under the second type electrode 6, the reflective layer 62 has a shape corresponding to the second type electrode 6 and has an area not larger than that of the first type electrode 6, the reflective layer 62 is connected to the transparent current diffusion layer 7, and the transparent current diffusion layer 7 at a corresponding position under the second type electrode 6 can be removed to connect the reflective layer 62 to the second type semiconductor layer 3; of course, a reflective layer may not be provided, as shown in fig. 11.
In order to clearly illustrate the structure of this embodiment, fig. 13 is a perspective view of hiding the transparent insulating layer 4 of fig. 12, and fig. 14 is a top view of fig. 13. Unlike the embodiment, the exposed region 30 is also seen as a ring-shaped top view, the first electrode extension layer 11 is electrically connected to the upper first type electrode 5 through the first through holes, the second semiconductor layer has a plurality of second electrode extension layers 31 thereon, and is electrically connected to the plurality of extensions 66 of the upper second type electrode 6 through the plurality of second through holes, and the first electrode extension layer 11 is seen as being disposed around one of the second electrode extension layers 31. Similarly, the two second electrode extension layers 31 at the outermost periphery in the present embodiment may also extend along the periphery of the LED chip to be connected to each other, so that the second electrode extension layers 31 are regarded as surrounding the first electrode extension layer 11.
Similarly, as further shown in fig. 13, a reflective layer 52 may be disposed in the transparent insulating layer 4 under the first type electrode 5, the reflective layer 52 may have a shape corresponding to the first type electrode 5 and an area not larger than the first type electrode 5, the reflective layer 52 may be connected to the transparent current diffusion layer 7, or the transparent current diffusion layer 7 at a corresponding position under the first type electrode 5 may be removed to connect the reflective layer 52 to the second type semiconductor layer 3; a reflective layer 62 is disposed in the transparent insulating layer under the second type electrode 6, the reflective layer 62 has a shape corresponding to the second type electrode 6 and has an area not larger than that of the first type electrode 6, the reflective layer 62 is connected to the transparent current diffusion layer 7, and the transparent current diffusion layer 7 at a corresponding position under the second type electrode 6 can be removed to connect the reflective layer 62 to the second type semiconductor layer 3; of course it is also possible to dispense with a reflective layer, as shown in fig. 15.
In the above-described embodiment, the first electrode extension layer 11 may be configured in a circular shape, an elongated shape, or a ring shape, and likewise, modifications and variations may be made to the above-described embodiment to configure the second electrode extension layer 31 in a circular shape, an elongated shape, or a ring shape without departing from the technical principle and spirit of the present invention.
The manufacturing method for the above embodiment is as follows: a method of fabricating an LED chip structure, comprising the steps of:
growing a first type semiconductor layer 1, a light emitting layer 2, and a second type semiconductor layer 3 in this order in an epitaxial manner on a substrate 10;
etching downwards from the second type semiconductor layer 3 to remove part of the second type semiconductor layer 3, the light emitting layer 2 and the first type semiconductor layer 1 so as to expose part of the first type semiconductor layer 1 and form an exposed region 30;
selectively depositing a transparent current diffusion layer 7 on the second semiconductor layer 3 by vapor deposition, sputtering, or the like, and then removing the transparent current diffusion layer 7 deposited on the exposed region 30 at a position of the transparent current diffusion layer 7 corresponding to the exposed region 30;
forming a first electrode extension layer 11 on the first semiconductor layer 1 in the exposed region 30; simultaneously, a second electrode extension layer 31 is formed on the transparent current diffusion layer 7 according to a pre-designed position and shape; in this case, if a reflective layer is required, the reflective layer 52 and the reflective layer 62 may be formed on the second semiconductor layer 3 or the transparent current diffusion layer 7 before the first electrode extension layer 11 and the second electrode extension layer 31 are formed;
the reflective layer 52 and the reflective layer 62 may be formed on the transparent current diffusion layer 7 at the same time;
then, a transparent insulating layer 4 is formed in the transparent current diffusion layer 7 and the exposed region 30;
etching to form a first through hole 41 and a second through hole 42 at predetermined positions on an end face of the transparent insulating layer 4 remote from the second type semiconductor layer 3, the first through hole 41 exposing the first electrode extension layer 11 to the outside, the second through hole 42 exposing the second electrode extension layer 31 to the outside;
generating a first electrode connection layer 51 and a second electrode connection layer 61 in the first through hole 41 and the second through hole 42 by vapor deposition, sputtering, chemical plating or electroplating, respectively, wherein the first electrode connection layer 51 is connected to the first electrode extension layer 11, and the second electrode connection layer 61 is connected to the second electrode extension layer 31;
a first type electrode 5 and a second type electrode 6 are formed on the transparent insulating layer 4, and the first type electrode 5 and the second type electrode 6 are electrically connected to the first electrode connection layer 51 and the second electrode connection layer 61, respectively.
The above are only preferred embodiments of the present invention, and the present invention is not limited to these embodiments, and the equivalent changes according to the claims by those skilled in the art are intended to fall within the scope of the present invention.
Claims (13)
1. An LED chip structure comprising a first type semiconductor layer, a light emitting layer and a second type semiconductor layer stacked in this order, characterized in that: the second type semiconductor layer is provided with an exposure area, and part of the first type semiconductor layer is exposed by the exposure area;
first type semiconductor of the exposed region a first electrode extension layer is arranged on the layer;
on the second semiconductor layer having a second electrode extension layer;
a transparent insulating layer is connected to the second semiconductor layer, and is filled in the exposed area, and the transparent insulating layer comprises a multilayer structure;
a first through hole and a second through hole are arranged in the transparent insulating layer, the first through hole is positioned in the transparent insulating layer on the exposed area and communicated with the first electrode extension layer, and the second through hole is communicated with the second electrode extension layer;
a first type electrode and a second type electrode are arranged on the end face of the transparent insulating layer far away from the second type semiconductor layer;
a first electrode connecting layer is arranged in the first through hole and is electrically connected with the first electrode extending layer and the first electrode; a second electrode connecting layer is arranged in the second through hole, the second electrode connecting layer is electrically connected with the second electrode extending layer and the second type electrode; and
a reflective layer is provided in the transparent insulating layer under the first type electrode and/or in the transparent insulating layer under the second type electrode.
2. An LED chip structure as set forth in claim 1, wherein: the first type semiconductor layer is an N type semiconductor layer, and the second type semiconductor layer is a P type semiconductor layer.
3. An LED chip structure as set forth in claim 1, wherein: a transparent current diffusion layer is arranged between the second semiconductor layer and the transparent insulating layer, and the second electrode extension layer is connected to the transparent current diffusion layer.
4. An LED chip structure as set forth in claim 1, wherein: the first type electrode and/or the second type electrode comprises a wire bonding part and an extension part, the tail end of the extension part of the first type electrode or the tail end of the extension part of the second type electrode comprises an expansion part, and the expansion part is connected with the first electrode connecting layer or the second electrode connecting layer.
5. An LED chip structure as set forth in claim 1, wherein: at least two first through holes and/or at least two second through holes are arranged.
6. An LED chip structure according to claim 1, the method is characterized in that: the first electrode extension layer and/or the second electrode extension layer are/is considered to be circular, elongated or annular.
7. An LED chip structure as set forth in claim 1, wherein: the first electrode extension layer and the second electrode extension layer are regarded as staggered arrangement.
8. An LED chip structure as set forth in claim 1, wherein: the first electrode extension layer is considered to surround the second electrode extension layer or the second electrode extension layer is considered to surround the first electrode extension layer.
9. An LED chip structure as set forth in claim 1, wherein: the transparent insulating layer the thickness is greater than 1.2um.
10. An LED chip structure as set forth in claim 1, wherein: the first type electrode and the second type electrode have the same height.
11. An LED chip structure as set forth in claim 1, wherein: the first type electrode and/or the second type electrode comprises a wire bonding part and an extension part, wherein the width of the wire bonding part is larger than that of the extension part.
12. An LED chip structure as set forth in claim 11, wherein:
the first electrode connecting layer connects the first type electrode extending layer and the extending part of the first type electrode and/or the second electrode connecting layer connects the second electrode extending layer and the extending part of the second type electrode.
13. A method of fabricating an LED chip structure, comprising the steps of:
sequentially growing a first type semiconductor layer, a light emitting layer and a second type semiconductor layer on a substrate;
removing part of the second type semiconductor layer, the light-emitting layer and the first type semiconductor layer to expose part of the first type semiconductor layer and form an exposed region;
generating a first electrode extension layer on the first type semiconductor layer of the exposed region; and forming a second electrode extension layer on the second type semiconductor layer;
generating a transparent insulating layer on the second type semiconductor layer and in the exposed region;
etching on the end face of the transparent insulating layer far away from the second type semiconductor layer to form a first through hole and a second through hole, wherein the first through hole penetrates through the transparent insulating layer, and the second through hole penetrates through the transparent insulating layer;
generating a first electrode connection layer in the first through hole and generating a second electrode connection layer in the second through hole; and
and generating a first type electrode and a second type electrode on the transparent insulating layer, wherein the first type electrode and the second type electrode are respectively and electrically connected to the first electrode extension layer and the second electrode extension layer through the first electrode connection layer and the second electrode connection layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410774774.XA CN105762252B (en) | 2014-12-16 | 2014-12-16 | LED chip structure and a method of manufacturing the same |
| CN202410121529.2A CN117878211A (en) | 2014-12-16 | 2014-12-16 | LED chip structure and manufacturing method thereof |
| US14/970,519 US10157960B2 (en) | 2014-12-16 | 2015-12-15 | Light-emitting device with electrode extending layer |
| TW104142198A TWI740811B (en) | 2014-12-16 | 2015-12-16 | Light-emitting device |
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| JP2005019530A (en) * | 2003-06-24 | 2005-01-20 | Matsushita Electric Works Ltd | Semiconductor light emitting device |
| CN103222073A (en) * | 2010-08-03 | 2013-07-24 | 财团法人工业技术研究院 | Light emitting diode chip, light emitting diode package structure, and method for forming the same |
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