CN105761687B - Shift register and shift register circuit - Google Patents
Shift register and shift register circuit Download PDFInfo
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- CN105761687B CN105761687B CN201610079202.9A CN201610079202A CN105761687B CN 105761687 B CN105761687 B CN 105761687B CN 201610079202 A CN201610079202 A CN 201610079202A CN 105761687 B CN105761687 B CN 105761687B
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- 238000006073 displacement reaction Methods 0.000 claims description 16
- 230000005611 electricity Effects 0.000 claims description 13
- 239000003990 capacitor Substances 0.000 claims description 12
- 239000004973 liquid crystal related substance Substances 0.000 description 22
- 238000010586 diagram Methods 0.000 description 9
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000001154 acute effect Effects 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- Crystallography & Structural Chemistry (AREA)
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Shift Register Type Memory (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
Shift register and shift register circuit. The shift register circuit comprises N stages of shift registers, wherein the nth stage of shift register comprises a driving circuit, a pull-up circuit and a pull-down circuit. The drive circuit outputs a grid signal of the shift register of the stage according to the main pull-up signal output by the shift register of the (n-1) th stage and the pre-charging pull-up signal output by the shift register of the (n-1-M) th stage. The pull-up circuit outputs a main pull-up signal and an auxiliary pull-up signal of the shift register of the current stage to the (n +1) th stage shift register, and outputs a pre-charged pull-up signal of the shift register of the current stage to the (n +1+ M) th stage shift register. The pull-down circuit pulls down the grid signal and the internal power-saving potential according to the (n-M +2) th stage shift register, the (n-1) th stage shift register, the (n +2) th stage shift register and the potential of the internal node of the shift register.
Description
Technical field
The present invention relates to a kind of shift register circuit, in particular to one kind can support polarity to invert and provide pixel preliminary filling
The shift register circuit of Electricity Functional.
Background technique
In order to avoid the liquid crystal molecule in liquid crystal display because being fixed under the bias of identical polar for a long time, cause
The characteristic of liquid crystal molecule fails and image quality is caused to decline, therefore prior art liquid crystal display can often be inverted using polarity
Method avoids liquid crystal molecule from receiving the bias of identical polar for a long time.For example, the liquid crystal display of the prior art can be
After each frame end cycle, the bias polarity that liquid crystal molecule is received is inverted.And in the liquid crystal display of larger size, it is
It avoids causing crosstalk (crosstalk) with internal signal when inverting acute, therefore the prior art also proposed such as column inversion
The mode of (column inversion) or dot inversion (dot inversion), so that adjacent two column or wantonly two adjacent pixel
Liquid crystal molecule can receive the bias of opposite polarity.
After a polarity reversal, as liquid crystal molecule deflection angle on the contrary, turnaround time required for therefore liquid crystal molecule
It can may also increase therewith.In order to avoid the steering of liquid crystal molecule does not catch up with the speed of content frame update, the prior art can also lead to
The mode for crossing precharge allows pixel before receiving correct data voltage, and receiving in advance will be polar inclined to what is deflected
Pressure, turns to pixel in advance, can so reduce turnaround time required for liquid crystal molecule.In the prior art, if
Liquid crystal display is that polarity reversion is carried out in a manner of column inversion, then since in column inversion, the pixel of same row will be by phase
The bias of same polarity, therefore the shift register circuit in liquid crystal display can be in output grid signal to open one-row pixels
When, while also exporting grid signal to next line pixel to be pre-charged to the liquid crystal molecule in next line pixel.
However if liquid crystal display is that polarity reversion is carried out in a manner of dot inversion, since wantonly two adjacent pixels all can
The bias of opposed polarity is received, therefore the shift register circuit of the above-mentioned liquid crystal display in column inversion can not be applicable in.In addition,
Liquid crystal display is the different demands for meeting various applications, in intended polarity reversion, it is also possible to be come in a manner of other arrangements
Polarity reversion is carried out, so that the function of precharge is not easy to implement.Therefore how to allow shift register circuit that can support anti-comprising column
Turn and other arrangement modes pre-charging functions, become a problem to be solved.
Summary of the invention
One embodiment of the invention provides a kind of shift register, and shift register includes first node, second node, drive
Dynamic circuit, pull-up circuit and pull-down circuit.First node can receive the auxiliary pull up signal of previous stage shift register output, the
Two nodes, can receive previous stage shift register output main pull up signal and preceding (M+1) grade shift register output it is pre-
Pull up signal is filled, M is the integer greater than 3.
Driving circuit is coupled to second node, to the current potential and clock signal Output Shift Register according to second node
Grid signal.Pull-up circuit includes first switch and pull-up output circuit.First switch has first end, second end and control
End, the first end of first switch receives clock signal, the second end of first switch is coupled to third node, and the control of first switch
End processed is coupled to first node.Pull-up output circuit is coupled to third node, and the main pull-up to Output Shift Register is believed
Number, preliminary filling pull up signal and auxiliary pull up signal.
Pull-down circuit is coupled to first node, second node and third node, to (M-2) grade shift register before
Third node current potential and rear second level shift register third node current potential drop-down first node and second node electricity
Position, and according to the current potential of second node and current potential pulldown gate signal, the first segment of the second node of previous stage shift register
The current potential of the third node of point, the second node of shift register and shift register.
Another embodiment of the present invention provides a kind of shift register circuit, and shift register circuit according to not being high potential simultaneously
M clock signal export multiple grid signals, shift register circuit includes N grades of shift registers.In N grades of shift registers
N-th grade of shift register includes: first node, second node, driving circuit, pull-up circuit and pull-down circuit.M is greater than 3
Integer, N is twice of the integer greater than M, and n is the integer greater than M.M grades of two shift LDs are differed in N grades of shift registers
Device can export grid signal according to clock signal identical in M clock signal.
The auxiliary pull up signal of first node reception (n-1) grade shift register output.Second node receives (n-1)
The grade main pull up signal of shift register output and the preliminary filling pull up signal of (n-1-M) grade shift register output.Driving
Circuit is coupled to the second node of n-th grade of shift register, to according to the current potential of the second node of n-th grade of shift register and
One of M clock signal clock signal exports the grid signal of n-th grade of shift register.
Pull-up circuit includes first switch and pull-up output circuit.First switch has first end, second end and control terminal,
The first end of first switch receives clock signal, the second end of first switch is coupled to third node, and the control of first switch
End is coupled to the first node of n-th grade of shift register.Pull-up output circuit is coupled to the third section of n-th grade of shift register
Point, to export the main pull up signal, preliminary filling pull up signal and auxiliary pull up signal of n-th grade of shift register；And
Pull-down circuit is coupled to the first node, second node and third node of n-th grade of shift register, to according to
(n-M+2) the current potential drop-down of the third node of the current potential and (n+2) grade shift register of the third node of grade shift register
The first node of n-th grade of shift register and the current potential of second node, and the electricity of the second node according to n-th grade of shift register
The current potential of the second node of position and (n-1) grade shift register pulls down the grid signal and n-th grade of shifting of n-th grade of shift register
The current potential of the first node of bit register, second node and third node.
Detailed description of the invention
Fig. 1 is the schematic diagram of the shift register circuit of one embodiment of the invention.
Fig. 2 is the schematic diagram of the shift register of the shift register circuit of Fig. 1 of one embodiment of the invention.
Fig. 3 is the operation timing figure of the shift register of Fig. 2 of one embodiment of the invention.
Fig. 4 is the schematic diagram of the shift register of the shift register circuit of Fig. 1 of another embodiment of the present invention.
Fig. 5 is the schematic diagram of the shift register of the shift register circuit of Fig. 1 of another embodiment of the present invention.
[symbol description]
10 shift register circuits
1001、1002、1003、1004、1005、1006, shift register
1007、1008、1009、10010、10011、10012、
100n、100’n
HC1, HC2, HC3, HC4 clock signal
SI initial signal
SQ5、SQ6、SQn、SQ(n-1)Main pull up signal
SR5、SR6、SRn、SR(n-1)Assist pull up signal
SQ’1、SQ’6、SQ’n、SQ’(n-1-M)Preliminary filling pull up signal
R6、Rn、Rm、R(m-1)First node
Q5、Q6、Qn、Q(n-1)Second node
T4、T6、T8、Tn、T(n+2)、T(n-M+2)Third node
110 driving circuits
120 pull-up circuits
122 pull-up output circuits
130 pull-down circuits
132 first drop-down units
134 second drop-down units
LC1 first selection signal
The second selection signal of LC2
VGH high potential
VGL low potential
C1 capacitor
M1 first switch
M2A, M2B second switch
M3A, M3B third switch
M4A, M4B the 4th is switched
M5 the 5th is switched
M6 the 6th is switched
M7 the 7th is switched
M8 the 8th is switched
M9 the 9th is switched
M10 the tenth is switched
M11 the 11st is switched
M12 the 12nd is switched
M13 the 13rd is switched
M14 the 14th is switched
M15 the 15th is switched
M16 sixteenmo closes
M17 the 17th is switched
M18 eighteenmo closes
M19 the 19th is switched
M20 the 20th is switched
M21 the 21st is switched
M22 the 22nd is switched
M23 the 23rd is switched
M24 the 24th is switched
M25 the 25th is switched
The second sixteenmo of M26 closes
M27 the 27th is switched
The second eighteenmo of M28 closes
Gn、G6Grid signal
First period of TP1
Second period of TP2
The TP3 third period
The 4th period of TP4
The 5th period of TP5
The 6th period of TP6
The 7th period of TP7
The 8th period of TP8
Specific embodiment
Fig. 1 is the schematic diagram of the shift register circuit 10 of one embodiment of the invention.Shift register circuit 10 may include N grades of shiftings
Bit register, and multiple grid signal G can be exported for M clock signal of high potential simultaneously according to not1To GN, M is greater than 3
Integer, and N is twice of the integer greater than M.In the embodiment in figure 1, M is 4 and N is 12.
Fig. 3 include shift register circuit 10 received four clock signal HC1 to HC4 timing diagram.In Fig. 3, when
Clock signal HC1 to the HC4 period having the same, and high potential VGH, and clock signal sequentially can be become from low potential VGL in turn
HC1 to HC4 is the time mutual non-overlapping of high potential VGH.In Fig. 1, every level-one shift register can differ from it by M grades of shifting
Bit register receives identical clock signal, such as first order shift register 1001With level V shift register 1005It can be same
Sample receives clock signal HC1, and second level shift register 1002With the 6th grade of shift register 1006When can equally receive
Clock signal HC2, and the rest may be inferred.Certainly, in other embodiments of the invention, shift register circuit can also be according to different number
Clock signal, such as 8,16 clock signals, to export grid signal.
Fig. 2 is n-th grade of shift register 100 in shift register 10nSchematic diagram, n is integer greater than M.N-th grade
Shift register 100nInclude first node Rn, second node Qn, driving circuit 110, pull-up circuit 120 and pull-down circuit 130.
First node RnReceive (n-1) grade shift register (i.e. n-th grade of shift register 100nPrevious stage displacement post
Storage) output auxiliary pull up signal SR(n-1).Second node QnReceive the main pull-up of (n-1) grade shift register output
Signal SQ(n-1)And (n-1-M) grade shift register (i.e. n-th grade of shift register 100nBefore (M+1) grade shift register)
The preliminary filling pull up signal SQ ' of output(n-1-M).For example, in the case where n is 6, (n-1-M) grade shift register is
First order shift register 100 in Fig. 11。
Driving circuit 110 is coupled to n-th grade of shift register 100nSecond node Qn, and can be according to n-th grade of shift LD
Device 100nSecond node QnCurrent potential and n-th grade of shift register 100nReceived clock signal exports n-th grade of displacement and posts
Storage 100nGrid signal Gn.In shift register circuit 10, the 6th grade of shift register 1006Received clock signal
For HC2, and to the 5th grade of shift register 1005For, the 5th grade of shift register 1005Received clock signal is then
HC1。
Pull-up circuit 120 includes first switch M1 and pull-up output circuit 122.First switch M1 has first end, second
End and control terminal.The first end of first switch M1 receives clock signal, and the second end of first switch M1 is coupled to n-th grade of displacement and posts
Storage 100nThird node Tn, and the control terminal of first switch M1 is coupled to n-th grade of shift register 100nFirst node
Rn.Pull-up output circuit 122 is coupled to n-th grade of shift register 100nThird node Tn, to export n-th grade of shift LD
Device 100nMain pull up signal SQn, preliminary filling pull up signal SQ 'nAnd auxiliary pull up signal SRn。
In Fig. 2, pull-up output circuit 122 includes second switch M2A to the 4th switch M4A.Second switch M2A has the
One end, second end and control terminal, the first end of second switch M2A are coupled to n-th grade of shift register 100nThird node Tn,
The second end of second switch M2A exports the auxiliary pull up signal SR of n-th grade of shift register 100nn, and the control of second switch M2A
End processed is coupled to the first end of second switch M2A.Third switch M3A has first end, second end and control terminal, third switch
The first end of M3A is coupled to n-th grade of shift register 100nThird node Tn, n-th grade of the second end output of third switch M3A
Shift register 100nMain pull up signal SQn, and the control terminal of third switch M3A is coupled to the first of third switch M3A
End.4th switch M4A has first end, second end and control terminal, and the first end of the 4th switch M4A is coupled to n-th grade of displacement and posts
Storage 100nThird node Tn, second end n-th grade of shift register 100 of output of the 4th switch M4AnPreliminary filling pull up signal
SQ’n, and the control terminal of the 4th switch M4A is coupled to the first end of the 4th switch M4A.
Pull-down circuit 130 is coupled to n-th grade of shift register 100nFirst node Rn, second node QnAnd third node
Tn, and can be according to (n-M+2) grade shift register (that is, n-th grade of shift register 100nBefore (M-2) grade shift register)
Third node T(n-M+2)Current potential and (n+2) grade shift register (that is, n-th grade of shift register 100nRear two-stage move
Bit register) third node T(n+2)Current potential pull down n-th grade of shift register 100nFirst node RnAnd second node Qn
Current potential, and according to n-th grade of shift register 100nSecond node QnCurrent potential and (n-1) grade shift register (that is,
N grades of shift registers 100nPrevious stage shift register) second node Q(n-1)Current potential pull down n-th grade of shift register
100nGrid signal GnAnd n-th grade of shift register 100nFirst node Qn, second node RnAnd third node TnCurrent potential.
In addition, in Fig. 2, n-th grade of shift register 100nMain pull up signal SQnIt can export to (n+1) grade and shift
Register (that is, n-th grade of shift register 100nRear stage shift register, such as in Fig. 1, the 6th grade of shift register
1006Main pull up signal SQ6It can export to the 7th grade of shift register 1007) second node Q(n+1), n-th grade of shift LD
Device 100nPreliminary filling pull up signal SQ 'nIt can export to (n+1+M) grade shift register (that is, n-th grade of shift register 100n
(M+1) grade shift register later, such as in Fig. 1, the 6th grade of shift register 1006Preliminary filling pull up signal SQ '6It can export
To the tenth level-one shift register 10011) second node Q(n+1+M), and n-th grade of shift register 100nAuxiliary pull up signal
SRnIt can export to (n+1) grade shift register (that is, n-th grade of shift register 100nRear stage shift register, such as
In Fig. 1, the 6th grade of shift register 1006Auxiliary pull up signal SR6It can export to the 7th grade of shift register 1007)
One node R(n+1)。
Puller circuit 130 includes under the 5th switch M5 to the 7th switch M7, the first drop-down unit 132 and second in figure 2 the lower
Draw unit 134.5th switch M5 has first end, second end and control terminal, and the first end of the 5th switch M5 is coupled to n-th grade of shifting
Bit register 100nSecond node Qn, the second end of the 5th switch M5 is to receive low potential VGL, and the control of the 5th switch M5
End processed is coupled to (n-M+2) grade shift register (that is, n-th grade of shift register 100nBefore (M-2) grade shift register)
Third node T(n-M+2).6th switch M6 has first end, second end and control terminal, and the first end of the 6th switch M6 is coupled to
N-th grade of shift register 100nSecond node Qn, the second end reception low potential VGL of the 6th switch M6, and the 6th switch M6
Control terminal is coupled to (n+2) grade shift register (that is, n-th grade of shift register 100nRear two-stage shift register)
Third node T(n+2).7th switch M7 has first end, second end and control terminal, and the first end of the 7th switch M7 is coupled to displacement
Register 100nFirst node Rn, the second end reception low potential VGL of the 7th switch M7, and the control terminal coupling of the 7th switch M7
It is connected to (n+2) grade shift register (that is, n-th grade of shift register 100nRear two-stage shift register) third node
T(n+2)。
In addition, in order to avoid transistor is caused characteristic to fail by the bias fixed for a long time, n-th grade of displacement of Fig. 3
Register 100nCan be stablized in turn using the first mutually symmetrical with drop-down unit 132 of framework and the second drop-down unit 134 or under
Draw the current potential to internal node and output signal.
First drop-down unit 132 includes the 8th switch M8 to the 17th switch M17.8th switch M8 has first end, the
Two ends and control terminal, the first end of the 8th switch M8 can receive first selection signal LC1, and the control terminal of the 8th switch M8 couples
In the first end of the 8th switch M8.9th switch M9 has first end, second end and control terminal, the first end coupling of the 9th switch M9
It is connected to the first end of the 8th switch M8, and the control terminal of the 9th switch M9 is coupled to the second end of the 8th switch M8.Tenth switch
M10 has first end, second end and control terminal, and the first end of the tenth switch M10 is coupled to the second end of the 8th switch M8, and the tenth
The second end of switch M10 can receive low potential VGL, and the control terminal of the tenth switch M10 is coupled to (n-1) grade shift register
(that is, n-th grade of shift register 100nPrevious stage shift register) second node Q(n-1).11st switch M11 has the
One end, second end and control terminal, the first end of the 11st switch M11 are coupled to the second end of the 9th switch M9, the 11st switch
The second end of M11 can receive low potential VGL, and the control terminal of the 11st switch M11 is coupled to (n-1) grade shift register
Second node Q(n-1).12nd switch M12 has first end, second end and control terminal, and the first end of the 12nd switch M12 couples
In the second end of the 8th switch M8, the second end of the 12nd switch M12 can receive low potential VGL, and the control of the 12nd switch M12
End processed is coupled to n-th grade of shift register 100nSecond node Qn.13rd switch M13 has first end, second end and control
End, the first end of the 13rd switch M13 are coupled to the second end of the 9th switch M9, and the second end of the 13rd switch M13 can receive
Low potential VGL, and the control terminal of the 13rd switch M13 is coupled to n-th grade of shift register 100nSecond node Qn.14th
Switch M14 has first end, second end and control terminal, and the first end of the 14th switch M14 is coupled to n-th grade of shift register
100nSecond node Qn, the receivable low potential VGL of the second end of the 14th switch M14, and the control terminal of the 14th switch M14
It is coupled to the second end of the 9th switch M9.15th switch M15 has first end, second end and control terminal, the 15th switch M15
First end be coupled to n-th grade of shift register 100nDriving circuit 110 to receive n-th grade of shift register 100nGrid
Signal Gn, the second end of the 15th switch M15 can receive low potential VGL, and the control terminal of the 15th switch M15 is coupled to the 9th
The second end of switch M9.Sixteenmo, which closes M16, has first end, second end and control terminal, and sixteenmo closes the first end coupling of M16
It is connected to n-th grade of shift register 100nThird node Tn, the receivable low potential VGL of second end of sixteenmo pass M16, and the
The control terminal that sixteenmo closes M16 is coupled to the second end of the 9th switch M9.17th switch M17 have first end, second end and
Control terminal, the first end of the 17th switch M17 are coupled to n-th grade of shift register 100nFirst node Rn, the 17th switch
The second end of M17 can receive low potential VGL, and the control terminal of the 17th switch M17 is coupled to the second end of the 9th switch M9.
Second drop-down unit 134 includes that eighteenmo closes M18 to the 27th switch M27.Eighteenmo, which closes M18, has the
One end, second end and control terminal, the first end that eighteenmo closes M18 can receive the second selection signal LC2, and eighteenmo closes
The control terminal of M18 is coupled to the first end that eighteenmo closes M18.19th switch M19 has first end, second end and control
End, the first end of the 19th switch M19 are coupled to the first end of eighteenmo pass M18, and the control terminal coupling of the 19th switch M19
It is connected to the second end that eighteenmo closes M18.20th switch M20 has first end, second end and control terminal, the 20th switch
The first end of M20 is coupled to the second end that eighteenmo closes M18, and the second end of the 20th switch M20 can receive low potential VGL,
And the control terminal of the 20th switch M20 is coupled to the second node Q of (n-1) grade shift register(n-1).21st switch
M21 has first end, second end and control terminal, and the first end of the 21st switch M21 is coupled to the second of the 19th switch M19
End, the receivable low potential VGL of the second end of the 21st switch M21, and the control terminal of the 21st switch M21 is coupled to the
(n-1) the second node Q of grade shift register(n-1).22nd switch M22 have first end, second end and control terminal, second
The first end of 12 switch M22 is coupled to the second end that eighteenmo closes M18, and the second end of the 22nd switch M22 can receive
Low potential VGL, and the control terminal of the 22nd switch M22 is coupled to n-th grade of shift register 100nSecond node Qn.Second
13 switch M23 have first end, second end and control terminal, and the first end of the 23rd switch M23 is coupled to the 19th switch
The second end of M19, the receivable low potential VGL of the second end of the 23rd switch M23, and the control terminal of the 23rd switch M23
It is coupled to n-th grade of shift register 100nSecond node Qn.24th switch M24 has first end, second end and control
End, the first end of the 24th switch M24 are coupled to n-th grade of shift register 100nSecond node Qn, the 24th switch
The second end of M24 can receive low potential VGL, and the control terminal of the 24th switch M24 is coupled to the second of the 19th switch M19
End.25th switch M25 has first end, second end and control terminal, and the first end of the 25th switch M25 is coupled to n-th
Grade shift register 100nDriving circuit 110 to receive n-th grade of shift register 100nGrid signal Gn, the 25th opens
The second end for closing M25 can receive low potential VGL, and the control terminal of the 25th switch M25 is coupled to the of the 19th switch M19
Two ends.Second sixteenmo, which closes M26, has first end, second end and control terminal, and the first end that the second sixteenmo closes M26 is coupled to the
N grades of shift registers 100nThird node Tn, the receivable low potential VGL of second end of the second sixteenmo pass M26, and the 20th
The control terminal of six switch M26 is coupled to the second end of the 19th switch M19.27th switch M27 has first end, second end
And control terminal, the first end of the 27th switch M27 are coupled to n-th grade of shift register 100nFirst node Rn, the 27th
The second end of switch M27 can receive low potential VGL, and the control terminal of the 27th switch M27 is coupled to the 19th switch M19's
Second end.
N-th grade of shift register 100nDriving circuit 110 include the second eighteenmo close M28 and capacitor C1.28th
Switch M28 has first end, second end and control terminal, and the first end that the second eighteenmo closes M28 can receive clock signal (with the 6th
Grade shift register 1006For, clock signal HC2), the second eighteenmo closes the second end of M28 to export n-th grade of shifting
Bit register 100nGrid signal Gn, and the control terminal that the second eighteenmo closes M28 is coupled to n-th grade of shift register 100n's
Second node Qn.Capacitor C1 has first end and second end, and the first end of capacitor C1 is coupled to the control that the second eighteenmo closes M28
End, and the second end of capacitor C1 is coupled to the second end that the second eighteenmo closes M28.
Fig. 3 is the 6th grade of shift register 100 of Fig. 16Operation timing figure.In the fig. 3 embodiment, first choice is believed
Number LC1 can be maintained at high potential VGH, and the second selection signal LC2 can be maintained at low potential VGL, therefore the 6th grade of shift LD
Device 1006Pull-down circuit mainly depend on the 5th switch M5 to the 7th switch M7 and its first drop-down unit 132 to stablize internal section
The voltage of point.In an embodiment of the present invention, first selection signal LC1 and the second selection signal LC2 can be maintained at high electricity in turn
Position VGH, so that shift register 1006In being stablized in turn using the first drop-down unit 132 or the second drop-down unit 134
The voltage of portion's node, also that is, when the second selection signal LC2 is maintained at high potential VGH, and first selection signal LC1 is maintained at low
When current potential VGL, the pull-down circuit 130 of the 6th grade of shift register 1006 then can by the 5th switch M5 to the 7th switch M7 and its
Second drop-down unit 134 stablizes internal node Rn、QnAnd TnAnd grid signal G6Voltage.
In the first period TP1 of Fig. 3, clock signal HC1 is high potential VGH, and clock signal HC2 is low potential VGL, by
First order shift register 1001The preliminary filling pull up signal SQ ' of output1For high potential VGH, and by level V shift register 1005
The main pull up signal SQ of output5And auxiliary pull up signal SR5Current potential be then floating.Due to the 6th grade of shift register
1006Second node Q6Preliminary filling pull up signal SQ ' can be received1, therefore the 6th grade of shift register 1006Second node Q6Electricity
Position can also be thus lifted to high potential VGH, and charge to capacitor C1.Further, since the second section of level V shift register 1005
Point Q5Also it can be in high potential VGH (in about the first period TP1, twice of 2VGH of second node Q6 current potential), therefore the 6th grade
Shift register 1006The tenth switch M10 to the 13rd switch M13 can all be switched on so that the 14th switch M14 to the tenth
Seven switch M17 can be ended, therefore will not pull down the 6th grade of shift register 1006First node R6And second node Q6's
Current potential.Furthermore fourth stage shift register 1004And the 8th grade of shift register 1008Third node T4And T8It is also in low
Current potential VGL, so the 6th grade of shift register 1006The 5th switch M5 to the 7th switch M7 will not pull down the 6th grade of displacement
Register 1006First node R6And second node Q6Current potential.
In the second period TP2, clock signal HC1 is low potential VGL, and clock signal HC2 is high potential VGH, by first
Grade shift register 1001The preliminary filling pull up signal SQ ' of output1Current potential be floating, and by level V shift register
1005The main pull up signal SQ of output5And auxiliary pull up signal SR5Current potential be also all floating.Clock signal HC2 can lead to
Capacitor C1 is crossed by the 6th grade of shift register 1006Second node Q6Ground to about original current potential twice of high potential
2VGH, and the 6th grade of shift register 1006The grid signal that M28 output has high potential VGH can be closed by the second eighteenmo
G6.In addition, the 6th grade of shift register 1006The tenth switch M10 to the 13rd switch M13 can still be switched on, and the 14th opens
Closing M14 to the 17th switch M17 can still be ended, therefore will not pull down the 6th grade of shift register 1006First node R6And
Second node Q6Current potential.
In third period TP3, clock signal HC1 and HC2 are all low potential VGL, by first order shift register 1001
The preliminary filling pull up signal SQ ' of output1For floating, and by level V shift register 1005The main pull up signal SQ of output5
And auxiliary pull up signal SR5It also is all floating.Due to the 6th grade of shift register 1006Second node Q6Surrounding is not put
Power path, therefore its current potential can still be maintained at high potential VGH, so that the 6th grade of shift register 1006The second eighteenmo close
M28 is persistently switched on, and makes grid signal G in turn6It is pulled down to low potential VGL identical with clock signal HC2.In addition, the
Six grades of shift registers 1006The 12nd switch M12 to the 13rd switch M13 can still be switched on, therefore the 14th switch M14
Can still it be ended to the 17th switch M17, without pulling down the 6th grade of shift register 1006First node R6And second node
Q6Current potential.
In the 4th period TP4, clock signal HC1 and HC2 are all low potential VGL, by first order shift register 1001
The preliminary filling pull up signal SQ ' of output1For floating, and by level V shift register 1005The main pull up signal SQ of output5
And auxiliary pull up signal SR5It also is all floating, however fourth stage shift register 1004Third node T4It then can be in height
Current potential VGH, therefore the 6th grade of shift register 1006The 5th switch M5 can be switched on, and by the 6th grade of shift register 1006
Second node Q6Current potential be pulled down to low potential VGL.6th grade of shift register 1006Second node Q6Current potential can be by under
Draw low potential VGL, therefore the 6th grade of shift register 1006The 12nd switch M12 to the 13rd switch M13 can be ended,
But level V shift register 1005Second node Q5It is still within high potential VGH, therefore the tenth switch M10 to the 11st
Switch M11 can be still switched on, so that the 14th switch M14 to the 17th switch M17 can still be ended, without pulling down the 6th grade
Shift register 1006First node R6And second node Q6Current potential.
In 5th period TP5, clock signal HC1 is high potential VGH, and clock signal HC2 is low potential VGL, by the first order
Shift register 1001The preliminary filling pull up signal SQ ' of output1For floating, and by level V shift register 1005Output
Main pull up signal SQ5And auxiliary pull up signal SR5It is all high potential VGH.Due to the 6th grade of shift register 1006The second section
Point Q6Main pull up signal SQ can be received5, therefore the 6th grade of shift register 1006Second node Q6Current potential can also be elevated
It charges to high potential VGH, and to capacitor C1.Further, since level V shift register 1005Second node Q5It also can be in height
Current potential (in about the first period TP1, second node Q6Twice of 2VGH of current potential), therefore the 6th grade of shift register 1006?
Ten switch M10 to the 13rd switch M13 can be switched on, so that the 14th switch M14 to the 17th switch M17 can be cut
Only, therefore the 6th grade of shift register 1006First node R6And second node Q6Current potential will not all be pulled down.Furthermore by
In the 6th grade of shift register 1006First node R6Auxiliary pull up signal SR can be received5, therefore the 6th grade of shift register
1006First node R6Current potential can also be thus lifted to high potential VGH so that the 6th grade of shift register 1006First switch
M1 is switched on, and to the 6th grade of shift register 1006First switch M1 parasitic capacitance charging.
In the 6th period TP6, clock signal HC1 is low potential VGL, and clock signal HC2 is high potential VGH, by first
Grade shift register 1001The preliminary filling pull up signal SQ ' of output1For floating, and by level V shift register 1005Output
Main pull up signal SQ5And auxiliary pull up signal SR5It is all floating.Due to first node R6With second node Q6Around
Discharge path is had no, therefore first switch M1 and the second eighteenmo close M28 and can still be switched on, clock signal HC2 can pass through capacitor
C1 is by the 6th grade of shift register 1006Second node Q6Ground to about original current potential twice of high potential VGH, and
6th grade of shift register 1006The second end output that M28 can be closed by the second eighteenmo is believed with the grid of high potential VGH
Number G6；Similarly, clock signal HC2 can also pass through the 6th grade of shift register 1006First switch M1 parasitic capacitance by
Six grades of shift registers 1006First node R6Ground to about original current potential twice of high potential VGH, and the 6th grade
Shift register 1006Third node T6Current potential can also be pulled to high potential VGH identical with clock signal HC2.Herein
In the case of, the 6th grade of shift register 1006Second switch M2A, third switch M3A and the 4th switch M4A can all be switched on,
And export the auxiliary pull up signal SR with high potential VGH6, main pull up signal SQ6And preliminary filling pull up signal SQ '6.In addition, the
Six grades of shift registers 1006The tenth switch M10 to the 13rd switch M13 can still be switched on so that the 14th switch
M14 to the 17th switch M17 is ended, therefore the 6th grade of shift register 1006First node R6And second node Q6Electricity
Position will not be all pulled down.
In the 7th period TP7, clock signal HC1 and HC2 are all low potential VGL, by first order shift register 1001
The preliminary filling pull up signal SQ ' of output1For floating, and by level V shift register 1005The main pull up signal SQ of output5
And auxiliary pull up signal SR5It also is all floating.6th grade of shift register 1006Second node Q6Current potential can still keep
In high potential VGH, and the 6th grade of shift register 1006The second eighteenmo close M28 can be switched on so that grid signal G6By under
It is pulled to low potential VGL identical with clock signal HC2.6th grade of shift register 1006First node R6Current potential can still protect
It holds in high potential VGH, and the 6th grade of shift register 1006First switch M1 can be switched on so that the 6th grade of shift register
1006Third node T6Current potential be pulled down to low potential VGL, and thus end the 6th grade of shift register 1006Second open
Close M2A, third switch M3A and the 4th switch M4A.In this way, the 6th grade of shift register 1006The auxiliary of output pulls up letter
Number SR6, main pull up signal SQ6And preliminary filling pull up signal SQ '6Become floating.In addition, the 6th grade of shift register
1006The 12nd switch M12 to the 13rd switch M13 can still be switched on, and the 14th switch M14 to the 17th switch M17 is still
It can be ended, therefore the 6th grade of shift register 100 will not be pulled down6First node R6And second node Q6Current potential.Furthermore
Fourth stage shift register 1004And the 8th grade of shift register 1008Third node T4And T8Also it can be all in low potential VGL,
So the 6th grade of shift register 1006The 5th switch M5 to the 7th switch M7 will not pull down the 6th grade of shift register 1006
First node R6And second node Q6Current potential.
In the 8th period TP8, clock signal HC1 and HC2 are all low potential VGL, by first order shift register 1001
The preliminary filling pull up signal SQ ' of output1For floating, and by level V shift register 1005The main pull up signal SQ of output5
And auxiliary pull up signal SR5It also is all floating, however the 8th grade of shift register 1008Third node T8It then can be in height
Current potential VGH, therefore the 6th grade of shift register 1006The 6th switch M6 and the 7th switch M7 can all be switched on, and then can be by
Six grades of shift registers 1006First node R6And second node Q6Current potential be pulled down to low potential VGL.At this point, the 6th grade of shifting
Bit register 1006The tenth switch M10 to the 13rd switch M13 can be ended, and the 14th switch M14 to the 17th switch
M17 can be then switched on, therefore can be by the 6th grade of shift register 1006First node R6And second node Q6Current potential stablize exist
Low potential VGL, and by the 6th grade of shift register 1006Grid signal G6Stablize in low potential VGL.
It is professed, in the second period TP2, the 6th grade of shift register 1006Grid signal G can first be exported6, so that coupling
In the 6th grade of shift register 1006Pixel be able to carry out precharge, that is, aloow the liquid crystal molecule in pixel preparatory
It turns to, then in the 6th period TP6, the 6th grade of shift register 1006Grid signal G6 can be exported again, be coupled at this time
6th grade of shift register 1006Pixel i.e. can be driven according to data-signal, enable the liquid crystal molecule in pixel rapid
Deflect into corresponding direction.
As long as in this way, select appropriate clock signal quantity, i.e. M according to the characteristic that the demand of system and polarity deflect
Numerical value, that is, may make shift register 100nAccording to (M+1) grade shift register, i.e. (n-1-M) grade shift LD before it
Device, the preliminary filling pull up signal exported export a grid signal G in advancen, reach to liquid crystal molecule precharge in pixel
Effect.
In section Example of the invention, n-th grade of shift register 100nPull-up output circuit 122 second switch
M2A to the 4th switch M4A can also have different connection types from Fig. 2.Fig. 4 is n-th grade of displacement of another embodiment of the present invention
Register 100 'nSchematic diagram.Shift register 100 'nWith shift register 100nStructure it is similar, difference is only that displacement is posted
Storage 100 'nPull-up output circuit 122 ' in, the connection type and shift register of second switch M2B to the 4th switch M4B
100nSecond switch M2A to the 4th switch M4A connection type it is different.
Second switch M2B has first end, second end and control terminal, and the first end of second switch M2B can receive high potential
VGH, the exportable n-th grade of shift register 100 ' of the second end of second switch M2BnAuxiliary pull up signal SRn, and second switch
The control terminal of M2B is coupled to the third node T of 100 ' n of shift registern.Third switch M3B has first end, second end and control
The first end at end processed, third switch M3B can receive high potential VGH, the exportable shift register of second end of third switch M3B
100’nMain pull up signal SQn, and the control terminal of third switch M3B is coupled to shift register 100 'nThird node Tn。
4th switch M4B has first end, second end and a control terminal, the first end of the 4th switch M4B receivable high potential VGH, and the 4th
The preliminary filling pull up signal SQ ' of the exportable 100 ' n of shift register of the second end of switch M4Bn, and the control terminal of the 4th switch M4B
It is coupled to 100 ' n third node T of shift registern。
In addition, in section Example of the invention, preceding M grades of shift registers in shift register circuit 10, i.e., first
Grade shift register 1001To fourth stage shift register 1004, it can be redundancy shift register, and can not be to export grid letter
Number.In the case, the shift LD utensil that M grades of shift registers can be later with (M+1) grade before shift register circuit 10
There is different frameworks.Furthermore in Fig. 1, first order shift register 1001First node, second node and level V displacement
Register 1005Second node can receive synchronous initial signal SI.
Fig. 5 is m grades of shift registers 100 of the shift register circuit 10 of one embodiment of the inventionmSchematic diagram, m is
Integer no more than M.Shift register 100mWith shift register 100nFramework it is similar, the difference is that shift register 100m
Shift register 100 can not includednIn second node QnAnd second node QnThe mutually switch and driving circuit 110 of coupling, also
That is, the shift register 100 of Fig. 5mWith shift register 100nThe difference is that shift register 100mThird can not included to switch
M3A, the 5th switch M5, the 6th switch M6, the 14th switch M14, the 15th switch M15, the 24th switch M24, the 20th
Five switch M25, the second eighteenmo close M28 and capacitor C1.Further, since shift register 100mIt does not include second node, because
This tenth switch M10, the 11st switch M11, the 20th switch M20 and the 21st switch M21 control terminal can be coupled to before
The first node R of level-one shift register(m-1), and the 12nd switch M12, the 13rd switch M13, the 22nd switch M22 and
The control terminal of 23rd switch M23 can be coupled to shift register 100mFirst node Rm。
Since the preceding main function of M grades of shift register is to generate preliminary filling pull up signal to be provided to (M+1) thereafter
The shift register of grade, and grid signal need not be exported into panel pixel, therefore above-mentioned relevant switch can be reduced, to keep away
Exempt to waste material and unnecessary technique can be reduced.Certainly, in section Example of the invention, in shift register circuit 10
Preceding M grades of shift register can also be used and shift register 100nIdentical framework.
In conclusion shift register provided by the embodiment of the present invention can before (M+1) grade shift register
The preliminary filling pull up signal that is exported exports the grid signal of the same level, therefore the effect of can achieve to pixel precharge, and logical
It crosses and selects clock signal quantity appropriate (i.e. the numerical value of M), that is, can ensure that when using different types of polar inversion method, allow
Pixel can receive the voltage of correct polarity to be pre-charged, therefore also increase the elasticity in panel circuit design.
The above description is only a preferred embodiment of the present invention, all equivalent changes made according to the claims of the present invention with repair
Decorations, are all covered by the present invention.
Claims (17)
1. a kind of shift register, includes:
First node, to receive the auxiliary pull up signal of previous stage shift register output；
Second node, to receive the previous stage shift register output main pull up signal and preceding M+1 grades of shift register
The preliminary filling pull up signal of output, M are the integer greater than 3；
Driving circuit is coupled to the second node, exports the displacement to the current potential and clock signal according to the second node and posts
The grid signal of storage；
Pull-up circuit includes:
First switch has first end to receive the clock signal, second end is coupled to third node and control terminal is coupled to
The first node；And
Output circuit is pulled up, the third node is coupled to, to export main pull up signal, the preliminary filling pull-up of the shift register
Signal and auxiliary pull up signal；And
Pull-down circuit is coupled to the first node, the second node and the third node, to according to preceding M-2 grades of shift LD
The current potential of the third node of the current potential of the third node of device and rear second level shift register pulls down the first node and second section
The current potential of point, and the grid is pulled down according to the current potential of the current potential of the second node and the second node of the previous stage shift register
Signal, the first node, the second node of the shift register and the shift register the third node current potential.
2. shift register as described in claim 1, after wherein the main pull up signal of the shift register is output to
The preliminary filling pull up signal of the second node of level-one shift register, the shift register is output to rear M+1 grades of shift LD
This of the second node of device and the shift register auxiliary pull up signal are output to the first segment of the rear stage shift register
Point.
3. shift register as claimed in claim 1 or 2, wherein the pull-up output circuit includes:
Second switch, the third node of the shift register is coupled to first end, and second end is posted to export the displacement
The auxiliary pull up signal and control terminal of storage are coupled to the first end of the second switch；
Third switch, the third node of the shift register is coupled to first end, and second end is posted to export the displacement
Main pull up signal and control terminal of storage are coupled to the first end of third switch；And
4th switch, the third node of the shift register is coupled to first end, and second end is posted to export the displacement
Preliminary filling pull up signal and control terminal of storage are coupled to the first end of the 4th switch.
4. shift register as claimed in claim 1 or 2, wherein the pull-up output circuit includes:
Second switch has first end to receive system high potential, the auxiliary of second end to export the shift register
Pull up signal and control terminal are coupled to the third node of the shift register；
Third switch, has first end to receive the system high potential, the master of second end to export the shift register
Pull up signal and control terminal is wanted to be coupled to the third node of the shift register；And
4th switch, has first end to receive the system high potential, second end to export the shift register this is pre-
It fills pull up signal and control terminal is coupled to the third node of the shift register.
5. shift register as described in claim 1, wherein the pull-down circuit includes:
5th switch, the second node of the shift register is coupled to first end, second end is to receive the low electricity of system
Position and control terminal are coupled to the third node of the preceding M-2 grades of shift register；
6th switch, the second node of the shift register is coupled to first end, and second end is low to receive the system
Current potential and control terminal are coupled to the third node of the rear second level shift register；And
7th switch, the first node of the shift register is coupled to first end, and second end is low to receive the system
Current potential and control terminal are coupled to the third node of the rear second level shift register.
6. shift register as claimed in claim 5, wherein the pull-down circuit also includes:
First drop-down unit includes:
There is 8th switch first end to be coupled to the 8th switch to receive first selection signal, second end and control terminal
The first end；
9th switch is coupled to the first end of the 8th switch with first end, and second end and control terminal are coupled to the 8th
The second end of switch；
Tenth switch, with first end be coupled to the 8th switch the second end, second end to receive the system low potential,
And control terminal is coupled to the second node of the previous stage shift register；
11st switch is coupled to the second end of the 9th switch with first end, and second end is to receive the low electricity of the system
Position and control terminal are coupled to the second node of the previous stage shift register；
12nd switch is coupled to the second end of the 8th switch with first end, and second end is to receive the low electricity of the system
Position and control terminal are coupled to the second node of the shift register；
13rd switch is coupled to the second end of the 9th switch with first end, and second end is to receive the low electricity of the system
Position and control terminal are coupled to the second node of the shift register；
14th switch, the second node of the shift register is coupled to first end, second end is to receive the system
Low potential and control terminal are coupled to the second end of the 9th switch；
There is 15th switch first end to be coupled to the driving circuit to receive the grid signal of the shift register, and second
It holds and is coupled to the second end of the 9th switch to receive the system low potential and control terminal；
Sixteenmo closes, and the third node of the shift register is coupled to first end, second end is to receive the system
Low potential and control terminal are coupled to the second end of the 9th switch；And
17th switch, the first node of the shift register is coupled to first end, second end is to receive the system
Low potential and control terminal are coupled to the second end of the 9th switch.
7. shift register as claimed in claim 6, wherein the pull-down circuit also includes:
Second drop-down unit includes:
Eighteenmo closes, and there is first end to be coupled to the eighteenmo to receive the second selection signal, second end and control terminal
The first end closed；
19th switch, the first end of eighteenmo pass is coupled to first end, second end and control terminal are coupled to this
The second end that eighteenmo closes；
20th switch, the second end of eighteenmo pass is coupled to first end, and second end is low to receive the system
Current potential and control terminal are coupled to the second node of the previous stage shift register；
21st switch is coupled to the second end of the 19th switch with first end, and second end is to receive the system
Low potential and control terminal are coupled to the second node of the previous stage shift register；
22nd switch, the second end of eighteenmo pass is coupled to first end, second end is to receive the system
Low potential and control terminal are coupled to the second node of the shift register；
23rd switch is coupled to the second end of the 19th switch with first end, and second end is to receive the system
Low potential and control terminal are coupled to the second node of the shift register；
24th switch, the second node of the shift register is coupled to first end, and second end is to receive this
System low potential and control terminal are coupled to the second end of the 19th switch；
25th switch, there is first end to be coupled to the driving circuit to receive the grid signal of the shift register, the
Two ends are coupled to the second end of the 19th switch to receive the system low potential and control terminal；
Second sixteenmo closes, and the third node of the shift register is coupled to first end, and second end is to receive this
System low potential and control terminal are coupled to the second end of the 19th switch；And
27th switch, the first node of the shift register is coupled to first end, and second end is to receive this
System low potential and control terminal are coupled to the second end of the 19th switch.
8. shift register as described in claim 1, wherein the driving circuit includes:
Second eighteenmo closes, and has first end to receive the clock signal, second end is to export being somebody's turn to do for the shift register
Grid signal and control terminal are coupled to the second node of the shift register；And
Capacitor is coupled to the control terminal of second eighteenmo pass with first end and second end is coupled to second eighteenmo
The second end closed.
9. a kind of shift register circuit, to be somebody's turn to do according to multiple grid signals are not exported simultaneously for M clock signal of high potential
Shift register circuit includes N grades of shift registers, and n-th grade of shift register in the N grades of shift register includes:
First node, to receive the auxiliary pull up signal of (n-1)th grade of shift register output；
Second node, to receive the main pull up signal and the (n-1)th-M grades of shift LD of (n-1)th grade of shift register output
The preliminary filling pull up signal of device output；
Driving circuit is coupled to the second node of n-th grade of shift register, to according to n-th grade of shift register
Clock signal in the current potential of the second node and the M clock signal exports the grid signal of n-th grade of shift register；
Pull-up circuit includes:
First switch has first end to receive the clock signal, second end is coupled to third node and control terminal is coupled to
The first node of n-th grade of shift register；And
Output circuit is pulled up, the third node of n-th grade of shift register is coupled to, to export n-th grade of shift LD
Main pull up signal, preliminary filling pull up signal and the auxiliary pull up signal of device；And
Pull-down circuit is coupled to the first node, the second node and the third node of n-th grade of shift register, to
According under the current potential of the current potential of the third node of the n-th-M+2 grades of shift register and the third node of the n-th+2 grades shift registers
Draw the first node of n-th grade of shift register and the current potential of the second node, and being somebody's turn to do according to n-th grade of shift register
The current potential of the second node of the current potential of second node and (n-1)th grade of shift register pulls down being somebody's turn to do for n-th grade of shift register
The current potential of the first node of grid signal and n-th grade of shift register, the second node and the third node；
Wherein:
M is the integer greater than 3, and N is twice of the integer greater than M, and n is the integer greater than M；And
It is defeated according to identical clock signal in the M clock signal that M grades of two shift registers are differed in the N grades of shift register
Grid signal out.
10. shift register circuit as claimed in claim 9, wherein main pull up signal quilt of n-th grade of shift register
It exports to the second node of (n+1)th grade of shift register, the preliminary filling pull up signal of n-th grade of shift register is output to the
The second node of n+1+M grades of shift registers and the auxiliary pull up signal of n-th grade of shift register be output to this n-th+
The first node of 1 grade of shift register.
11. the shift register circuit as described in claim 9 or 10, wherein the pull-up of n-th grade of shift register exports electricity
Road includes:
Second switch is coupled to the third node of n-th grade of shift register with first end, second end to export this
The auxiliary pull up signal and control terminal of n grades of shift registers are coupled to the first end of the second switch；
Third switch is coupled to the third node of n-th grade of shift register with first end, second end to export this
Main pull up signal and control terminal of n grades of shift registers are coupled to the first end of third switch；And
4th switch is coupled to the third node of n-th grade of shift register with first end, second end to export this
Preliminary filling pull up signal and control terminal of n grades of shift registers are coupled to the first end of the 4th switch.
12. the shift register circuit as described in claim 9 or 10, wherein the pull-up of n-th grade of shift register exports electricity
Road includes:
Second switch has first end to receive system high potential, and second end is to export being somebody's turn to do for n-th grade of shift register
Auxiliary pull up signal and control terminal are coupled to the third node of n-th grade of shift register；
Third switch, has first end to receive the system high potential, second end is to export n-th grade of shift register
The main pull up signal and control terminal are coupled to the third node of n-th grade of shift register；And
4th switch, has first end to receive the system high potential, second end is to export n-th grade of shift register
The preliminary filling pull up signal and control terminal are coupled to the third node of n-th grade of shift register.
13. shift register circuit as claimed in claim 9, wherein the pull-down circuit of n-th grade of shift register includes:
5th switch, the second node of n-th grade of shift register is coupled to first end, second end is to receive system
Low potential and control terminal are coupled to the third node of the n-th-M+2 grades of shift register；
6th switch, the second node of n-th grade of shift register is coupled to first end, and second end is to receive this
System low potential and control terminal are coupled to the third node of the n-th+2 grades shift registers；And
7th switch, the first node of the shift register is coupled to first end, and second end is low to receive the system
Current potential and control terminal are coupled to the third node of the n-th+2 grades shift registers.
14. shift register circuit as claimed in claim 13, wherein the pull-down circuit of n-th grade of shift register also wraps
Contain:
First drop-down unit includes:
There is 8th switch first end to be coupled to the 8th switch to receive first selection signal, second end and control terminal
The first end；
9th switch is coupled to the first end of the 8th switch with first end, and second end and control terminal are coupled to the 8th
The second end of switch；
Tenth switch, with first end be coupled to the 8th switch the second end, second end to receive the system low potential,
And control terminal is coupled to the second node of (n-1)th grade of shift register；
11st switch is coupled to the second end of the 9th switch with first end, and second end is to receive the low electricity of the system
Position and control terminal are coupled to the second node of (n-1)th grade of shift register；
12nd switch is coupled to the second end of the 8th switch with first end, and second end is to receive the low electricity of the system
Position and control terminal are coupled to the second node of n-th grade of shift register；
13rd switch is coupled to the second end of the 9th switch with first end, and second end is to receive the low electricity of the system
Position and control terminal are coupled to the second node of n-th grade of shift register；
14th switch, the second node of n-th grade of shift register is coupled to first end, second end is to receive this
System low potential and control terminal are coupled to the second end of the 9th switch；
15th switch, there is first end to be coupled to the driving circuit of n-th grade of shift register to receive this n-th grade displacement
The grid signal of register, second end to receive the system low potential and control terminal be coupled to the 9th switch this
Two ends；
Sixteenmo closes, and the third node of n-th grade of shift register is coupled to first end, second end is to receive this
System low potential and control terminal are coupled to the second end of the 9th switch；And
17th switch, the first node of n-th grade of shift register is coupled to first end, second end is to receive this
System low potential and control terminal are coupled to the second end of the 9th switch.
15. shift register circuit as claimed in claim 13, wherein the pull-down circuit of n-th grade of shift register also wraps
Contain:
Second drop-down unit includes:
Eighteenmo closes, and there is first end to be coupled to the eighteenmo to receive the second selection signal, second end and control terminal
The first end closed；
19th switch, the first end of eighteenmo pass is coupled to first end, second end and control terminal are coupled to this
The second end that eighteenmo closes；
20th switch, the second end of eighteenmo pass is coupled to first end, and second end is low to receive the system
Current potential and control terminal are coupled to the second node of (n-1)th grade of shift register；
21st switch is coupled to the second end of the 19th switch with first end, and second end is to receive the system
Low potential and control terminal are coupled to the second node of (n-1)th grade of shift register；
22nd switch, the second end of eighteenmo pass is coupled to first end, second end is to receive the system
Low potential and control terminal are coupled to the second node of n-th grade of shift register；
23rd switch is coupled to the second end of the 19th switch with first end, and second end is to receive the system
Low potential and control terminal are coupled to the second node of n-th grade of shift register；
24th switch, the second node of n-th grade of shift register is coupled to first end, second end is to receive
The system low potential and control terminal are coupled to the second end of the 19th switch；
25th switch, there is first end to be coupled to the driving circuit of n-th grade of shift register to receive this n-th grade shifting
The grid signal of bit register, second end are coupled to the 19th switch to receive the system low potential and control terminal
The second end；
Second sixteenmo closes, and the third node of n-th grade of shift register is coupled to first end, second end is to receive
The system low potential and control terminal are coupled to the second end of the 19th switch；And
27th switch, the first node of n-th grade of shift register is coupled to first end, second end is to receive
The system low potential and control terminal are coupled to the second end of the 19th switch.
16. shift register circuit as claimed in claim 9, wherein the driving circuit of n-th grade of shift register includes:
Second eighteenmo closes, and has first end to receive the clock signal, second end is to export n-th grade of shift register
The grid signal and control terminal be coupled to the second node of n-th grade of shift register；And
Capacitor is coupled to the control terminal of second eighteenmo pass with first end and second end is coupled to second eighteenmo
The second end closed.
17. shift register circuit as claimed in claim 9, wherein m grades of shift register packets in the N grades of shift register
Contain:
First node, to receive the auxiliary pull up signal of m-1 grades of shift register outputs；
Pull-up circuit includes:
There is first switch first end to be coupled to third node to clock signal, the second end received in the M clock signal
And control terminal is coupled to the first node of the m grades of shift registers；And
Output circuit is pulled up, the third node of the m grades of shift registers is coupled to, to export the m grades of shift LDs
The preliminary filling pull up signal and auxiliary pull up signal of device；And
Pull-down circuit is coupled to the first node and the third node of the m grades of shift registers, to according at least this
The current potential of the third node of first node and m+2 grades of shift registers of m grades of shift registers pulls down this m grades displacements and posts
The first node of storage and the current potential of the third node；
Wherein m is the integer no more than M.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104144421 | 2015-12-30 | ||
| TW104144421A TWI562114B (en) | 2015-12-30 | 2015-12-30 | Shift register and shift register circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105761687A CN105761687A (en) | 2016-07-13 |
| CN105761687B true CN105761687B (en) | 2019-01-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610079202.9A Expired - Fee Related CN105761687B (en) | 2015-12-30 | 2016-02-04 | Shift register and shift register circuit |
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| CN (1) | CN105761687B (en) |
| TW (1) | TWI562114B (en) |
Families Citing this family (3)
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|---|---|---|---|---|
| CN106991984B (en) * | 2017-05-12 | 2018-05-18 | 惠科股份有限公司 | Shift register circuit and display panel using the same |
| TWI637371B (en) * | 2017-12-28 | 2018-10-01 | 友達光電股份有限公司 | Shift register circuit |
| CN111192546B (en) * | 2018-11-15 | 2023-08-15 | 群创光电股份有限公司 | Display panel and electronic device |
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| US20130077736A1 (en) * | 2011-09-23 | 2013-03-28 | Hydis Technologies Co., Ltd. | Shift Register and Driving Circuit Using the Same |
| CN103137061A (en) * | 2013-02-18 | 2013-06-05 | 京东方科技集团股份有限公司 | Shifting register unit, grid electrode driving circuit and display device |
| CN103236273A (en) * | 2013-04-16 | 2013-08-07 | 北京京东方光电科技有限公司 | Shift register unit and driving method thereof, gate drive circuit, and display device |
| CN103474017A (en) * | 2013-09-12 | 2013-12-25 | 北京京东方光电科技有限公司 | Shift register unit, gate drive circuit and display device |
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| JP5090008B2 (en) * | 2007-02-07 | 2012-12-05 | 三菱電機株式会社 | Semiconductor device and shift register circuit |
| TWI373019B (en) * | 2007-05-09 | 2012-09-21 | Chunghwa Picture Tubes Ltd | Shift register and shift register apparatus therein |
| TWI393978B (en) * | 2009-07-14 | 2013-04-21 | Au Optronics Corp | Liquid crystal display and shift register device thereof |
| KR101374113B1 (en) * | 2010-06-07 | 2014-03-14 | 엘지디스플레이 주식회사 | Liquid crystal display device and method for driving the same |
| TWI426486B (en) * | 2010-12-16 | 2014-02-11 | Au Optronics Corp | Gate driving circuit on array applied to chareg sharing pixel |
| TWI427591B (en) * | 2011-06-29 | 2014-02-21 | Au Optronics Corp | Gate driving circuit |
| TWI498877B (en) * | 2013-04-26 | 2015-09-01 | Chunghwa Picture Tubes Ltd | Display panel |
| TWI512740B (en) * | 2014-05-07 | 2015-12-11 | Au Optronics Corp | Shift register apparatus and voltage regulating device thereof |
-
2015
- 2015-12-30 TW TW104144421A patent/TWI562114B/en not_active IP Right Cessation
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2016
- 2016-02-04 CN CN201610079202.9A patent/CN105761687B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130077736A1 (en) * | 2011-09-23 | 2013-03-28 | Hydis Technologies Co., Ltd. | Shift Register and Driving Circuit Using the Same |
| CN103021309A (en) * | 2011-09-23 | 2013-04-03 | 海蒂斯技术有限公司 | Shift register and driving circuit using the same |
| CN103137061A (en) * | 2013-02-18 | 2013-06-05 | 京东方科技集团股份有限公司 | Shifting register unit, grid electrode driving circuit and display device |
| CN103236273A (en) * | 2013-04-16 | 2013-08-07 | 北京京东方光电科技有限公司 | Shift register unit and driving method thereof, gate drive circuit, and display device |
| CN103474017A (en) * | 2013-09-12 | 2013-12-25 | 北京京东方光电科技有限公司 | Shift register unit, gate drive circuit and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI562114B (en) | 2016-12-11 |
| CN105761687A (en) | 2016-07-13 |
| TW201724067A (en) | 2017-07-01 |
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