CN103137061A - Shifting register unit, grid electrode driving circuit and display device - Google Patents
Shifting register unit, grid electrode driving circuit and display device Download PDFInfo
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- CN103137061A CN103137061A CN201310052893XA CN201310052893A CN103137061A CN 103137061 A CN103137061 A CN 103137061A CN 201310052893X A CN201310052893X A CN 201310052893XA CN 201310052893 A CN201310052893 A CN 201310052893A CN 103137061 A CN103137061 A CN 103137061A
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
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Abstract
The invention discloses a shifting register unit, a grid electrode driving circuit and a display device. The shifting register unit is provided with a capacity unit, one end of the capacity unit is connected with a same level output node, the other end of the capacity unit is connected with a pulling-up node, the shifting register unit further comprises a first pulling-down unit and a second pulling-down unit, wherein the first pulling-down unit comprises at least two first transistors, the second pulling-down unit comprises at least two second transistors, and the at least two first transistors are alternate in a breakover state under the control of respectively corresponding control signals, and alternately output low level signals to the same level output node when the same level output node is in a pulling-down state; the at least two second transistors are alternate in a breakover state under the control of respectively corresponding control signals, and alternately output the low level signals to the pulling-up node when the pulling-up node is in a pulling-down state.
Description
Technical field
The present invention relates to the shift LD technology, particularly a kind of shift register cell, gate driver circuit and display device.
Background technology
Integrated grid shift register is integrated in the grid impulse output register on panel, thereby has saved IC, has reduced cost.The implementation method of integrated grid shift register has a variety of, can comprise different a plurality of transistors and electric capacity, and commonly used have structures such as 12T1C, 9T1C, 13T1C.
Generally speaking, shift register is comprised of the multi-stage shift register unit, and every one-level shift register cell high level signal of output within the extremely short time just, and all can the output low level signal at other times, is generally the VSS signal.
There is the lower shortcoming of life of product at least in the shift register of prior art, and this is described as follows.
The front is mentioned, every one-level shift register cell is high level signal of output within the extremely short time just, and all can the output low level signal at other times, in order to guarantee shift register cell output low level signal, need upwards to draw node and output node output low level signal, be generally VSS.That is to say, upwards draw the time of node and output node output low level signal very long, this time accounts for more than 99% usually.
And simultaneously, this VSS signal is all export by pull-down transistor, and this just needs pull-down transistor to be in the state of high level conducting, with export the VSS signal on draw node and output node.
Can find from the above description, be in for a long time high level state on the grid of pull-down transistor, this will cause making pull-down transistor faster than other transistor ageings in shift register cell, has shortened the serviceable life of product.
Summary of the invention
The purpose of the embodiment of the present invention is to provide a kind of shift register cell, gate driver circuit and display device, improves the life-span of shift register.
to achieve these goals, the embodiment of the present invention provides a kind of shift register cell, described shift register cell has a capacitor cell, one end of described capacitor cell is connected with output node at the corresponding levels, the other end with on draw node to be connected, described shift register cell also comprises for the first drop-down unit of the current potential of drop-down described output node at the corresponding levels and is used for drop-down the second drop-down unit that draws the current potential of node on described, the described first drop-down unit comprises at least two the first transistors, the described second drop-down unit comprises at least two transistor secondses, when described output node at the corresponding levels is in the drop-down stage, described at least two the first transistors are in conducting state in turn under the control of each self-corresponding control signal, the output low level signal is to described output node at the corresponding levels in turn, when drawing node to be in the drop-down stage on described, described at least two transistor secondses are in conducting state in turn under the control of each self-corresponding control signal, and the output low level signal draws node on described in turn.
Above-mentioned shift register cell wherein, also comprises:
Transistor T 3, source electrode is connected with the upper level output node, drain electrode with described on draw node to be connected, the signal that grid and is exported is in the signal output part sub-connection of high level when the upper level output node is exported high level;
Described at least two transistor secondses comprise described transistor T 3, draw on described low level signal that node receives to comprise low level signal by the described upper level output node output of described transistor T 3 outputs.
Above-mentioned shift register cell, wherein, described at least two transistor secondses also comprise transistor T 4, and source electrode is connected with the next stage output node, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection of exporting the 4th control signal; The low level signal that draws node to receive on described comprises the low level signal by the described next stage output node output of described transistor T 4 outputs.
Above-mentioned shift register cell wherein, also comprises:
Described at least two the first transistors comprise described transistor T 2, and the low level signal that described output node at the corresponding levels receives comprises the cut-off signals by described transistor (T2) output.
Above-mentioned shift register cell, wherein,
Described at least two the first transistors comprise:
Transistor T 6, source electrode receives cut-off signals, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection of exporting the 3rd control signal;
Transistor T 7, source electrode receives cut-off signals, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection of exporting the 4th control signal;
Described at least two transistor secondses comprise:
Transistor T 3, source electrode is connected with the upper level output node, drain electrode with on draw node to be connected, grid and export the signal output part sub-connection of the first control signal;
Transistor T 4, source electrode is connected with the next stage output node, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection of exporting the 4th control signal;
Transistor T 5, source electrode is connected with output node at the corresponding levels with the signal output part sub-connection of exporting cut-off signals, drain electrode, grid and the signal output part sub-connection of exporting the 3rd control signal;
Wherein:
The signal dutyfactor of described the first control signal, the second control signal, the 3rd control signal, the 4th control signal is 1/4, and is in the time period non-overlapping copies of high level;
During upper level output node output high level, described the first control signal is in high level;
When output node at the corresponding levels need to be exported high level signal, described the second control signal was in high level;
During next stage output node output high level, described the 3rd control signal is in high level.
In order better to realize above-mentioned purpose, the embodiment of the present invention also provides a kind of gate driver circuit, comprises multistage shift register cell as claimed in claim.
In order better to realize above-mentioned purpose, the embodiment of the present invention also provides a kind of display device, comprises above-mentioned gate driver circuit.
The embodiment of the present invention has at least one in following beneficial effect:
In the embodiment of the present invention, a plurality of TFT conducting in turn in drop-down unit (namely grid is in high level control in turn), therefore, in the drop-down stage, the grid of pull-down transistor only has part-time to be in high level state, reduced the grid dutycycle voltage of pull-down transistor, improved the life-span of pull-down transistor, thereby improved the life-span of whole shift register cell.
In the embodiment of the present invention, a plurality of TFT conducting output low level in turn signal in drop-down unit is to treating pull-down node, treats pull-down node and carries out repeatedly drop-downly, reduced the burr of drop-down stage shift register cell output signal;
In the embodiment of the present invention, part in a plurality of TFT in drop-down unit is the existing TFT in multiplexing shift register cell, reduce number of devices, reduced cost, also made the shift register cell of the embodiment of the present invention be conducive to realize narrower panel border.
Description of drawings
Fig. 1 represents the structural representation of the shift register cell of the embodiment of the present invention;
Fig. 2 represents the signal timing diagram of shift register cell shown in Figure 1;
Fig. 3 represents the structural representation of the shift register of the embodiment of the present invention.
Embodiment
the shift register cell of the embodiment of the present invention, in gate driver circuit and display device, each treats that drop-down unit corresponding to pull-down node (output node at the corresponding levels and on draw node) includes at least two TFT, make when pull-down node need to be controlled by low level signal, at least two TFT that drop-down unit comprises can be in conducting state in turn, the output low level signal is to treating pull-down node, reduce the time that the TFT grid in drop-down unit is worked under high level state, slow down the aging speed of the TFT in drop-down unit, improve the serviceable life of whole shift register cell.
Before the embodiment of the present invention was further elaborated, the conceptual illustration that first embodiment of the present invention is related to was as follows.
Take n level shift register cell as example, its course of work is as follows, and it generally is divided into following 4 stages:
Stage A, n-1 level output node n-1 exports high level, and the high level signal that utilizes the upper level output node to export this moment is tentatively drawn high the level of PU node;
Stage B, the PU node that continues to draw high is opened a TFT, and high level signal is outputed to output node at the corresponding levels, makes the output node output high level signal of n level shift register cell;
Stage C, n+1 level output node output high level signal, PU node and the output node at the corresponding levels of n level shift register cell are dragged down by low level signal;
Stage D is until before next order n-1 level output node n-1 output high level, PU node and the output node at the corresponding levels of n level shift register cell are dragged down by low level signal.
In specific embodiments of the invention, this drop-down stage refers to stage C and stage D, i.e. the time except the stage of output node at the corresponding levels and upper level output node output high level signal.
has a capacitor cell in the shift register cell of the embodiment of the present invention, one end of described capacitor cell is connected with output node at the corresponding levels, the other end with on draw node to be connected, described shift register cell also comprises for the first drop-down unit of the current potential of drop-down described output node at the corresponding levels and is used for drop-down the second drop-down unit that draws the current potential of node on described, wherein, the described first drop-down unit comprises at least two the first transistors, the described second drop-down unit comprises at least two transistor secondses, when described output node at the corresponding levels is in the drop-down stage that need to be subjected to low level signal control, described at least two the first transistors are in conducting state in turn under the control of each self-corresponding control signal, the output low level signal is to described output node at the corresponding levels in turn, when drawing node to be in need to be subjected to the drop-down stage that low level signal controls on described, described at least two transistor secondses are in conducting state in turn under the control of each self-corresponding control signal, and the output low level signal draws node on described in turn.
At this, should be noted that at first being in turn conducting state in the drop-down stage comprises following various situations:
1, be in turn conducting state, and continuous distribution in time; Thisly easily realize when being distributed in the drop-down unit of independent design.
2, be in turn conducting state, but discontinuously arranged in time.Thisly can occur when being distributed in the TFT that needs in multiplexing existing shift register cell, as the shift register of the 7T1C that will mention in the back.
In the shift register cell of the embodiment of the present invention, owing to being provided with a plurality of TFT in each drop-down unit, these TFT conducting in turn (namely grid be in turn high level control), with output low level signal in turn to corresponding node.With respect to prior art in the time controlled by low level signal, the grid of pull-down transistor will be in high level state always, TFT in the drop-down unit of the embodiment of the present invention only has part-time to be in high level state, reduced the grid dutycycle voltage of pull-down transistor, improved the life-span of pull-down transistor, thereby improved the life-span of whole shift register cell.
The drop-down unit corresponding with output node at the corresponding levels illustrates as follows.
Suppose that gate driver circuit comprises 1024 grades of shift register cells, according to the method for prior art, pull-down transistor is within the working time, and the time grid more than 99.9% (1023/1024) all is under the control of high level signal.
and in the method for the supposition embodiment of the present invention, 2 TFT parallel connections, its source electrode connects the VSS signal, and drain electrode is connected with output node at the corresponding levels, when output node at the corresponding levels need to be in low level signal control, the signal that outputs to the grid of 2 TFT by control is in high level with time interval T in turn, can guarantee that the VSS signal constantly outputs to output node at the corresponding levels, simultaneously, when output node at the corresponding levels need to be in low level signal control, the grid of each TFT only has part-time to be under the control of high level signal, therefore reduced transistorized aging speed, thereby improved the life-span of whole shift register cell.
Simultaneously, in specific embodiments of the invention, in the whole drop-down stage, can carry out repeatedly PU node and output node at the corresponding levels drop-downly, can reduce the burr of shift register cell output signal.
In specific embodiments of the invention, the first drop-down unit and the second drop-down unit specifically can be accomplished in several ways, and are described as follows.
＜mode one 〉
The first drop-down unit and the second drop-down unit work alone separately, have separately independently control signal.
TFT quantity as the first drop-down unit and the second drop-down unit can be identical, also can be different.
Have 3 TFT as the first drop-down unit, source electrode receives the VSS signal, and drain electrode is connected with output node at the corresponding levels, and the second drop-down unit has 2 TFT, and source electrode all receives the VSS signal, and drain with on draw node to be connected.
A kind of reasonable mode is:
The high level signal non-overlapping copies of 3 each self-corresponding 3 control signals of TFT of the first drop-down unit, but within the whole drop-down stage of output node at the corresponding levels continuous distribution.
The high level signal non-overlapping copies of 2 each self-corresponding 2 control signals of TFT of the second drop-down unit, but within the upper whole drop-down stage of drawing node continuous distribution.
And these control signals are can dutycycle identical, also can dutycycle different, as each self-corresponding 2 control signal X1 of 2 TFT of the second drop-down unit and the high level signal non-overlapping copies of X2, and continuous distribution within output node at the corresponding levels needs time period of output low level signal, but the high level lasting time of X1 is longer than the high level lasting time of X1.
＜mode two 〉
For mode one, each drop-down unit works alone separately, is unfavorable for the overall arrangement of control signal, also needs more control signal simultaneously, can cause complex structure.
In mode two, in drop-down unit, TFT quantity is identical, therefore the TFT in difference drop-down unit can be divided into groups in twos, each group TFT uses identical control signal, the high level distributed area non-overlapping copies of all these control signals, but output node at the corresponding levels and on draw node need to be subjected to simultaneously that in time period that low level signal controls, continuous distribution gets final product.
Certainly, the realization of the drop-down unit in the embodiment of the present invention is not limited to above implementation, and those skilled in the art can realize above-mentioned drop-down unit by alternate manner according to the record of the embodiment of the present invention, does not describe in detail one by one at this.
In specific embodiments of the invention, above-mentioned shift register cell also comprises other TFT device, as being in conducting and this high level signal outputed to the PU node to carry out the TFT of precharge when the upper level output node being exported high level signal, and for example in pre-charging stage, a low level signal is outputed to the TFT of output node at the corresponding levels.
In specific embodiments of the invention, above-mentioned drop-down unit can increase new TFT on the basis of above-mentioned existing element realizes, but this will increase the quantity of TFT, increases the complexity that realizes.
Therefore, in specific embodiments of the invention, further consider that multiplexing existing TFT is used as the TFT in drop-down unit, to reduce the quantity of TFT.
In the specific embodiment of the invention, one or more in can multiplexing existing TFT reduce the quantity that shift register cell uses TFT, this just wherein several modes be described as follows.
In existing shift register cell, comprise that a high level signal that is used for when upper level output node output high level signal, the upper level output node being exported outputs to the transistor T 3 that draws node to carry out precharge, its source electrode is connected with the upper level output node, drain electrode with described on draw node to be connected, the signal that grid and is exported is in the signal output part sub-connection of high level when the upper level output node is exported high level;
Consider when shift register cell at the corresponding levels is in the drop-down stage, the inevitable output low level signal of upper level shift register cell, based on above consideration, in the specific embodiment of the invention, multiplexing above-mentioned transistor T 3 is as the part of the second drop-down unit, that is: described at least two transistor secondses comprise described transistor T 3, draw on described low level signal that node receives to comprise low level signal by the described upper level output node output of described transistor T 3 outputs.
In existing shift register, comprise that also one is used for when shift register at the corresponding levels is in pre-charging stage, export a low level signal (cut-off signals) to the transistor T 4 of output node at the corresponding levels, the signal of its grid and an output is in the signal output part sub-connection of high level when upper level output node output high level; Therefore, upper level output node output high level, the control that transistor T 4 is subject to high level signal is in conducting state, and output one cut-off signals is to output node at the corresponding levels.
In the prior art, this transistor T 4 only need to work in pre-charging stage, and is in cut-off state in the drop-down stage, and therefore, in the specific embodiment of the invention, all right multiplexing above-mentioned transistor T 4 is as the part of the first drop-down unit, that is:
Described at least two the first transistors comprise described transistor T 2, and the low level signal that described output node at the corresponding levels receives comprises the cut-off signals by described transistor T 2 outputs.
shift register cell in prior art, the high level signal of next stage output node output is to use as the reset signal of shift register cell at the corresponding levels, consider that the signal of next stage output node output is in the stage that drags down of shift register cell at the corresponding levels, the overwhelming majority time is in low level state, therefore in specific embodiments of the invention, be used for the TFT that resets in can also multiplexing prior art, but need to be used for the second drop-down unit after the annexation of modification TFT, in amended TFT, use the signal of next stage output node output to use as degrade signal, under this mode, described at least two transistor secondses also comprise transistor T 4, source electrode is connected with the next stage output node, drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection of exporting the 4th control signal, the low level signal that draws node to receive on described comprises the low level signal by the described next stage output node output of described transistor (T4) output.
Under above-mentioned variety of way, multiplexing existing at least one transistor T 2, T3 or T4, in the situation that the TFT quantity that takes turns to operate in guaranteeing each drop-down unit is enough, reduced the device usage quantity of whole shift register cell, reduced cost and implementation complexity.
The 7T1C shift register cell that the below realizes with 4 control signals describes the course of work and the structure of the shift register cell of the embodiment of the present invention in detail.
As shown in Figure 1, the 7T1C shift register cell of the embodiment of the present invention comprises:
One output node OUTPUT at the corresponding levels;
Capacitor cell C, the end of described capacitor cell C is connected with output node OUTPUT at the corresponding levels, the other end with on draw node PU to be connected;
Transistor T 3, source electrode is connected with upper level output node N-1OUT, drain electrode with on draw node PU to be connected, grid and export the signal output part sub-connection of the first control signal C1; When upper level output node N-1OUT output high level signal, the signal C1 that the grid of transistor T 3 is in high level state controls, transistor T 3 conductings, and the high level signal of output N-1OUT output carries out precharge to the PU node.
in specific embodiments of the invention, the the first drop-down unit multiplexed transistor T 2 that is used for the current potential of drop-down described output node OUTPUT at the corresponding levels, and use the VSS signal to carry out drop-down to the current potential of output node OUTPUT at the corresponding levels, and be used for the second drop-down unit multiplexed transistor T 3 of the drop-down current potential that draws node PU on described, and use VSS signal, the low level signal of the low level signal of upper level output node N-1OUT output and next stage output node N+1OUT output on draw the current potential of node PU to carry out drop-down, as shown in Figure 1, at least two the first transistors that the described first drop-down unit comprises are:
Transistor T 6, source electrode receives cut-off signals, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection of exporting the 3rd control signal;
Transistor T 7, source electrode receives cut-off signals, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection of exporting the 4th control signal;
At least two transistor secondses that the described second drop-down unit comprises comprise:
Transistor T 3;
Transistor T 4, source electrode is connected with the next stage output node, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection of exporting the 4th control signal;
Transistor T 5, source electrode is connected with output node at the corresponding levels with the signal output part sub-connection of exporting cut-off signals, drain electrode, grid and the signal output part sub-connection of exporting the 3rd control signal;
Wherein:
The signal dutyfactor of described the first control signal C1, the second control signal C2, the 3rd control signal C3, the 4th control signal C4 is 1/4, and is in the time period non-overlapping copies of high level;
During upper level output node output high level, described the first control signal is in high level;
When output node at the corresponding levels need to be exported high level signal, described the second control signal was in high level;
During next stage output node output high level, described the 3rd control signal is in high level.
Be described in detail as follows below in conjunction with the signal timing diagram shown in Figure 2 course of work to above-mentioned 7T1C shift register cell.
At first, can find, the signal dutyfactor of C1, C2, C3 and C4 is 1/4, and is in the time period non-overlapping copies of high level, and during upper level output node N-1OUT output high level, C1 is in high level, and during output node OUTPUT at the corresponding levels output high level signal, C2 is in high level, during next stage output node N+1OUT output high level, C3 is in high level, and all the other time C4 are in high level.
In pre-charging stage 1., C1 is high level, and C2, C3, C4 are low level, and N-1OUT is high level, and N+1OUT is low level.At this moment, T1, T4, T5, T6, T7 cut-off, T2, T3 conducting.The high level signal of N-1OUT output outputs to the PU node by T3, and the T1 grid is carried out precharge, and the PU point voltage rises, and the T2 conducting, output VSS signal keeps OUTPUT to be in low level to OUTPUT.
Draw the stage 2. upper, C2 is that high level, C1, C3, C4 are low level, and N-1OUT is low level, and N+1OUT is low level.T2, T3, T4, T5, T6, T7 cut-off, and PU point current potential continues to raise, the T1 conducting, the C2 that is in high level outputs to OUTPUT by T1.
Drop-down sub 3., C3 is that high level, C1, C2, C4 are low level, N-1OUT is low level, N+1OUT is high level.T1, T2, T3, T4, T7 cut-off, the C3 that is in high level controls T5, T6 conducting, and the output low level signal to PU node and OUTPUT node, keeps PU node and OUTPUT node to be in low level respectively.
Drop-down sub 4., C4 is high level, C1, C2, C3 are low level, N-1OUT is low level, N+1OUT is low level.T1, T2, T3, T5, T6 cut-off, the C4 that is in high level controls T4, T7 conducting, and the low level of the T4 output N+1OUT of conducting keeps the PU node to be in low level to the PU node.And the T7 of conducting output VSS low level signal keeps the OUTPUT node to be in low level to the OUTPUT node.
Drop-down sub 5., C1 is high level, C2, C3, C4 are low level, N-1OUT is low level, T1, T4, T5, T6, T7 cut-off, and the C1 that is in high level controls T2, T3 conducting, the low level of the T3 output N-1OUT of conducting keeps the PU node to be in low level to the PU node.And the T2 of conducting output VSS low level signal keeps the OUTPUT node to be in low level to the OUTPUT node.
Said process 3.-4.-5. move in circles and (can find, said process is exactly the discontinuously arranged situation in time of mentioning before the embodiment of the present invention, but this does not affect the PU node and the OUTPUT node is in low level in the whole drop-down stage), until the high level of upper level output node N-1OUT output next time.
Beneficial effect below in conjunction with the above-mentioned example explanation embodiment of the present invention is as follows.
In above-mentioned example, in the drop-down stage, the grid of TFT in drop-down subelement only has time of 1/3 to be in high level state, therefore being in for high level state in the whole drop-down stage with respect to prior art, the grid that has reduced TFT is in the time of high level state, has slowed down the aging speed of TFT;
In above-mentioned example, in the drop-down stage, PU stage and OUTPUT node have been carried out repeatedly drop-down, reduced the burr of output node output signal at the corresponding levels of drop-down stage.
In above-mentioned example, each drop-down subelement includes 3 TFT, but due to these TFT multiplexing TFT in existing shift register, therefore, the increase of integral device quantity is not a lot, reduces costs;
The embodiment of the present invention also provides a kind of gate driver circuit, comprises multistage shift register cell as above.
As shown in Figure 3, structural representation for the gate driver circuit of the shift register cell that utilizes the specific embodiment of the invention, it comprises the multi-stage shift register unit, and wherein the output of upper level is as the input of next stage, and the output of next stage simultaneously feeds back to again upper level and resets.
The embodiment of the present invention also provides a kind of display device, comprises above-mentioned gate driver circuit.
Above explanation is just illustrative for the purpose of the present invention; and nonrestrictive, those of ordinary skills understand, in the situation that do not break away from the spirit and scope that claims limit; can make many modifications, variation or equivalence, but all will fall within the scope of protection of the present invention.
Claims (7)
1. shift register cell, described shift register cell has a capacitor cell, one end of described capacitor cell is connected with output node at the corresponding levels, the other end with on draw node to be connected, described shift register cell also comprises for the first drop-down unit of the current potential of drop-down described output node at the corresponding levels and is used for drop-down the second drop-down unit that draws the current potential of node on described, it is characterized in that, the described first drop-down unit comprises at least two the first transistors, the described second drop-down unit comprises at least two transistor secondses, when described output node at the corresponding levels is in the drop-down stage, described at least two the first transistors are in conducting state in turn under the control of each self-corresponding control signal, the output low level signal is to described output node at the corresponding levels in turn, when drawing node to be in the drop-down stage on described, described at least two transistor secondses are in conducting state in turn under the control of each self-corresponding control signal, and the output low level signal draws node on described in turn.
2. shift register cell according to claim 1, is characterized in that, also comprises:
Transistor (T3), source electrode is connected with the upper level output node, drain electrode with described on draw node to be connected, the signal that grid and is exported is in the signal output part sub-connection of high level when the upper level output node is exported high level;
Described at least two transistor secondses comprise described transistor (T3), draw on described low level signal that node receives to comprise low level signal by the described upper level output node output of described transistor (T3) output.
3. shift register cell according to claim 1, is characterized in that, also comprises:
Transistor (T2), source electrode receives cut-off signals, and drain electrode is connected with output node at the corresponding levels, and the signal of grid and an output is in the signal output part sub-connection of high level when upper level output node output high level;
Described at least two the first transistors comprise described transistor (T2), and the low level signal that described output node at the corresponding levels receives comprises the cut-off signals by described transistor (T2) output.
4. shift register cell according to claim 1, it is characterized in that, described at least two transistor secondses also comprise transistor (T4), source electrode is connected with the next stage output node, drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection of exporting the 4th control signal; The low level signal that draws node to receive on described comprises the low level signal by the described next stage output node output of described transistor (T4) output.
5. shift register cell according to claim 1, is characterized in that, also comprises:
Transistor (T1), source electrode with output the second control signal the signal output part sub-connection, the drain electrode be connected with described output node at the corresponding levels, grid with on draw node to be connected; When output node at the corresponding levels need to be exported high level signal, described the second control signal was in high level;
Described at least two the first transistors comprise:
Transistor (T2), source electrode receives cut-off signals, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection of exporting the first control signal;
Transistor (T6), source electrode receives cut-off signals, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection of exporting the 3rd control signal;
Transistor (T7), source electrode receives cut-off signals, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection of exporting the 4th control signal;
Described at least two transistor secondses comprise:
Transistor (T3), source electrode is connected with the upper level output node, drain electrode with on draw node to be connected, grid and export the signal output part sub-connection of the first control signal;
Transistor (T4), source electrode is connected with the next stage output node, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection of exporting the 4th control signal;
Transistor (T5), source electrode is connected with output node at the corresponding levels with the signal output part sub-connection of exporting cut-off signals, drain electrode, grid and the signal output part sub-connection of exporting the 3rd control signal;
Wherein:
The signal dutyfactor of described the first control signal, the second control signal, the 3rd control signal, the 4th control signal is 1/4, and is in the time period non-overlapping copies of high level;
During upper level output node output high level, described the first control signal is in high level;
During next stage output node output high level, described the 3rd control signal is in high level.
6. a gate driver circuit, is characterized in that, comprises multistage shift register cell as described in any one in claim 1-5.
7. a display device, is characterized in that, comprises gate driver circuit as claimed in claim 6.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310052893.XA CN103137061B (en) | 2013-02-18 | 2013-02-18 | Shift register cell, gate driver circuit and display device |
| PCT/CN2013/074001 WO2014124570A1 (en) | 2013-02-18 | 2013-04-10 | Shift register unit, grid drive circuit and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310052893.XA CN103137061B (en) | 2013-02-18 | 2013-02-18 | Shift register cell, gate driver circuit and display device |
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| Publication Number | Publication Date |
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| CN103137061A true CN103137061A (en) | 2013-06-05 |
| CN103137061B CN103137061B (en) | 2015-12-09 |
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| CN201310052893.XA Active CN103137061B (en) | 2013-02-18 | 2013-02-18 | Shift register cell, gate driver circuit and display device |
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| WO (1) | WO2014124570A1 (en) |
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| Publication number | Publication date |
|---|---|
| CN103137061B (en) | 2015-12-09 |
| WO2014124570A1 (en) | 2014-08-21 |
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