CN105760330B - A kind of channelized frequencies Acquisition Circuit with APB interface - Google Patents
A kind of channelized frequencies Acquisition Circuit with APB interface Download PDFInfo
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Abstract
The channelized frequencies Acquisition Circuit with APB interface that the invention discloses a kind of, including being integrated in the APB interface for forming a general IP module in SoC system, internal register, programmable counter/timer, multiple independent capture modules and corresponding multiple fifo modules for being used to store capture time value；The register address space of on piece SoC system is distributed for internal register, the microprocessor in SoC system handles the interrupt signal received by APB interface configuration and reading and writing internal register.IP module with APB interface, the general purpose I P module in SoC system mainly applied, practicability, transplantability are high, versatile.Area occupied is small, saves circuit cost, is limited using resource, simple easily to realize.Interior design can store certain fifo module for capturing time information, prevent CPU from cannot timely respond to interrupt the value for overriding capture moment storage time information.
Description
Technical field
The present invention relates to microelectronics technology and the extensive SoC system regions of integrated circuit, especially relate generally to SoC system
One of system channelized frequencies acquisition interface IP modular circuit.
Background technique
With the progress and development of extensive SoC technology, on piece integrated multifunction IP module demand becomes more and more, makes
Area can be saved with some functional requirements of the method realization on piece SoC system of simple general-purpose, reduce first device on circuit board
It is part amount, simple to operation.
Existing frequency collection circuit realize technology be all taken out by components such as big resistance capacitances on pcb board it is hard
Part circuit realizes, frequency collection system that the hardware circuit of existing proposition realized based on resistance capacitance component is realized,
All have that circuit is complicated, area occupied is big, is difficult to the features such as integrating in SoC system, may not apply in SoC system.
Such as it at patent " a kind of modulation domain frequency counter ", authorizes publication number: in mono- text of CN204422648U, proposing
A kind of modulation domain frequency counter, the method by the way that preparation gate is arranged are realized to measured signal frequency measurement.The present invention realizes
Method is different, and interior design frequency counter and frequency acquisition module are realized and measured multi pass acquisition signal frequency outside SoC,
And the design is the circuit applied to the field SoC.
Patent " a kind of frequency and phase difference Acquisition Circuit ", publication number is authorized: in mono- text of CN2042214499U, proposing
Using the frequency and phase difference Acquisition Circuit of single-chip microcontroller and acquisition unit composition, internal in circuit includes that resistance, capacitor etc. are big
Component, mainly apply the circuit system on pcb board, cannot integrate and be applied in SoC system, be different from the design
The frequency collection circuit of proposition.
It is proposed in paper " the multichannel frequency acquisition system based on VB and DLL technology " (author: Ding Li, Jia Dangping)
The multichannel frequency acquisition system realized using DLL technology has big component and system by development board system etc.
Hardware circuit realize frequency collection, occupy that circuit area is big, the wasting of resources is more and circuit cost height；It cannot be applied
In SoC system, the scheme that its implementation and the design propose is different.
By consulting and comparing discovery, there are no propose the design frequency Acquisition Circuit in SoC system in existing document
Scheme, there are no the frequency collection circuits for proposing to be applied to SoC system.
Summary of the invention
Technical problem to be solved by the invention is to provide propose a kind of General Multiplex frequency collection electricity with APB interface
Road in the SoC system based on APB bus, and is used for sampling to multichannel input signal, have high real-time,
The features such as high-precision；Every road frequency collection circuit, which can be achieved, to carry out cycle count, height (low) level meter to the signal of acquisition
The multiple functions such as number, step-by-step counting, signal frequency calculating, signal phase difference calculating, and the circuit has area occupied small, uses
Resource is few, save the cost etc..
In order to solve the above technical problems, the present invention provides the channelized frequencies Acquisition Circuit with APB interface, characterized in that packet
Include be integrated in SoC system formed the APB interface of a general IP module, internal register, programmable counter/timer,
Multiple independent capture modules and corresponding multiple fifo modules for being used to store capture time value；
The register address space of on piece SoC system is distributed for internal register, the microprocessor in SoC system passes through
APB interface configuration and reading and writing internal register, and handle the interrupt signal received.
Programmable counter/timer gate time benchmark can be matched according to the frequency of application environment or acquisition signal
It sets.
Capture module working frequency can also require to be configured according to the frequency and acquisition precision of acquisition signal.
Internal register includes frequency collection control register, frequency collection timing mode register, multiple frequency collections
Capture register, multiple frequency collection pull-in time information registers, frequency collection counter/timer current count value；Its
In frequency collection capture register, frequency collection pull-in time information register quantity according to the external signal road that need to be acquired
Number is configured.
When being sampled to external signal, when the rising edge or failing edge for collecting external signal, or the acquisition thing of setting
When part occurs, triggering generates interrupt signal.
Interruption is handled by the microprocessor in SoC system and reads the time value accessed in fifo module, inside
The value of register calculates period, frequency, low and high level counting and the acquisition signal pulse counting number of acquisition signal.
The method for calculating frequency are as follows: be stored in fifo module nonce counter when rising edge or failing edge triggering generate interruption
Count value, the microprocessor responds in SoC system interrupt and read the meter in twice frequency acquisition pull-in time information register
Numerical value does difference and calculates the acquisition signal pulse period, calculates acquisition signal frequency by the period.
The method that low and high level counts are as follows: deposit fifo module is currently counted when rising edge or failing edge triggering generate interruption
Counter count value is interrupted by the microprocessor responds in SoC system and reads twice frequency acquisition pull-in time information deposit
Count value in device makes the difference and calculates holding time for low and high level, calculates duty ratio by holding time for low and high level.
The method that pulse number counts are as follows: each rising edge or failing edge triggering generate interruption, occur to interrupt it is primary and
A certain setting variable is arranged in interrupt service routine to count once, sampling pulse number is obtained according to the last number that counts.
It is interrupted between two-way by sampling triggering, phase difference is gone out according to the interval calculation occurred between interruption, in all the way
The temporal information of respectively deposit fifo module is all read in disconnected generation, and the time value interval calculation of twi-read goes out between different pulses
Time interval and phase difference.
The General Multiplex frequency collection electricity of this programme band APB (Advanced Peripheral Bus, peripheral bus) interface
Road, design have APB bus interface, can be acquired to external signal and pass through transmission interrupt signal into SoC system
Cycle count, high level and the low electricity to the multiple signals of acquisition are realized in microprocessor, the processing by microprocessor to interruption
Flat counting, step-by-step counting can also realize the frequency calculating to acquisition signal, period calculating, phase difference calculating etc..
Compared with prior art, the invention has the advantages that:
1, the IP module with APB interface, the general purpose I P module in SoC system mainly applied, practical, transplantability
It is high, versatile.
2, area occupied is small, saves circuit cost, is limited using resource, simple easily to realize.
3, apply in integrated circuit and SoC system regions, currently available technology there are no propose apply in the field SoC
Frequency collection circuit.
4, interior design can store certain fifo module for capturing time information, prevent CPU from cannot timely respond to
Interrupt the value for overriding capture moment storage time information.
Detailed description of the invention
Frequency collection circuit system block diagram of the Fig. 1 with APB interface；
The APB interface signal of Fig. 2 frequency collection circuit；
Fig. 3 frequency collection logic function block diagram；
Fig. 4 frequency collection work clock can configure exemplary graph；
Fig. 5 captures trigger circuit principle diagram；
Sketch plan is interrupted in Fig. 6 triggering deposit FIFO temporal information and generation.
Specific embodiment
Further explanation of the technical solution of the present invention with reference to the accompanying drawing, is illustrated by taking 6 tunnel frequency collection circuits as an example,
The channelized frequencies Acquisition Circuit of other demands can carry out the increase and decrease change of some corresponding internal module parts.Band APB connects
The system schematic block diagram of the frequency collection circuit of mouth is as shown in Figure 1.
It mainly include APB interface, 32 programmable counter/timers, multiple independent capture modules and corresponding more
It is a to be used to store the FIFO etc. for capturing time value.The frequency collection circuit of design is that a general IP module is integrated in
It is used in SoC system.Need to distribute the register of on piece SoC system in circuit design for frequency collection circuit internal register
Address space, by APB interface, the microprocessor in SoC can be configured correctly and the deposit inside read-write frequency acquisition module
Device, and signals such as interruption for transmitting of processing frequency Acquisition Circuit etc.；One programmable counter of interior design, gate time
Benchmark can be changed according to application environment or the acquisition general frequency of signal or option and installment.The multiple independent capture moulds of interior design
Block, it is specific to need according to the independent capture module for acquiring a few road frequency signal interior design corresponding numbers, capture module work
Frequency is required according to the about frequency and acquisition precision of acquisition signal and is configured.The multiple FIFO of interior design store a fixed number
The pull-in time information of amount, prevent microprocessor from making internal some triggering information loss without processing interruption in time etc..Frequency
Acquisition Circuit can generate interrupt signal when the collection event on the edge or setting that collect external signal occurs；Need to configure SoC
In microprocessor handled and read the time value that FIFO memory takes to interruption, period, the frequency of acquisition signal can be calculated
Rate and high-low level time, and by further calculating the duty ratio that can estimate to calculate acquisition signal；Pass through acquisition multichannel letter
It number can calculate phase relation and the frequency characteristic etc. between multiple signals；It can also be carried out by frequency collection circuit to outside
Acquisition signal pulse number is counted.
The APB interface signal of the 6 road frequency collection IP modules wherein designed is as shown in Figure 2.The list of APB interface signal is retouched
It states as shown in table 1.
1 AMBA APB Slave interface of table
| Title | I/O | Function description |
| pclk | I | APB clock |
| n_p_reset | I | APB resets |
| psel | I | APB selection |
| penable | I | APB is enabled |
| pwrite | I | APB read/write strobe |
| paddr[03:00] | I | APB address path |
| pwdata[31:00] | I | APB writes data |
| rdata[31:00] | I | APB reads data |
In addition to APB interface part, the internal logic of other parts component frequency Acquisition Circuit work in frequency collection circuit
Funtion part, logic function circuit block diagram are as shown in Figure 3.Inside 6 road frequency collection logic function partial circuits specially comprising one
The counter/timer of 32bit and 6 trapping modules.Each capture module interior design FIFO storage is a certain number of
Capture time value information prevents CPU from cannot timely respond to interrupt the capture register for overriding capture moment storage time information
Value.Counter overflow mark (COF) in frequency collection timing mode register, which is set to one interruption of logic 1 and generation, asks
Ask (if COF interruption is allowed to).Logic 1, which is set as, by ECOF in frequency collection timing mode register allows COF
Mark generates interrupt requests.When CPU turns to interrupt service routine, COF cannot be removed automatically by hardware, it is necessary to clear with software
0.Frequency collection captures the working method that register is used to configure frequency collection capture module, and set frequency collection captures deposit
ECCF in device will allow the CCF of module to interrupt.In edging trigger trap mode, SoC chip needs 6 tunnels of frequency collection to input
There is effect level changes to cause to capture frequency collection inside frequency collection circuit on CEXn pin in signal pins, that is, Fig. 1
The value of counter/timer is simultaneously loaded into the FIFO of 32 storage capture time information of respective modules.Each
Capture module all can be configured to work independently, frequency collection capture register in CAPP and CAPN for select trigger catch
The level change type caught: low level to high level (positive edge), high level to low level (negative edge) or any variation (positive edge
Or negative edge).When capture occur when, capture in frequency collection control register/compare mark (CCF) and be set to logic 1 and produce
A raw interrupt requests (if CCF interruption is allowed to).When CPU turns to interrupt service routine, CCF cannot be automatic by hardware
It removes, it is necessary to software clear 0.When the microprocessor in SoC, which receives interrupt signal reading frequency acquisition capture module, to be captured
Between the value of information preservation register the time count value that the moment occurs for corresponding acquisition signal can be read, read in a FIFO and store
Data just send out one.In frequency collection interface function logic circuit about the clock of internal counter and capture module frequency
Rate is configurable, only with a kind of clock frequency introduction explanation in Fig. 3.It can be according to practical application scene and the external acquisition general frequency of signal
Rate carries out MUX selection control processing to clock.It is every to be selected all the way by MUX, make per frequency collection internal work clock all the way
It is independent configurable.Shown in one of clock configuration relation can be referred to such as Fig. 4.Capture module captures principle as shown in figure 5, externally
Portion's signal is sampled, and relatively front and back variation, when occur up and down, it is double along variation when and according to internal sample demand into
Row internal trigger, and in the value of hour counter deposit FIFO, trigger interrupt signal.Sampling triggers and deposits current count value
Enter FIFO and generation interruption simple process is as shown in Figure 6.
The main register of the configuration wherein needed used specifically includes that frequency collection controls register, frequency collection
Timing mode register, frequency collection capture register (multiple), frequency collection pull-in time information register (multiple), frequency
Acquisition counter device/timer current count value.Frequency collection therein captures register, frequency collection pull-in time information preservation
The quantity of register, which needs specifically to acquire a few road external signals according to design, is configured to and acquires the identical quantity number of signal.It is main
Register detailed content is wanted to be listed as follows: 1. frequency collection control register
2 frequency collection of table controls register
2. frequency collection timing mode register
3 frequency collection timing mode register of table
3. frequency collection captures register and (since design is 6 road frequency collection interfaces, it is identical to need to configure 6 functions
It distributes 6 different frequency collections of address and captures register).
4 frequency collection of table captures register
4. counter/timer current count value (read-only).
5 counter/timer count value of table
5. pull-in time information register (since design is 6 road frequency collection interfaces, it is identical to need to configure 6 functions
Distribute 6 different pull-in time information preservation registers of address).
6 pull-in time information register of table
| Bit field | Access type | Function description |
| 31-0 | Read/Write | Register saves the value of 32 bit timing devices of capture module capture |
Some inside processing and reading frequency acquisition post is carried out to interruption by the above register and SoC internal microprocessor
The value of storage can calculate the frequency of acquisition signal and carry out the functions such as low and high level counting.Computing Principle following (1) calculates frequency
Rate triggers rising edge or failing edge by configuring, for example is triggered in rising edge, the square-wave signal determine to the period
Interval time is the square-wave cycle time between two rising edges, and when rising edge triggers and generates interruption, deposit fifo module is current
Counter, the microprocessor responds in SoC system interrupt and read twice frequency acquisition pull-in time information register
In count value, do difference can calculate acquisition the signal pulse period, that is, further calculate out and acquire signal frequency.(2) height
Level counts, and same principle setting carries out the positive capture along with negative edge to acquisition signal and triggers interruption and save nonce counter
Count value is stored in fifo module nonce counter count value when rising edge and failing edge triggering generate interruption, passes through SoC system
In microprocessor responds interrupt and read the count value in twice frequency acquisition pull-in time information register, twice rising edge
Triggering or the twice time at failing edge moment, which make the difference, calculates the period, the time difference meter between adjacent rising edge and failing edge
High level is calculated to hold time, time difference between adjacent failing edge and rising edge calculate it is low level hold time,
The duty ratio of low and high level can be calculated after the relationship of being divided by by the doing between the period of holding time of high/low level.(3)
Pulse number counts, and similarly each rising edge or failing edge select triggering to interrupt, and occurs to interrupt once and in interrupt service routine
Middle some variable of setting counts once, infers sampling pulse number according to the last number that counts.(4) pass through sampling touching between two-way
Hair interrupts, and goes out phase difference according to the interval calculation occurred between interruption, and every interruption all the way, which occurs all to read, is respectively stored in FIFO's
Temporal information, the time value interval of twi-read are the time interval calculated between different pulses and calculate phase difference.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, several improvement and deformations can also be made, these improvement and deformations
Also it should be regarded as protection scope of the present invention.
Claims (8)
1. a kind of channelized frequencies Acquisition Circuit with APB interface, characterized in that general including being integrated in formation one in SoC system
The APB interface of IP module, internal register, programmable counter/timer, multiple independent capture modules and corresponding more
It is a to be used to store the fifo module for capturing time value；
The register address space of on piece SoC system is distributed for internal register, the microprocessor in SoC system is connect by APB
Mouth configuration and reading and writing internal register, and handle the interrupt signal received；
When being sampled to external signal, when the collection event hair of the rising edge or failing edge for collecting external signal, or setting
When raw, triggering generates interrupt signal；
The time value accessed in fifo module is handled and read to interruption by the microprocessor in SoC system, pass through reading
The value of internal register of access time information calculate acquisition period of signal, frequency；And by entering to the event of capture
Interruption times counting can be realized low and high level count and acquisition signal pulse counting number.
2. the channelized frequencies Acquisition Circuit according to claim 1 with APB interface, characterized in that programmable counter/meter
When device gate time benchmark according to application environment or acquire signal frequency configured.
3. the channelized frequencies Acquisition Circuit according to claim 1 with APB interface, characterized in that capture module work frequency
Rate requires to be configured according to the frequency and acquisition precision of acquisition signal.
4. the channelized frequencies Acquisition Circuit according to claim 1 with APB interface, characterized in that internal register includes
Frequency collection controls register, frequency collection timing mode register, multiple frequency collections and captures register, multiple frequency collections
Pull-in time information register, frequency collection counter/timer current count value；Frequency collection therein capture register,
The quantity of frequency collection pull-in time information register is configured according to the external signal number that need to be acquired.
5. the channelized frequencies Acquisition Circuit according to claim 1 with APB interface, characterized in that the method for calculating frequency
Are as follows: it is stored in fifo module nonce counter count value when rising edge or failing edge triggering generate interruption, micro- place in SoC system
The count value in twice frequency acquisition pull-in time information register is interrupted and is read in reason device response, is done difference and is calculated acquisition signal
Pulse period calculates acquisition signal frequency by the period.
6. the channelized frequencies Acquisition Circuit according to claim 1 with APB interface, characterized in that low and high level counted
Method are as follows: be stored in fifo module nonce counter count value when rising edge and failing edge triggering generate interruption, pass through SoC system
In microprocessor responds interrupt and read the count value in twice frequency acquisition pull-in time information register, twice rising edge
Triggering or the twice time at failing edge moment, which make the difference, calculates the period, the time difference meter between adjacent rising edge and failing edge
High level is calculated to hold time, time difference between adjacent failing edge and rising edge calculate it is low level hold time,
Duty ratio is calculated by the relationship of high/low level held time between the period.
7. the channelized frequencies Acquisition Circuit according to claim 1 with APB interface, characterized in that pulse number counted
Method are as follows: each rising edge or failing edge triggering generate interruption, occur to interrupt primary and be arranged in the interrupt service program a certain
It sets variable to count once, sampling pulse number is obtained according to the last number that counts.
8. the channelized frequencies Acquisition Circuit according to claim 1 with APB interface, characterized in that by adopting between two-way
Sample triggering is interrupted, and goes out phase difference according to the interval calculation occurred between interruption, occurs all to read respectively deposit per interrupting all the way
The temporal information of fifo module, the time value interval calculation of twi-read go out time interval and phase difference between different pulses.
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| CN109240595A (en) * | 2018-08-24 | 2019-01-18 | 武汉中旗生物医疗电子有限公司 | Single-chip microcontroller frequency collection method and device |
| CN115015618B (en) * | 2022-08-08 | 2022-10-14 | 深圳市恒运昌真空技术有限公司 | Radio frequency power supply signal acquisition method and device |
| CN115629298B (en) * | 2022-12-19 | 2023-06-06 | 杭州加速科技有限公司 | Method and device for capturing abnormal synchronous trigger signal in ATE equipment |
| CN116481599A (en) * | 2023-06-25 | 2023-07-25 | 珠海矽敏科技有限公司 | Multichannel signal acquisition device and sensor system |
| CN116499500B (en) * | 2023-06-28 | 2024-01-30 | 珠海矽敏科技有限公司 | Sensor system, sensor, signal output circuit of sensor and signal acquisition equipment |
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