CN105760327A - Internal bus of aerospace electronic product - Google Patents
Internal bus of aerospace electronic product Download PDFInfo
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- CN105760327A CN105760327A CN201510916908.1A CN201510916908A CN105760327A CN 105760327 A CN105760327 A CN 105760327A CN 201510916908 A CN201510916908 A CN 201510916908A CN 105760327 A CN105760327 A CN 105760327A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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Abstract
The invention provides an internal bus of an aerospace electronic product, which is used for information interaction between a main module and a plurality of slave modules, and the bus signals comprise: the bus timing is divided into two types of main module operation period using waiting and main module operation period without waiting, and each type is divided into two types of reading and writing. The bus provided by the invention is specific to aerospace electronic products, has strong universality and compatibility, and is beneficial to improving the quality and the working reliability of module interconnection signals.
Description
Technical field
The present invention relates to aerospace electron product scope, in particular, relate to a kind of aerospace electron interiors of products interconnection.
Background technology
At present, the type of aerospace electron product is various, of many uses, work characteristics is more numerous and diverse, and different research and development factories, the product developed are also different therewith, and product inner module mutual contact mode is multifarious especially.Only from physically, just have the multiple combination modes such as leaf type, board plug type, stacked, blade type, thus the mode of intermodule signal interconnection be also each has something to recommend him, it does not have highly versatile, compatible most products interconnection specification.
Along with the introducing of progressively development and the space industry market mechanism of Space Science and Technology, the development of aerospace electron product is distributed Custom Prosthesis by original task and changes to generalization, off the shelf product selection type gradually.
It addition, along with the continuous progress of the whole industry of electronic product, the integrated level raising of circuit brings being substantially improved of properties of product: operating frequency is more and more higher, data throughput capabilities significantly rises.
Under such premise, existing aerospace electron interiors of products mutual contact mode starts to seem unable to do what one wishes, often occurs connecting and excessively complicated causes that productibility is not high, definition causes that uniformity module is not generally applicable repeatedly, cabling does not take into account the problem that is simultaneously connected with etc. of low-and high-frequency signal and modulus signal without specification.
Some Domestic phase shutout, had started to recognize such problem gradually, carried out certain research work in advance in this regard, be directed generally to be incorporated in military computer by versabus technology such as PCI, PXI, VPX, obtained certain achievement.But compare military computer due to aerospace electron product there is functional module dividing mode difference, modulus mixing and control the special circumstances such as computing mixing, it is difficult to utilize above-mentioned general purpose computer bussing technique, temporarily there is no proper ready-made technical scheme.Further, since the control chip that above-mentioned bus relates to mostly is technical grade, army grade is little, also largely limits these technology and applies in aerospace electron product.
For such present situation and products characteristics, realize the generalization of aerospace electron interiors of products module interconnection, standardization, prior art cannot be introduced directly into, for aerospace electron product own characteristic by the general interconnection definition of a set of self-defining space product of tailor and specification, can only achieve the goal with this.
Summary of the invention
For above-mentioned the problems of the prior art, it is an object of the invention to provide a kind of aerospace electron interiors of products bus, for aerospace electron product, there is stronger versatility and compatibility, be conducive to improving the interconnected bus of module interconnecting signal quality and functional reliability, the present invention is by its called after AECI bus (AeroaspaceEmbeddedComponentInterconnectionBUS), change the present situation without suitable bussing technique with this, promote aerospace electron product industry faster to generalization, goods-shelf type development.
For reaching above-mentioned purpose, the technical solution adopted in the present invention is as follows:
A kind of aerospace electron interiors of products bus, mutual for a primary module and multiple information between module, bus signals includes: test signal, system signal, numeral I/O signal, miscellaneous function signal, power supply signal, clock sync signal, bus timing is divided into the primary module operation cycle using wait and the primary module operation cycle two types not using wait, and each type is divided into again two kinds of sequential of read and write.
Except test signal, all the other signals all at least take two signaling points, form Redundancy Design.
Bus physical layer adopts coil spring hole electric connector.
Described test signal includes a debugging serial ports and 12 discrete test signals, and wherein 6 test signal reusables are standard external JTAG signal.
Described system signal includes 4 tunnel interrupt signals, 4 tunnel module chip selection signals, the conventional control signal in 7 roads, address signal and data signal.
The conventional control signal in described 7 roads includes: primary module reset signal, by externally input, from module resets signal, primary module provides, read signal, provided by primary module, write signal, primary module provide, WAIT signal, provided by from module, bus operation cycle stretch-out, DIR signal, being provided by primary module, data flow direction indicates, high for flowing into primary module, low for flowing out primary module, ALE, provided by primary module, address latch signal, according to can cutting from module timing requirements.
Described numeral I/O signal includes 24 tunnel discrete digital amounts, 4 road serial differentials pair, when the serial signal that design uses is non-differential, only use in differential pair+end.
Described miscellaneous function signal is primarily referred to as the function signal using accessory power supply to power, in the majority with analog quantity, including 16 tunnel auxiliary signal inputs and 8 tunnel auxiliary signal outputs.
Described power supply signal divides two kinds, and one is digital power signal, and another kind is accessory power supply signal, and magnitude of voltage is arranged according to different demands.
Described clock sync signal is divided into two kinds, and respectively SYSCLK and IOCLK, SYSCLK are system synchronization clock, and for machine system timing synchronization, IOCLK is I/O functional interface synchronised clock, primary module provide, as the synchronised clock from module corresponding function interface.
Compared with prior art, the present invention has following beneficial effect:
1), the adapter selection scheme that provides under the multiple physical arrangement such as board plug type, stacked, blade type, applied widely, versatility good, adapter is coil spring type, and connection reliability is high；
2), define the aerospace electron product module built based on AECI bus to be distributed and master slave relation, provide multiple configuration structure from module, and defining the naming method deferring to the module that this bus specification designs, product module standardization degree is high, reusability is high；
3) 6 class bus signals, have been divided, 6 class bus signals cover and use power supply widely, parallel, serial, the numeral multi-signal such as I/O, simulation in aerospace electron product, the intermodule providing complete set accesses control handshake, and has reserved a set of test signal that can define flexibly.This bus covers the demand of conventional aerospace electron product, can extensive use；
4), to the distribution on the connectors of 6 class bus signals giving and explicitly define, wherein the signal except test-purpose has all carried out two point Redundancy Design, and application reliability is high；
5) the basic sequential of AECI bus, is defined, it is provided that using and wait and do not use wait both of which, sets forth clear and definite timing requirements, and reserved enough sequential allowances, enforceability is strong, safety is high；
6), defining AECI bus signals electric requirement, adopt Transistor-Transistor Logic level, CMOS compatible level, be Common levels, wide usage is strong.
Accompanying drawing explanation
By reading detailed description non-limiting example made with reference to the following drawings, the other features, objects and advantages of the present invention will become more apparent upon:
Fig. 1 is the specification that the present invention defers to that module is named by AECI bus standard；
Fig. 2 is the signal sequence using the primary module write cycles waited to meet of AECI bus standard of the present invention regulation；
Fig. 3 is the signal sequence that should meet in the primary module read operation cycle not using wait that AECI bus standard of the present invention specifies；
Fig. 4 is the signal sequence that the primary module write cycles not using wait that AECI bus standard of the present invention specifies should meet；
Fig. 5 is the signal sequence using the primary module read operation cycle waited to meet of AECI bus standard of the present invention regulation；
Fig. 6 is the embedded computer composition frame chart applying AECI bus of the present invention.
Detailed description of the invention
Below in conjunction with specific embodiment, the present invention is described in detail.Following example will assist in those skilled in the art and are further appreciated by the present invention, but do not limit the present invention in any form.It should be pointed out that, to those skilled in the art, without departing from the inventive concept of the premise, it is also possible to make some deformation and improvement.These broadly fall into protection scope of the present invention.
AECI bus provided by the present invention is as follows:
1) system constitutes specification
Having in the embedded computer that AECI bus specifies and be only capable of a primary module, the information being controlled by AECI bus is mutual.The configuration of AECI bus standard is supported multiple from module.
2) module design specification
Physical layer recommends 276 heart yearn spring hole electric connectors of HMM276 series, and this series provides board plug type and all spendable plugs and sockets subfamily of blade type and stacked spendable sub-series series.Except test signal, all the other signals all at least take two signaling points, form Redundancy Design.
Corresponding module size is recommended as F2 and the F3 standard size in GJB2355.
Module name should defer to AECI bus standard module Naming conventions, carries out specification name according to Fig. 1 demonstration.
3) signal design specifications
A) test signal
The test signal of AECI bus definition includes a debugging serial ports (RS232) and 12 discrete test signals (purposes can customize, and wherein 7 to 12 reusables are standard external JTAG signal).
B) system signal
The system signal of AECI bus definition includes 4 tunnel interrupt signals, 4 tunnel module chip selection signals, the conventional control signal in 7 roads, address signal (addressing bit wide 20) and data signal (data bit width 16).
The conventional control signal in 7 roads includes:
Primary module reset signal (externally input)；
From module resets signal (primary module provides)；
Read signal (primary module provides)；
Write signal (primary module provides)；
WAIT signal (provides from module, bus operation cycle stretch-out)；
DIR signal (primary module provides, and data flow direction indicates, high for flowing into primary module, low for flowing out primary module)；
ALE (primary module provides, address latch signal, according to can cutting from module timing requirements).
AECI bus supports sixteen-bit system, backward compatible 8 systems.
C) numeral I/O signal
The digital I/O signal of AECI bus definition includes 24 tunnel discrete digital amounts (designer is self-defined in permission), 4 road serial differentials to (RS422 or CAN).When the serial signal that design uses is non-differential, only use in differential pair+end.
D) miscellaneous function signal
The miscellaneous function signal of AECI bus definition is primarily referred to as the function signal using accessory power supply to power, in the majority with analog quantity, including 16 tunnel auxiliary signal inputs and 8 tunnel auxiliary signal outputs.Miscellaneous function signal allows to carry out on this basis self-defined if desired.
E) power supply signal
The power supply signal of AECI bus definition divides two kinds, and one is digital power signal, is generally+5V, and another kind is accessory power supply signal, and magnitude of voltage is arranged according to different demands.
F) clock sync signal
AECI bus definition two clock sync signals, respectively SYSCLK and IOCLK.SYSCLK is system synchronization clock, for machine system timing synchronization.IOCLK is I/O functional interface synchronised clock, is generally provided by primary module, as the synchronised clock from module corresponding function interface.
4) electrical design specification
AECI bus signals adopts Transistor-Transistor Logic level, CMOS compatible level.
Input/output argument index is as follows:
VOLmin=0V, VOLmax=0.55V；
VOHmin=2.4V, VOHmax=VCC；
VILmin=-0.5V, VILmax=0.8V；
VIHmin=2V, VIHmax=5.25V；
IOLmin=IOHmin=20mA；
IILmax=IILmin=200uA.
Signal termination requires as follows:
Primary module input system high level useful signal terminates 1k Ω over the ground；
VCC is terminated 4.7k Ω by primary module input system Low level effective signal；
4.7k Ω is terminated over the ground from module input system high level useful signal；
From module input system Low level effective signal, VCC is terminated 10k Ω.
5) the basic sequential of AECI bus
The basic sequential of AECI bus is divided into the primary module operation cycle using wait (WAIT) and primary module operation cycle two class not using wait (WAIT), and every apoplexy due to endogenous wind is divided into two kinds of sequential of read and write according to action type again.
For above-mentioned four generic operation sequential, clearly giving timing requirements in AECI bus specification, the module timing Design deferring to AECI bus design specification must is fulfilled for these requirements.
AECI bus standard specifies that the primary module read operation cycle not using wait should meet the signal sequence shown in Fig. 2, and time sequence parameter is in Table 1.
Table 1
AECI bus standard specifies that the primary module write cycles not using wait should meet the signal sequence shown in Fig. 3, and time sequence parameter is in Table 2.
Table 2
| Explanation | Minimum | Typical case | Maximum | Unit | Remarks | |
| t1 | Chip select effectively/release delay in address effectively/release time | 5 | 10 | ns | ||
| t8 | With effect, data flow direction effective delay in chip select effective time | 5 | 20 | ns | ||
| t9 | Write low address hold time after release | 0 | 5 | ns | ||
| t10 | With the effect retention time | 200 | 300 | ns | ||
| t11 | Write the data flow direction retention time after release | 0 | 5 | ns | ||
| t12 | Data effective delay is in chip select effective time | 20 | ns | |||
| t13 | Write data hold time after release | 0 | 5 | ns |
AECI bus standard specifies to use the primary module read operation cycle waited should meet the signal sequence shown in Fig. 4, and time sequence parameter is in Table 3.
Table 3
AECI bus standard specifies to use the primary module write cycles waited should meet the signal sequence shown in Fig. 5, and time sequence parameter is in Table 4.
Table 4
| Explanation | Minimum | Typical case | Maximum | Unit | Remarks | |
| t1 | Chip select effectively/release delay in address effectively/release time | 5 | 10 | ns | ||
| t8 | With effect, data flow direction effective delay in chip select effective time | 5 | 20 | ns | ||
| t9 | Write low address hold time after release | 0 | 5 | ns | ||
| t11 | Write the data flow direction retention time after release | 0 | 5 | ns | ||
| t12 | Data effective delay is in chip select effective time | 5 | 20 | ns | ||
| t13 | Write data hold time after release | 0 | 5 | ns | ||
| t16 | Wait that effective delay is in writing effective time | 5 | 20 | ns | ||
| t17 | Write release delay in waiting release time | 10 | 20 | 50 | ns |
Based on above-mentioned AECI bus, develop the formation special embedded computer series products of a series of space flight, with one of which for representative, the specific embodiment of AECI bus has been described.
This type embedded computer forms as shown in Figure 6.
Based on AECI bus definition, have employed board plug type product structure.According to task feature, built-in function being divided into Control on Communication and data two kinds of functional units of process, Control on Communication is as master unit, and data process as from unit, and wherein data processing unit has carried out triple redundance design and improved reliability.
Modular connector has selected the domestic substituted type of proposed model in AECI bus specification, is also the wire spring hole connector of 276.Module have employed F2 standard size.
Adapter definition is with reference to requiring in AECI bus specification to be designed, and signal service condition is as follows:
Test signal employs the 4 discrete test signals in road, and all the other do not use；
System signal employs 3 tunnel interrupt signals and 3 tunnel module chip selection signals, does not use ALE address latch signal in conventional control signal, and system is configured to 16 bit wides；
Numeral I/O signal employs 8 tunnel discrete digital amounts and 2 road serial differentials to signal, and all the other do not use；
Miscellaneous function signal employs 3 tunnels, as analog quantity sampling channel；
Power supply signal employs+5V as digital power signal, and another road+5V is as accessory power supply signal；
Time synchronizing signal employs system synchronization clock signal, does not use interface synchronization clock signal.
The electrical design of all modules is satisfied by the requirement in AECI bus specification, and all module input/output signals have been terminated on request.
Master unit and between unit access adopt be use wait the primary module operation cycle, read and write sequential is satisfied by the corresponding requirements in AECI bus specification.
This type embedded computer have passed through the checking of all of development stage, is applied to space technology field, compared with the like product being provided without AECI bus, has the advantage that
Seriation, generalization degree height, part of module therein has achieved direct multiplexing in homologous series product, and product complete machine structure is the standard type cabinet in national military standard, it is possible to multiplexing, significantly reduces the lead time of subsequent product；
Productibility is high, and the course of processing is not related to special process, adopts common processes can ensure its manufacturing and the quality of production；
Reliability is high, and all of intermodule communication is owing to being satisfied by the timing requirements of AECI bus, and communication reliability is high, remains to normal operation under severe environmental conditions；
Connected mode is easy, and complete machine weight declines to a great extent, and integration degree is high；
Module plug simplicity so that debug more convenient.
276 core connector pinout signal distribution are shown in Table 5 by AECI bus.
Table 5
Above specific embodiments of the invention are described.It is to be appreciated that the invention is not limited in above-mentioned particular implementation, those skilled in the art can make various deformation or amendment within the scope of the claims, and this has no effect on the flesh and blood of the present invention.
Claims (10)
1. an aerospace electron interiors of products bus, mutual for a primary module and multiple information between module, it is characterized in that, bus signals includes: test signal, system signal, numeral I/O signal, miscellaneous function signal, power supply signal, clock sync signal, bus timing is divided into the primary module operation cycle using wait and the primary module operation cycle two types not using wait, and each type is divided into again two kinds of sequential of read and write.
2. aerospace electron interiors of products bus according to claim 1, it is characterised in that except test signal, all the other signals all at least take two signaling points, form Redundancy Design.
3. aerospace electron interiors of products bus according to claim 1, it is characterised in that bus physical layer adopts coil spring hole electric connector.
4. aerospace electron interiors of products bus according to claim 1, it is characterised in that described test signal includes a debugging serial ports and 12 discrete test signals, wherein 6 test signal reusables are standard external JTAG signal.
5. aerospace electron interiors of products bus according to claim 1, it is characterised in that described system signal includes 4 tunnel interrupt signals, 4 tunnel module chip selection signals, the conventional control signal in 7 roads, address signal and data signal.
6. aerospace electron interiors of products bus according to claim 5, it is characterized in that, the conventional control signal in described 7 roads includes: primary module reset signal, by externally input, from module resets signal, provided by primary module, read signal, provided by primary module, write signal, provided by primary module, WAIT signal, provided by from module, bus operation cycle stretch-out, DIR signal, provided by primary module, data flow direction indicates, high for flowing into primary module, low for flowing out primary module, ALE, provided by primary module, address latch signal, according to can cutting from module timing requirements.
7. aerospace electron interiors of products bus according to claim 1, it is characterised in that described numeral I/O signal includes 24 tunnel discrete digital amounts, 4 road serial differentials pair, when the serial signal that design uses is non-differential, only use in differential pair+end.
8. aerospace electron interiors of products bus according to claim 1, it is characterised in that described miscellaneous function signal is primarily referred to as the function signal using accessory power supply to power, in the majority with analog quantity, including 16 tunnel auxiliary signal inputs and 8 tunnel auxiliary signal outputs.
9. aerospace electron interiors of products bus according to claim 1, it is characterised in that described power supply signal divides two kinds, one is digital power signal, and another kind is accessory power supply signal, and magnitude of voltage is arranged according to different demands.
10. aerospace electron interiors of products bus according to claim 1, it is characterized in that, described clock sync signal is divided into two kinds, respectively SYSCLK and IOCLK, SYSCLK is system synchronization clock, and for machine system timing synchronization, IOCLK is I/O functional interface synchronised clock, provided by primary module, as the synchronised clock from module corresponding function interface.
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| CN114124277A (en) * | 2021-10-28 | 2022-03-01 | 康威通信技术股份有限公司 | Time service system and method based on local bus between terminals |
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| CN105760327B (en) | 2019-09-17 |
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