CN103617145A - User-defined bus and achievement method thereof - Google Patents
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Abstract
The invention relates to a user-defined bus and an achievement method thereof. The method includes the steps that the bus comprising a back panel, a main panel, a transmitting panel and a plurality of receiving panels is set, a main control unit, a first programmable logic component, a first single chip microcomputer and a crystal oscillator are arranged in the main panel, a second programmable logic component and a second single chip microcomputer are arranged in the transmitting panel, a third programmable logic component and a third single chip microcomputer are arranged in each receiving plate, high-speed buses are arranged between the first programmable logic component and the second programmable logic component and between the first programmable logic component and the third programmable logic components and are used for transmitting real-time control data, reset signals, handshaking signals, reserved signals, bus clock signals and synchronous clock signals, low-speed buses are arranged between the first single chip microcomputer, and the second single chip microcomputer and between the first single chip microcomputer and the third single chip microcomputers and are used for transmitting initial signals or random detection signals. The user-defined bus can be widely used in magnetic resonance spectrometer systems.
Description
Technical field
The present invention relates to a kind of bus and its implementation, particularly about a kind of self-defined bus for magnetic resonance spectrum instrument system and its implementation
Background technology
At present, the device interiors such as capture card, frequency spectrograph and some large-scale communications, data processing adopt universal high speed bus to carry out data transmission more, universal high speed bus can adopt PCI(Peripheral Component Interconnect, peripheral component interconnect standard) bus, PCIe(PCI Express, the bus interface of new generation) mode such as bus or network.Universal high speed bus have speed fast, can with the advantage such as other hardware compatibilities.For example PCIe the highest current 16X2.0 version can reach 10Gb/s, and network communication also can reach 1Gb/s.Yet use universal high speed bus to have two problems of not evading, the i.e. problem of agreement problem and real-time data transmission.Not only on hardware, need the support of a lot of special chips, and also need complicated agreement support in operating system application software aspect.
Universal high speed bus is applicable to general applied environment, but under specific functional requirement, it is complicated and loaded down with trivial details that universal high speed bus just seems.While adopting universal high speed bus to transmit fragmentary data, there is following problem: (1) can not become chunk data to transmit fragmentary data encapsulation, and takies for a long time universal high speed bus, can cause the obstruction of fragmentary data.(2) detect or control signal comes wait in data queue and sequentially sends, easily cause temporal delay.(3) after fragmentary data are completed by protocol encapsulation, can increase a lot of excessive datas, communication validity is declined.(4) design process of hardware and software complexity and existing data acquisition equipment are all to adopt single high-speed bus to carry out data transmission, and its Software for Design more complicated, lacks the dirigibility that equipment is controlled.(5) universal high speed bus can not meet the requirement of real-time data transmission.
Summary of the invention
For the problems referred to above, the object of this invention is to provide and a kind ofly can meet real-time data transmission requirement, the simple self-defined bus of communications protocol and its implementation.
For achieving the above object, the present invention takes following technical scheme: a kind of self-defined bus, is characterized in that: it comprises backboard, mainboard, expelling plate and some dash receivers; Described backboard adopts passive design, only plays connection function; Described mainboard is connected with described backboard with board form or common cable, and described expelling plate and dash receiver are plugged on described backboard with board form respectively; Described mainboard by described backboard by the clock signal of generation, control data, bus control signal and low speed signal in real time and transfer to respectively described expelling plate and dash receiver; Described expelling plate is processed rear output radio frequency or gradient signal by the signal receiving, described dash receiver according to given parameters receiving magnetic resonance signals, and transfers to described mainboard by the magnetic resonance signal receiving by described backboard according to the bus control signal receiving.
Main control unit, the first programmable logic device (PLD), the first single-chip microcomputer and crystal oscillator are set in described mainboard, the second programmed logic device and second singlechip are set in described expelling plate, the 3rd programmed logic device and the 3rd single-chip microcomputer are set in described dash receiver; The 32 descending control buss in tunnel, 1 road bus clock signal line, 1 tunnel transmitting synchronous clock cable, 1 road reseting signal line, 4 tunnel handshake lines and 1 road preserved signal line are being set respectively between described the first programmable logic device (PLD) and the second programmed logic device and between described the first programmable logic device (PLD) and the 3rd programmed logic device and 32 road uplink receiving buses are being set between described the first programmable logic device (PLD) and the 3rd programmed logic device; Between described the first single-chip microcomputer and second singlechip and between described the first single-chip microcomputer and the 3rd single-chip microcomputer, low speed bus is being set.
Described the first programmable logic device (PLD), the second programmed logic device and the 3rd programmed logic device all adopt a kind of in FPGA and CPLD.
The data line of described the first single-chip microcomputer is connected with described the first programmable logic device (PLD) with address wire, makes the RAM of described the first programmable logic device (PLD) and the outside XRAM that IO mouth becomes described the first single-chip microcomputer; The data line of described second singlechip is connected with described the second programmable logic device (PLD) with address wire, makes the RAM of described the second programmable logic device (PLD) and the outside XRAM that IO mouth becomes described second singlechip; The data line of described the 3rd single-chip microcomputer is connected with described the 3rd programmable logic device (PLD) with address wire, makes the RAM of described the 3rd programmable logic device (PLD) and the outside XRAM that IO mouth becomes described the 3rd single-chip microcomputer.
In described the first programmable logic device (PLD), be provided for selecting to adopt the zone bit of high-speed bus or low speed bus transmission data.
Connect described mainboard and backboard and adopt a kind of of 422 buses, 485 buses, I2C bus and CAN bus for transmitting the cable of low speed signal.
Described clock signal comprises bus clock signal and transmitting synchronous clock signal, and described bus clock signal and transmitting synchronous clock signal are all set to be less than or equal to the signal of 200MHz; Bus control signal comprises reset signal and handshake; Low speed signal comprises initializing signal and random detection signal.
An implementation method for described self-defined bus, it comprises the following steps: 1) bus that comprises backboard, mainboard, expelling plate and some dash receivers is set, main control unit, the first programmable logic device (PLD), the first single-chip microcomputer and crystal oscillator are set in mainboard, the second programmed logic device and second singlechip are set in expelling plate, the 3rd programmed logic device and the 3rd single-chip microcomputer are set in dash receiver, 2) the 32 descending control buss in tunnel, 1 road bus clock signal line, 1 tunnel transmitting synchronous clock cable, 1 road reseting signal line, 4 tunnel handshake lines and 1 road preserved signal line are set respectively between the first programmable logic device (PLD) and the second programmed logic device and between the first programmable logic device (PLD) and the 3rd programmed logic device, 32 road uplink receiving buses are set between the first programmable logic device (PLD) and the 3rd programmed logic device, between the first single-chip microcomputer and second singlechip and between the first single-chip microcomputer and the 3rd single-chip microcomputer, low speed bus is being set respectively, 3) crystal oscillator produces a clock signal and transfers to the first programmable logic device (PLD), by the first programmable logic device (PLD), clock signal is carried out generating a bus clock signal and a transmitting synchronous clock signal after shaping, frequency division processing, bus clock signal and transmitting synchronous clock signal transfer to the second programmed logic device and the 3rd programmed logic device respectively by bus clock signal line and transmitting synchronous clock cable, 4) main control unit produces and controls in real time data and transfer to the first programmable logic device (PLD), the rising edge of transmitting synchronous clock represents the beginning of a transmission cycle, each bus clock in each transmission cycle, the first programmable logic device (PLD) becomes fixed data form to be sent to respectively expelling plate and dash receiver the real-time control data definition receiving by each descending control bus, after processing, the second programmed logic device on expelling plate exports gradient signal or radiofrequency signal, after processing, the 3rd programmed logic device on dash receiver make dash receiver according to the given parameter receiving magnetic resonance signals of main control unit, 5) the 3rd programmed logic device receives after the handshake of the first programmable logic device (PLD) transmission, by uplink receiving bus, the magnetic resonance signal receiving is defined as to fixed data form and transfers to mainboard, when the rising edge of first transmitting synchronous clock starts, first transmission cycle starts, and by uplink receiving bus dash receiver, the N road magnetic resonance signal receiving is defined as to N*32 bit data and transmits, 32 bit data of transmission in each bus clock, when first dash receiver passes through uplink receiving bus transfer data, all the other dash receivers are in high-impedance state, N bus clock cycle in first transmission cycle, by second dash receiver of uplink receiving bus, the magnetic resonance signal receiving being defined as to N*32 bit data transmits, all the other dash receivers are in high-impedance state, the like, until in a transmitting synchronous clock, the magnetic resonance signal end of transmission that all dash receivers receive, continues at first dash receiver of second transmission cycle the magnetic resonance signal that transmission receives, 6) main control unit is controlled initializing signal and the random detection signal that the first single-chip microcomputer produces and is transferred to respectively second singlechip and the 3rd single-chip microcomputer by low speed bus, and expelling plate and dash receiver are carried out to initialization, random Check processing.
The present invention is owing to taking above technical scheme, it has the following advantages: 1, the present invention comprises backboard owing to arranging one, mainboard, the bus of expelling plate and some dash receivers, mainboard is connected with backboard with board form or common cable, expelling plate and dash receiver are plugged on backboard with board form respectively, mainboard transfers to respectively expelling plate and dash receiver by backboard by the clock signal of generation, mainboard, programmable logic device (PLD) and single-chip microcomputer are set respectively in expelling plate and dash receiver, according to the clock signal receiving, programmable logic device (PLD) becomes fixing data layout to transmit the real-time control data definition receiving, therefore the present invention can meet the needs of real-time data transmission, and communications protocol is simple.2, the present invention, due between the first programmable logic device (PLD) and the second programmed logic device and between the first programmable logic device (PLD) and the 3rd programmed logic device, high-speed bus being all set, is respectively used to transmit real-time control data, reset signal, handshake, preserved signal, bus clock signal and transmitting synchronous clock signal; Between the first single-chip microcomputer and second singlechip and between the first single-chip microcomputer and the 3rd single-chip microcomputer, low speed bus is being set, be used for transmitting the low speed signals such as initializing signal or random detection signal, high-speed bus and low speed bus can be worked simultaneously, therefore the present invention can realize transmit high-speed signals and low speed signal simultaneously, thereby saves data transmission and processing time.Based on above advantage, the present invention can be widely used in magnetic resonance spectrum instrument system.
Accompanying drawing explanation
Fig. 1 is one-piece construction schematic diagram of the present invention
Fig. 2 is mainboard of the present invention and backboard annexation schematic diagram
Fig. 3 receives data time sequence schematic diagram in the embodiment of the present invention
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in detail.
As shown in Figure 1, self-defined bus of the present invention comprises backboard 1, mainboard 2, expelling plate 3 and some dash receivers 4, and backboard 1 adopts passive design, only plays connection function; Mainboard 2 is with board form or adopt the common cables such as flat wire to be connected with backboard 1, and expelling plate 3 and dash receiver 4 are plugged on backboard 1 with board form respectively.By backboard 1, mainboard 2 by the clock signal of generation, control the signals such as data, bus control signal and low speed signal in real time and transfer to respectively expelling plate 3 and dash receiver 4; Expelling plate 3 is processed rear output radio frequency or gradient signal by the signal receiving, and dash receiver 4 according to given parameters receiving magnetic resonance signals, and transfers to mainboard 2 by the magnetic resonance signal receiving by backboard 1 according to the bus control signal receiving.
In above-described embodiment, as shown in Figure 1, main control unit 21, the first programmable logic device (PLD) 22, the first single-chip microcomputer 23 and crystal oscillator 24 are set in mainboard 2, the second programmed logic device 25 and second singlechip 26 are set in expelling plate 3, the 3rd programmed logic device 27 and the 3rd single-chip microcomputer 28 are set in dash receiver 4.As shown in Figure 2, between the first programmable logic device (PLD) 22 and the second programmed logic device 25 and between the first programmable logic device (PLD) 22 and the 3rd programmed logic device 27, high-speed bus is all being set, high-speed bus is included between the first programmable logic device (PLD) 22 and the second programmed logic device 25 and between the first programmable logic device (PLD) 22 and the 3rd programmed logic device 27 the descending control bus in 32 road is set respectively, 1 road bus clock signal line, 1 tunnel transmitting synchronous clock cable, 1 road reseting signal line, 4 tunnel handshake lines and 1 road preserved signal line and between the first programmable logic device (PLD) 22 and the 3rd programmed logic device 27,32 road uplink receiving bus is set, mainboard 2 is controlled data by the 32 descending control buss in tunnel in real time to expelling plate 3 and dash receiver 4 transmission, dash receiver 4 transfers to mainboard 2 by 32 road uplink receiving buses by the real-time magnetic resonance signal receiving, mainboard 2 provides bus clock signal and transmitting synchronous clock signal by bus clock signal line and transmitting synchronous clock cable for expelling plate 3 and dash receiver 4, and mainboard 2 provides reset signal and handshake etc. by reseting signal line and handshake line for expelling plate 3 and dash receiver 4.Between the first single-chip microcomputer 23 and second singlechip 26 and between the first single-chip microcomputer 23 and the 3rd single-chip microcomputer 28, low speed bus is being set, main control unit 21 is controlled initialization that the first single-chip microcomputers 23 produce, with low speed signals such as machine testings, by low speed bus, is transmitted.
In above-described embodiment, clock signal comprises bus clock signal and transmitting synchronous clock signal; Bus control signal comprises reset signal and handshake etc.; Low speed signal comprises initializing signal and random detection signal etc.
In above-described embodiment, the first programmable logic device (PLD) 22, the second programmed logic device 25 and the 3rd programmed logic device 27 all can adopt FPGA(Field Programmable Gate Array, field programmable gate array) and CPLD(Complex Programmable Logic Device, a kind of CPLD).
In above-described embodiment, the data line of the first single-chip microcomputer 23 is connected with the first programmable logic device (PLD) 22 with address wire, makes the RAM of the first programmable logic device (PLD) 22 and the outside XRAM that IO mouth becomes the first single-chip microcomputer 23.
The data line of second singlechip 26 is connected with the second programmable logic device (PLD) 25 with address wire, makes the RAM of the second programmable logic device (PLD) 25 and the outside XRAM that IO mouth becomes second singlechip 26.
The data line of the 3rd single-chip microcomputer 28 is connected with the 3rd programmable logic device (PLD) 27 with address wire, makes the RAM of the 3rd programmable logic device (PLD) 27 and the outside XRAM that IO mouth becomes the 3rd single-chip microcomputer 28.
In above-described embodiment, between each descending control bus and each uplink receiving bus, be provided with ground wire, to improve transmission range and the interference free performance of each bus.
In above-described embodiment, bus clock signal and transmitting synchronous clock signal are all set to be less than or equal to the signal of 200MHz.
In above-described embodiment, in the first programmable logic device (PLD) 22, zone bit is set, for selecting to adopt high-speed bus or low speed bus transmission data.
In above-described embodiment, connect mainboard 2 and for transmitting the cable of low speed signal, can adopt 422 buses, 485 buses, I2C(Inter Integrated Circuit with backboard 1, internal integrated circuit) a kind of in bus bus and CAN(Controller Area Network, controller local area network).
The implementation method of self-defined bus of the present invention comprises the following steps:
1) bus that comprises backboard 1, mainboard 2, expelling plate 3 and some dash receivers 4 is set; Main control unit 21, the first programmable logic device (PLD) 22, the first single-chip microcomputer 23 and crystal oscillator 24 are set in mainboard 2, the second programmed logic device 25 and second singlechip 26 are set in expelling plate 3, the 3rd programmed logic device 27 and the 3rd single-chip microcomputer 28 are set in dash receiver 4.
2) the 32 descending control buss in tunnel, 1 road bus clock signal line, 1 tunnel transmitting synchronous clock cable, 1 road reseting signal line, 4 tunnel handshake lines and 1 road preserved signal line are set respectively between the first programmable logic device (PLD) 22 and the second programmed logic device 25 and between the first programmable logic device (PLD) 22 and the 3rd programmed logic device 27,32 road uplink receiving buses are set between the first programmable logic device (PLD) 22 and the 3rd programmed logic device 27; Between the first single-chip microcomputer 23 and second singlechip 26 and between the first single-chip microcomputer 23 and the 3rd single-chip microcomputer 28, low speed bus is being set respectively.
3) crystal oscillator 24 produces a clock signal and transfers to the first programmable logic device (PLD) 22, according to actual needs, by 22 pairs of clock signals of the first programmable logic device (PLD), undertaken after shaping, frequency division etc. are processed generating a bus clock signal and a transmitting synchronous clock signal, bus clock signal and transmitting synchronous clock signal transfer to the second programmed logic device 25 and the 3rd programmed logic device 27 respectively by bus clock signal line and transmitting synchronous clock cable.
4) main control unit 21 produces and controls in real time data and transfer to the first programmable logic device (PLD) 22, the rising edge of transmitting synchronous clock represents the beginning of a transmission cycle, each bus clock in each transmission cycle, the first programmable logic device (PLD) 22 becomes fixed data form to be sent to respectively expelling plate 3 and dash receiver 4 the real-time control data definition receiving by each descending control bus, after processing, the second programmed logic device 25 on expelling plate 3 exports gradient signal or the radiofrequency signal of certain waveform, after processing, the 3rd programmed logic device 27 on dash receiver 4 make dash receiver 4 according to the given parameter receiving magnetic resonance signals of main control unit 21.
5) the 3rd programmed logic device 27 on dash receiver 4 receives after the handshake of the first programmable logic device (PLD) 22 transmissions on mainboard 2, by uplink receiving bus, the magnetic resonance signal receiving is defined as to fixed data form and transfers to mainboard 2.
When the rising edge of first transmitting synchronous clock starts, first transmission cycle starts, and by uplink receiving bus dash receiver 4, the N road magnetic resonance signal receiving is defined as to N*32 bit data and transmits, 32 bit data of transmission in each bus clock.When first dash receiver 4 passes through uplink receiving bus transfer data, all the other dash receivers 4 are in high-impedance state; N bus clock cycle in first transmission cycle, by second dash receiver 4 of uplink receiving bus, the magnetic resonance signal receiving being defined as to N*32 bit data transmits, all the other dash receivers 4 are in high-impedance state, the like, until in a transmitting synchronous clock, the magnetic resonance signal end of transmission that all dash receivers 4 receive, continues at first dash receiver of second transmission cycle 4 magnetic resonance signal that transmission receives.Can change according to actual needs the frequency of transmitting synchronous clock and the quantity of dash receiver 4.
6) main control unit 21 is controlled initialization that the first single-chip microcomputers 23 produce, with low speed signals such as machine testings, by low speed bus, is transferred to respectively second singlechip 26 and the 3rd single-chip microcomputer 28, to expelling plate 3 and dash receiver 4 carry out initialization, with processing such as machine testings.
Embodiment: as shown in Figure 3, crystal oscillator 24 produces a clock signal and transfers to the first programmable logic device (PLD) 22, by 22 pairs of clock signals of the first programmable logic device (PLD), is undertaken after shaping, frequency division etc. are processed generating the bus clock signal line of a 50MHz and the transmitting synchronous clock signal of a 2MHz.The transmitting synchronous clock of each 2MHz, for identifying the beginning of a transmission cycle, has the bus clock of 25 50MHz in the transmitting synchronous clock of each 2MHz.First transmission cycle starts, and by first dash receiver 4 of uplink receiving bus, the 4 road magnetic resonance signals that receive is defined as to 4*32 bit data and transmits, 32 bit data of transmission in the bus clock of each 50MHz; First dash receiver 4 is by the bus clock cycle of uplink receiving bus transfer data, and all the other dash receivers 4 are in high-impedance state.In bus clock cycle after the 4 road magnetic resonance signal end of transmissions that first dash receiver 4 receives, by second dash receiver 4 of uplink receiving bus, the 4 road magnetic resonance signals that receive are defined as to 4*32 bit data and transmit, 32 bit data of transmission in the bus clock of each 50MHz; Second dash receiver 4 is by the bus clock cycle of uplink receiving bus transfer data, all the other dash receivers 4 are in high-impedance state, the like, until in the transmitting synchronous clock of a 2MHz, the magnetic resonance signal end of transmission that all dash receivers 4 receive, continues at first dash receiver of second transmission cycle 4 magnetic resonance signal that transmission receives.
The various embodiments described above are only for illustrating the present invention; wherein the structure of each parts, connected mode and method step etc. all can change to some extent; every equivalents of carrying out on the basis of technical solution of the present invention and improvement, all should not get rid of outside protection scope of the present invention.
Claims (10)
1. a self-defined bus, is characterized in that: it comprises backboard, mainboard, expelling plate and some dash receivers; Described backboard adopts passive design, only plays connection function; Described mainboard is connected with described backboard with board form or common cable, and described expelling plate and dash receiver are plugged on described backboard with board form respectively; Described mainboard by described backboard by the clock signal of generation, control data, bus control signal and low speed signal in real time and transfer to respectively described expelling plate and dash receiver; Described expelling plate is processed rear output radio frequency or gradient signal by the signal receiving, described dash receiver according to given parameters receiving magnetic resonance signals, and transfers to described mainboard by the magnetic resonance signal receiving by described backboard according to the bus control signal receiving.
2. a kind of self-defined bus as claimed in claim 1, it is characterized in that: main control unit, the first programmable logic device (PLD), the first single-chip microcomputer and crystal oscillator are set in described mainboard, the second programmed logic device and second singlechip are set in described expelling plate, the 3rd programmed logic device and the 3rd single-chip microcomputer are set in described dash receiver; The 32 descending control buss in tunnel, 1 road bus clock signal line, 1 tunnel transmitting synchronous clock cable, 1 road reseting signal line, 4 tunnel handshake lines and 1 road preserved signal line are being set respectively between described the first programmable logic device (PLD) and the second programmed logic device and between described the first programmable logic device (PLD) and the 3rd programmed logic device and 32 road uplink receiving buses are being set between described the first programmable logic device (PLD) and the 3rd programmed logic device; Between described the first single-chip microcomputer and second singlechip and between described the first single-chip microcomputer and the 3rd single-chip microcomputer, low speed bus is being set.
3. a kind of self-defined bus as claimed in claim 1, is characterized in that: described the first programmable logic device (PLD), the second programmed logic device and the 3rd programmed logic device all adopt a kind of in FPGA and CPLD.
4. a kind of self-defined bus as claimed in claim 2, is characterized in that: described the first programmable logic device (PLD), the second programmed logic device and the 3rd programmed logic device all adopt a kind of in FPGA and CPLD.
5. a kind of self-defined bus as claimed in claim 1 or 2 or 3 or 4, it is characterized in that: the data line of described the first single-chip microcomputer is connected with described the first programmable logic device (PLD) with address wire, makes the RAM of described the first programmable logic device (PLD) and the outside XRAM that IO mouth becomes described the first single-chip microcomputer; The data line of described second singlechip is connected with described the second programmable logic device (PLD) with address wire, makes the RAM of described the second programmable logic device (PLD) and the outside XRAM that IO mouth becomes described second singlechip; The data line of described the 3rd single-chip microcomputer is connected with described the 3rd programmable logic device (PLD) with address wire, makes the RAM of described the 3rd programmable logic device (PLD) and the outside XRAM that IO mouth becomes described the 3rd single-chip microcomputer.
6. a kind of self-defined bus as claimed in claim 1 or 2 or 3 or 4, is characterized in that: the zone bit that is provided for selecting to adopt high-speed bus or low speed bus transmission data in described the first programmable logic device (PLD).
7. a kind of self-defined bus as claimed in claim 5, is characterized in that: the zone bit that is provided for selecting to adopt high-speed bus or low speed bus transmission data in described the first programmable logic device (PLD).
8. a kind of self-defined bus as described in claim 1～7 any one, is characterized in that: connect described mainboard and backboard and adopt a kind of of 422 buses, 485 buses, I2C bus and CAN bus for transmitting the cable of low speed signal.
9. a kind of self-defined bus as described in claim 1～8 any one, it is characterized in that: described clock signal comprises bus clock signal and transmitting synchronous clock signal, described bus clock signal and transmitting synchronous clock signal are all set to be less than or equal to the signal of 200MHz; Bus control signal comprises reset signal and handshake; Low speed signal comprises initializing signal and random detection signal.
10. an implementation method for self-defined bus as described in claim 1～9 any one, it comprises the following steps:
1) bus that comprises backboard, mainboard, expelling plate and some dash receivers is set; Main control unit, the first programmable logic device (PLD), the first single-chip microcomputer and crystal oscillator are set in mainboard, the second programmed logic device and second singlechip are set in expelling plate, the 3rd programmed logic device and the 3rd single-chip microcomputer are set in dash receiver;
2) the 32 descending control buss in tunnel, 1 road bus clock signal line, 1 tunnel transmitting synchronous clock cable, 1 road reseting signal line, 4 tunnel handshake lines and 1 road preserved signal line are set respectively between the first programmable logic device (PLD) and the second programmed logic device and between the first programmable logic device (PLD) and the 3rd programmed logic device, 32 road uplink receiving buses are set between the first programmable logic device (PLD) and the 3rd programmed logic device; Between the first single-chip microcomputer and second singlechip and between the first single-chip microcomputer and the 3rd single-chip microcomputer, low speed bus is being set respectively;
3) crystal oscillator produces a clock signal and transfers to the first programmable logic device (PLD), by the first programmable logic device (PLD), clock signal is carried out generating a bus clock signal and a transmitting synchronous clock signal after shaping, frequency division processing, bus clock signal and transmitting synchronous clock signal transfer to the second programmed logic device and the 3rd programmed logic device respectively by bus clock signal line and transmitting synchronous clock cable;
4) main control unit produces and controls in real time data and transfer to the first programmable logic device (PLD), the rising edge of transmitting synchronous clock represents the beginning of a transmission cycle, each bus clock in each transmission cycle, the first programmable logic device (PLD) becomes fixed data form to be sent to respectively expelling plate and dash receiver the real-time control data definition receiving by each descending control bus, after processing, the second programmed logic device on expelling plate exports gradient signal or radiofrequency signal, after processing, the 3rd programmed logic device on dash receiver make dash receiver according to the given parameter receiving magnetic resonance signals of main control unit,
5) the 3rd programmed logic device receives after the handshake of the first programmable logic device (PLD) transmission, by uplink receiving bus, the magnetic resonance signal receiving is defined as to fixed data form and transfers to mainboard;
When the rising edge of first transmitting synchronous clock starts, first transmission cycle starts, and by uplink receiving bus dash receiver, the N road magnetic resonance signal receiving is defined as to N*32 bit data and transmits, 32 bit data of transmission in each bus clock; When first dash receiver passes through uplink receiving bus transfer data, all the other dash receivers are in high-impedance state; N bus clock cycle in first transmission cycle, by second dash receiver of uplink receiving bus, the magnetic resonance signal receiving being defined as to N*32 bit data transmits, all the other dash receivers are in high-impedance state, the like, until in a transmitting synchronous clock, the magnetic resonance signal end of transmission that all dash receivers receive, continues at first dash receiver of second transmission cycle the magnetic resonance signal that transmission receives;
6) main control unit is controlled initializing signal and the random detection signal that the first single-chip microcomputer produces and is transferred to respectively second singlechip and the 3rd single-chip microcomputer by low speed bus, and expelling plate and dash receiver are carried out to initialization, random Check processing.
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