CN105742229B - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN105742229B CN105742229B CN201410756554.4A CN201410756554A CN105742229B CN 105742229 B CN105742229 B CN 105742229B CN 201410756554 A CN201410756554 A CN 201410756554A CN 105742229 B CN105742229 B CN 105742229B
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Abstract
A kind of forming method of semiconductor structure, comprising: substrate and the first interlayer dielectric layer are provided；The second interlayer dielectric layer is formed in the first interlayer dielectric layer surface；Photoresist layer is formed in device region the second interlayer dielectric layer surface；Etching cavity is provided, the distance between external zones and etching cavity cavity wall are less than the distance between device region and etching cavity cavity wall；In etching cavity, along the second interlayer dielectric layer of etched features area, contact hole is formed in the second interlayer dielectric layer of device region, the temperature of the cavity wall of etching cavity is higher than the indoor temperature of etch chamber, and forms polymeric layer in external zones substrate；Remove polymeric layer；Form the conductive plunger for filling full contact hole.The present invention reduces the content of polymeric impurities in polymeric layer, so that the difficulty of the first bevel edge etching processing removal polymeric layer reduces, and polymeric layer can be completely removed, avoid polymeric layer flake-off from substrate from improving the production yield of semiconductor structure in other substrates.
Description
Technical field
The present invention relates to field of semiconductor fabrication technology, in particular to a kind of forming method of semiconductor structure.
Background technique
As integrated circuit develops to super large-scale integration, the current densities of IC interior are increasing, institute
The number of elements for including is also more and more.In semiconductor integrated circuit, metal-oxide semiconductor (MOS) (MOS, Metal Oxide
Semiconductor) one of element wherein mostly important when transistor.
Existing MOS transistor technique is to form gate structure on a semiconductor substrate, in gate structure opposite sides
Source region and drain region are formed in semiconductor substrate；Then contact hole (Contact is formed on gate structure, source region and drain region
Via), metal being filled in contact hole and forming conductive plunger, external circuit and gate structure, source region and leakage are made by conductive plunger
Area's electrical connection.
However, the production yield and chip quantum of output of prior art semiconductor structure are still to be improved.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of semiconductor structure, and removal is located in external zones substrate
Polymeric layer avoids polymeric layer flake-off from substrate from falling in other substrates, polymeric layer is avoided to cause subsequent technique
Adverse effect；The content of the polymeric impurities in the polymeric layer that substrate external zones is formed is reduced simultaneously, so that carrying out first
The technology difficulty that bevel edge etching processing removes polymeric layer reduces, and improves semiconductor production yield and chip quantum of output.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising: provide substrate and position
In the first interlayer dielectric layer of substrate surface, the substrate includes the external zones of device region and the encirclement device region, described
Grid conductive layer is formed in first interlayer dielectric layer of device region, the grid conductive layer top and the first interlayer dielectric layer top are neat
It is flat；The second interlayer dielectric layer is formed in the grid conductive layer surface, device region and external zones the first interlayer dielectric layer surface；Institute
It states device region the second interlayer dielectric layer surface and forms the photoresist layer with the first opening；Etching cavity is provided, will be had described
The substrate of photoresist layer is placed in etching cavity, and the distance between the external zones and etching cavity cavity wall are less than device region and carve
Lose the distance between chamber cavity wall；In the etching cavity, along the first opening second interlayer dielectric layer of etched features area
Until exposing grid conductive layer surface, contact hole is formed in second interlayer dielectric layer of device region, the etching cavity
The temperature of cavity wall is higher than the indoor temperature of etch chamber, and polymerization is formed in the external zones substrate during forming contact hole
Nitride layer；Remove the photoresist layer；First bevel edge etching processing is carried out to the polymeric layer, removes the polymeric layer；Shape
At the conductive plunger for filling the full contact hole.
Optionally, the processing step for forming the grid conductive layer includes: the shape in first interlayer dielectric layer of device region
At the second opening；The gate-conductive film of full second opening of filling is formed, and the gate-conductive film is also covered in the first interlayer Jie
Matter layer surface；Grinding removal is higher than the gate-conductive film of the first interlayer dielectric layer surface, and it is conductive to form grid in second opening
Layer, and after milling, conductive adhesive layer, the material of the conduction adhesive layer are formed in external zones the first interlayer dielectric layer surface
It is identical as grid conductive layer material.
Optionally, it after forming the grid conductive layer, before formation second interlayer dielectric layer, further comprises the steps of:
Second bevel edge etching processing is carried out to the conductive adhesive layer, removes the conductive adhesive layer.
Optionally, the temperature of the cavity wall of the etching cavity is 80 degrees Celsius to 200 degrees Celsius；The etch chamber is indoor
Temperature is 20 degrees Celsius to 80 degrees Celsius.
Optionally, the first bevel edge etching processing is carried out in bevel edge etching machine；The first bevel edge etching processing
Etching gas is fluoro-gas, wherein fluoro-gas includes CF4、CHF3、NF3Or SF6。
Optionally, the technological parameter of the first bevel edge etching processing are as follows: etching gas includes CH4And SF6, also to etching
CO is passed through in chamber2And N2, CF4Flow is 10sccm to 500sccm, SF6Flow is 10sccm to 100sccm, CO2Flow is
10sccm to 100sccm, N2Flow is 100sccm to 500sccm, and providing source power is 200 watts to 1000 watts.
Optionally, after the first bevel edge etching processing, the external zones substrate surface is not exposed.
Optionally, after carrying out the first bevel edge etching processing, the external zones substrate surface is by the first inter-level dielectric
Layer covering；Alternatively, after carrying out the first bevel edge etching processing, the external zones substrate surface by the first interlayer dielectric layer with
And the second interlayer dielectric layer covering of segment thickness.
Optionally, the processing step for forming the conductive plunger includes: at the top of second interlayer dielectric layer of device region
On surface, external zones substrate and contact hole bottom and side wall surface forms electrically conductive barrier, and formation is covered in conductive resistance
Barrier surface and the conductor layer for filling full contact hole, and it is higher than the second interlayer dielectric layer of device region top at the top of the conductor layer
Portion surface；Grinding removal is higher than the conductor layer and electrically conductive barrier of the second interlayer dielectric layer of device region top surface, is formed
Fill the conductive plunger of full contact hole.
Optionally, it is described outer after the grinding when external zones substrate surface is covered by the first interlayer dielectric layer
Area's the first interlayer dielectric layer surface is enclosed to be covered by the conductor layer of electrically conductive barrier and segment thickness.
Optionally, the external zones surface is covered by the second interlayer dielectric layer of the first interlayer dielectric layer and segment thickness
When, after the grinding, external zones the second interlayer dielectric layer surface is by the conduction of electrically conductive barrier and segment thickness
The covering of body layer.
Optionally, the first bevel edge etching processing is multiple tracks etching technics, after guaranteeing the first bevel edge etching processing, outside
Area's substrate surface is enclosed not to be exposed.
Optionally, the material of the electrically conductive barrier is Ti, TiN, Ta, TaN, WN, Cu, Al or W；The conductor layer
Material is Ti, TiN, Ta, TaN, WN, Cu, Al or W.
Optionally, while etching second interlayer dielectric layer of device region forms the contact hole, external zones is etched
Second interlayer dielectric layer.
Optionally, while forming the contact hole, the second interlayer dielectric layer of external zones is etched removal, the polymerization
Nitride layer is located at external zones the first interlayer dielectric layer surface；Alternatively, while forming the contact hole, external zones segment thickness
Second interlayer dielectric layer is etched removal, and the polymeric layer is located at the remaining second interlayer dielectric layer surface of external zones.
Optionally, it before forming the conductive plunger, further comprises the steps of: and the contact hole is carried out at wet-cleaning
Reason；The processing of Ar plasma bombardment is carried out to the contact hole.
Optionally, the photoresist layer exposes external zones the second interlayer dielectric layer surface；Using wafer edge exposure
Method forms the photoresist layer.
Optionally, the processing step for forming the photoresist layer includes: in the second interlayer of the device region and external zones
Dielectric layer surface forms initial lithographic glue-line；Place is exposed to the initial lithographic glue-line of external zones the second interlayer dielectric layer surface
Reason, while processing is exposed to the initial lithographic glue-line region of the first opening to be formed；After being exposed processing, to first
Beginning photoresist layer carries out development treatment, forms the photoresist layer.
Optionally, the material of first interlayer dielectric layer is silica, low k dielectric materials or ultra-low k dielectric material；Institute
The material for stating the second interlayer dielectric layer is silica, low k dielectric materials or ultra-low k dielectric material.
Optionally, the material of the grid conductive layer includes Ti, TiN, Ta, TaN, WN, Cu, Al or W；The device region substrate
Gate dielectric layer is also formed between grid conductive layer.
Compared with prior art, technical solution of the present invention has the advantage that
The present invention provides a kind of forming method of semiconductor structure, in the etching cavity that etching forms contact hole, periphery
The distance between area and etching cavity cavity wall are less than the distance between device area etching cavity cavity wall, and etching cavity cavity wall
Temperature is higher than the indoor temperature of etch chamber, so that the warm-up movement for being subject to the by-product near substrate external zones is stronger, to make
The polymer content obtained in the polymeric layer formed in external zones substrate reduces, and then reduces the work of the first bevel edge etching processing
Skill difficulty enables the first bevel edge etching processing to etch the removal polymeric layer completely.The present invention can completely remove poly-
Nitride layer is closed, prevents polymeric layer from peeling off from the substrate, and prevent subsequent polymer layer from causing adverse effect to subsequent technique, mentions
High semiconductor structure production yield and chip quantum of output.
Further, the temperature of the cavity wall of etching cavity is 80 degrees Celsius to 200 degrees Celsius, is prevented since cavity wall temperature is excessively high
And cause substrate to rupture, while keeping the polymer warm-up movement near external zones stronger, it is effective to reduce polymer in polymeric layer
Impurity content.
Further, it during forming grid conductive layer, is formed in external zones the first interlayer dielectric layer surface conductive attached
Layer, it is described conduction adhesive layer material it is identical as the material of grid conductive layer.The present invention before forming the second interlayer dielectric layer,
The conductive adhesive layer is removed, avoids conductive adhesive layer from peeling off from substrate and other substrates is polluted；Also, it prevents subsequent
Conductive adhesive layer is formed between the first interlayer dielectric layer and the second interlayer dielectric layer, so that the first inter-level dielectric of external zones
Layer and the second interlayer dielectric layer adhesiveness are strong；The polymeric layer being subsequently formed can also be avoided to be attached to conductive layer adhesive layer simultaneously
On, avoid the byproduct layer in external zones substrate excessively complicated.
Further, after the first bevel edge etching processing of the invention, external zones substrate surface is not exposed, external zones substrate
Surface is covered by the first interlayer dielectric layer, correspondingly, the subsequent electrically conductive barrier formed in external zones is located at the first inter-level dielectric
Layer surface so that between the electrically conductive barrier and substrate of external zones have stronger adhesiveness, prevent formed conductive plunger it
The electrically conductive barrier of external zones is peeled off from substrate afterwards, to further increase the production yield of semiconductor structure.If external zones
Electrically conductive barrier directly contacted with substrate surface, due to the adhesiveness between electrically conductive barrier and substrate be much smaller than conductive barrier
Adhesiveness between layer and the first interlayer dielectric layer, then the electrically conductive barrier of external zones is easy from base after forming conductive plunger
It is peeled off on bottom.
Further, after the first bevel edge etching processing, external zones substrate surface is by the first interlayer dielectric layer and segment thickness
The second interlayer dielectric layer covering, likewise, due to the adhesiveness between external zones electrically conductive barrier and the second interlayer dielectric layer
It is relatively strong, to prevent the external zones electrically conductive barrier after forming conductive plunger from peeling off from substrate, further increase semiconductor
The production yield of structure.
Further, photoresist layer is formed using the method for wafer edge exposure, prevents photoresist layer from flowing to substrate back
Substrate cleaning degree is improved in face.
Detailed description of the invention
Fig. 1 to Figure 12 is the schematic diagram of the section structure that the semiconductor structure that one embodiment of the invention provides forms process.
Specific embodiment
It can be seen from background technology that substrate is easy to be damaged or pollute during the device production of the prior art, leads to half
The production yield of conductor structure is low, chip quantum of output is low.
It has been investigated that in semiconductor fabrication, need to be related to multiple working procedure, and dry etch process is usually to make
Common step in the process.Dry etch process makes after obtaining energy using reaction gas, passes through reaction pair physically or chemically
Etching object performs etching.But in etching process or in other technical process, it will usually in the adjacent edges shape of substrate
At by-product, for example, the polymer comprising elements such as carbon, oxygen, nitrogen, fluorine, and the low quality film generated due to edge effect
Layer etc..
In subsequent technical process, the adhesiveness between the by-product and substrate can finally die down and lead to the by-product
Object spallation or peeling in substrate transfer process, generally fall on other substrates, so that other substrates are caused to damage or be polluted,
Seriously affect the production yield of semiconductor structure.
Particularly, when the polymeric impurities content in by-product is big or by-product type is complex, by-product is more
It is easily peeled off from substrate, and the difficulty for removing the by-product in basal edge region is bigger.
For this purpose, the present invention provides a kind of forming method of semiconductor structure, in the etching cavity that etching forms contact hole,
The distance between external zones and etching cavity cavity wall are less than the distance between device area etching cavity cavity wall, and etch chamber chamber
The temperature of wall is higher than the indoor temperature of etch chamber, so that the warm-up movement for being subject to the by-product near substrate external zones is stronger, from
And the polymer content in the polymeric layer formed in external zones substrate is reduced, and then reduce the first bevel edge etching processing
Technology difficulty, enable the first bevel edge etching processing to etch the removal polymeric layer completely.The present invention can be gone completely
It except polymeric layer, prevents polymeric layer from peeling off from the substrate, and prevents subsequent polymer layer from causing bad shadow to subsequent technique
It rings, improves semiconductor structure production yield and chip quantum of output.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 1 to Figure 12 is the schematic diagram of the section structure that the semiconductor structure that one embodiment of the invention provides forms process.
Referring to FIG. 1, providing substrate 100, the substrate 100 includes device region 110 and the encirclement device region 110
External zones 120.
The material of the substrate 100 is silicon, germanium, SiGe, silicon carbide, GaAs or gallium indium；The substrate 100 may be used also
Think the germanium on the silicon or insulator on insulator.
The device region 110 is the region for being subsequently formed semiconductor devices, and the external zones 120 is along 100 radius side of substrate
Upward width can be adjusted according to specific manufacture craft.
In the present embodiment, the external zones 120 includes the first external zones and the second external zones, wherein the first peripheral position
Between device region 110 and the second external zones.
In one embodiment, the first external zones surface is parallel with 110 surface of device region, and the second external zones surface is oblique
Face.In another embodiment, the first external zones and the second external zones surface are parallel with 110 surface of device region.In other implementations
In example, the external zones surface can also be ladder-like, zigzag etc..
Referring to FIG. 2, forming the first interlayer dielectric layer 101 on 100 surface of substrate.
First interlayer dielectric layer 101 is covered in 100 surface of device region 110 and 120 substrate of external zones.Using chemistry
Vapor deposition, physical vapour deposition (PVD) or atom layer deposition process form first interlayer dielectric layer 101.
The material of the first medium layer 101 is silica, (low k dielectric materials refer to that opposite dielectric is normal to low k dielectric materials
Number be lower than 3.9 dielectric materials) or ultra-low k dielectric material (ultra-low k dielectric material refer to relative dielectric constant be lower than 2.5 medium
Material).
When the material of the first medium layer 101 is low .k dielectric material or ultra-low k dielectric material, first medium layer 101
Material be SiOH, SiCOH, FSG (silica of fluorine doped), BSG (silica of boron-doping), the PSG (titanium dioxide of p-doped
Silicon), BPSG (silica of boron-doping phosphorus), hydrogenation silsesquioxane (HSQ, (HSiO1.5)n) or methyl silsesquioxane (MSQ,
(CH3SiO1.5)n)。
The material of first interlayer dielectric layer 101 described in the present embodiment is silica.In the present embodiment, in the device region
Pseudo- grid 131,131 top of puppet grid and 101 top of the first interlayer dielectric layer are also formed in 110 first interlayer dielectric layers 101
It flushes, the material of the puppet grid 131 can be polysilicon.After the pseudo- grid 131 of subsequent removal, in 110 first layer of device region
Between the second opening is formed in dielectric layer 101.
Before forming the pseudo- grid 131 and the first interlayer dielectric layer 101, heat can also be formed on 100 surface of substrate
Oxide layer, in part of devices area, 110 substrate, 101 surface forms gate dielectric layer, and the grid conductive layer being subsequently formed is located at gate dielectric layer
Surface, the material of the gate dielectric layer are that (high K medium material refers to that relative dielectric constant is big for silica or high K medium material
In the dielectric material of the relative dielectric constant of silica).
Referring to FIG. 3, forming the second opening 102 in 110 first interlayer dielectric layer 101 of device region.
Specifically, the removal pseudo- grid 131 (referring to Fig. 2), the shape in 110 first interlayer dielectric layer 101 of device region
At the second opening 102；The position of second opening 102 and width dimensions correspond to the position of grid conductive layer being subsequently formed and
Width dimensions, second opening 102 run through first interlayer dielectric layer 101.
As a specific embodiment, the processing step for forming second opening 102 includes: to be situated between in first interlayer
101 surface of matter layer forms patterned mask layer, has third opening in the patterned mask layer；With described patterned
Mask layer is exposure mask, and being open to etch along third removes pseudo- grid 131, is formed and is open through the second of the first interlayer dielectric layer 101
102。
Referring to FIG. 4, forming the gate-conductive film 103 of full second opening 102 (referring to Fig. 3) of filling, and the grid are led
Electrolemma 103 is also covered in 101 surface of the first interlayer dielectric layer.
The material of the gate-conductive film 103 includes Ti, TiN, Ta, TaN, WN, Cu, Al or W.
The material of gate-conductive film 103 described in the present embodiment is Al, forms the grid using physical gas-phase deposition and leads
Electrolemma 103.
The grid conductive layer film 103 had both been covered in 110 first interlayer dielectric layer of device region, 101 surface, was also covered in periphery
120 first interlayer dielectric layer of area, 101 surface.
Referring to FIG. 5, grinding removal is higher than the gate-conductive film 103 (referring to Fig. 4) on 101 surface of the first interlayer dielectric layer,
Grid conductive layer 104 is formed in second opening 102 (referring to Fig. 3).
Specifically, the grid that grinding removal is higher than 101 surface of the first interlayer dielectric layer are conductive using chemical mechanical milling tech
Film 103.
Since the tool of substrate 100 has the dimensions, during the grinding process, the gate-conductive film 103 of external zones 120 is ground
Removal rates are usually less than the rate that 110 gate-conductive film 103 of device region is removed, and cause after milling, in external zones 120
First interlayer dielectric layer, 101 surface is formed with conductive adhesive layer 105, and the conduction adhesive layer 105 is that external zones 120 is not ground
The part gate-conductive film 103 removed is ground off, therefore the material of the conductive adhesive layer 105 is identical as 104 material of grid conductive layer.
In the present embodiment, the material of the conductive adhesive layer 105 is Al.
Referring to FIG. 6, carrying out the second bevel edge etching processing to the conductive adhesive layer 105 (referring to Fig. 5), led described in removal
Electric adhesive layer 105 exposes 120 first interlayer dielectric layer of external zones, 101 surface.
It is corresponding subsequent when forming polymer layer in 120 substrate 100 of external zones if the conduction adhesive layer 105 is not removed,
The polymeric layer of formation will be located at 105 surface of conductive adhesive layer；In subsequent technical process, it is located at 105 table of conductive adhesive layer
The polymeric layer in face is easy to fall off in other substrates, influences the yield rate of device.Meanwhile in subsequent technical process,
Adhesiveness between conductive adhesive layer 105 and the first interlayer dielectric layer 101 also can gradually die down, therefore the conductive adhesive layer
105 are also easy to fall off in other substrates, influence the yield rate of device.
For this purpose, the present embodiment is after milling process, using the second bevel edge etching processing etching removal conductive attachment
Layer 105, to avoid the possible adverse effect of conductive adhesive layer 105.Also, at the present embodiment the second bevel edge etching
Reason needs to etch layer to be etched more single, the conductive adhesive layer 105 of etching removal, avoids to be etched due to needing to etch
The problem that erosion layer is complex and causes the etching difficulty of the second bevel edge etching processing big.
The second bevel edge etching processing is carried out in bevel edge etching machine, specifically, by bevel etcher it is better-than-average from
Daughter exclusion region (Process Exclusion Zone, referred to as PEZ) ring and lower plasma exclusion zone ring control the
Etching gas is actuated to plasma by radio-frequency power supply by the etching range of two bevel edge etching processings, removal external zones 120
Conductive adhesive layer 105.
In a specific embodiment, the etching gas of the second bevel edge etching processing includes Cl2。
Referring to FIG. 7, in 120 first interlayer dielectric layer 101 of 104 surface of grid conductive layer, device region 110 and external zones
Surface forms the second interlayer dielectric layer 106.
The material of second interlayer dielectric layer 106 is silica, low k dielectric materials or ultra-low k dielectric material, this implementation
Example is using the material of second interlayer dielectric layer 106 as silica as an example, being formed using chemical vapor deposition process described
Second interlayer dielectric layer 106.
Since the present embodiment is before forming the second interlayer dielectric layer 106, the conductive adhesive layer of external zones 120 is eliminated
105 so that the second interlayer dielectric layer 106 of external zones 120 is located at 101 surface of the first interlayer dielectric layer so that it is subsequent
The polymeric layer that external zones 120 is formed is located at 106 surface of 101 surface of the first interlayer dielectric layer or the second interlayer dielectric layer, gathers
The adhesiveness closed between nitride layer material and silica is relatively strong, to can prevent polymeric layer from peeling off to a certain extent
Problem.
If 120 first interlayer dielectric layer of external zones, 101 surface has conductive adhesive layer, subsequent to form contact hole in etching
While can etch the second interlayer dielectric layer 106 of external zones 120 so that the conductive adhesive layer of external zones 120 is exposed,
And then lead to etch the polymeric layer formed during contact hole positioned at conductive attachment layer surface.On the one hand, it will increase subsequent quarter
Technology difficulty of the etching off except polymeric layer and conductive adhesive layer；On the other hand, due between polymeric layer and conductive adhesive layer
Poor adhesion, be easy to cause polymeric layer to peel off from conductive adhesive layer, influence device yield.
Referring to FIG. 8, forming the light with the first opening 107 on 110 second interlayer dielectric layer of device region, 106 surface
Photoresist layer 108.
In the present embodiment, the photoresist layer 108 exposes 120 second interlayer dielectric layer of external zones, 106 surface.
Using the method for wafer edge exposure (WEE, Wafer Edge Exposure), the photoresist layer 108 is formed.
Specifically, the processing step for forming the photoresist layer 108 includes: in 120 second interlayer of the device region 110 and external zones
106 surface of dielectric layer forms initial lithographic glue-line；To the initial lithographic glue-line on 120 second interlayer dielectric layer of external zones, 106 surface
It is exposed processing, while processing is exposed to the initial lithographic glue-line region of the first opening 106 to be formed；It is being exposed
After processing, development treatment is carried out to initial lithographic glue-line, forms the photoresist layer 108.
The initial lithographic glue-line that external zones 120 can be removed using the method for WEE avoids 120 photoresist of external zones from shifting
To 100 back side of substrate, so that subsequent technical process be made to keep cleaning, and the technique essence of the initial lithographic glue-line of external zones is removed
It spends higher.
In other embodiments, institute can also be formed using the method for side glue removal (EBR, Edge Bead Removal)
Photoresist layer 108 is stated, specifically, it is sprayed at external zones 120 using solvent during forming initial lithographic glue-line, it will be outer
Enclose the initial lithographic glue-line removal in area 120.
It in other embodiments, can be comprising steps of in the device region before forming the photoresist layer 108
110 and 106 surface of the second interlayer dielectric layer of external zones 120 form organic distribution layer and positioned at organic distribution layer surface
Bottom antireflective coating；Alternatively, being formed on 106 surface of the second interlayer dielectric layer of the device region 110 and external zones 120 non-
Brilliant carbon-coating and inorganic dielectric bottom antireflective coating positioned at amorphous carbon layer surface；Alternatively, in device region 110 and periphery
Second interlayer dielectric layer, 106 surface in area 120 forms bottom antireflective coating.
Referring to FIG. 9, providing etching cavity, will there is the substrate 100 of the photoresist layer 108 (with reference to Fig. 8) to be placed in quarter
It loses in chamber, the distance between the external zones 120 and etching cavity cavity wall are less than between device region 110 and etching cavity cavity wall
Distance；In the etching cavity, along first opening, 107 etched features area, 110 second interlayer dielectric layer 106 until sudden and violent
Expose 104 surface of grid conductive layer, forms contact hole 118 in 110 second interlayer dielectric layer 106 of device region, and formed
Polymeric layer 109 is formed during contact hole 118 in 120 substrate 100 of external zones.
The contact hole 118 is formed using dry etch process.It is described between etching of second layer while dielectric layer 106
Etching technics can also perform etching photoresist layer 108, the material of the etching gas of etching technics and the second interlayer dielectric layer 106
Occur to chemically react and form byproduct of reaction, while the material of etching gas and photoresist layer 108 occurs chemical reaction and formed instead
Answer by-product.The byproduct of reaction is by warm-up movement and relies on the flowing of etching gas and is discharged out of etching cavity.
However there are the relatively large polymeric impurities of quality in the byproduct of reaction, what the polymeric impurities were subject to
Gravity is larger, and under the effect of gravity, the part polymeric impurities can fall the second interlayer Jie for being attached to device region 110
106 surface of matter layer and 106 surface of the second interlayer dielectric layer of external zones 120.
Since photoresist layer 108 exposes 120 second interlayer dielectric layer of external zones, 106 surface, is formed and connect in etching
While contact hole 118,120 second interlayer dielectric layer 106 of external zones is etched, so that the second interlayer dielectric layer 106 of external zones 120
It is entirely removed or is partially removed.
The present embodiment is etched removal as an example, correspondingly, periphery with the second interlayer dielectric layer 106 of external zones 120
Polymeric layer 109 in 120 substrate 100 of area is located at 101 surface of the first interlayer dielectric layer of external zones 120.
In other embodiments, during forming contact hole 118 120 segment thickness of external zones the second inter-level dielectric
Layer 106 is etched when removing, correspondingly, the polymeric layer 109 in 120 substrate 100 of external zones is located at 120 residue second of external zones
106 surface of interlayer dielectric layer.
In the present embodiment, the distance between external zones 120 and etching cavity cavity wall are less than device region 110 and etch chamber chamber
The temperature of the distance between wall, the cavity wall of the etching cavity is higher than the indoor temperature of etch chamber.The advantages of this arrangement are as follows:
Since in etching process, the temperature of external zones 120 is higher, so that the energy of thermal motion of the polymeric impurities near external zones 120
Power is very strong, to reduce the content of the polymeric impurities fallen in 120 substrate 100 of external zones, reduces the thickness of polymeric layer 109
Degree, so that the difficulty of subsequent first bevel edge etching processing reduces.
As an example, the temperature of the cavity wall of the etching cavity be 80 degrees Celsius to 200 degrees Celsius, for example, 100
Degree Celsius, 130 degrees Celsius, 150 degrees Celsius or 180 degrees Celsius；The indoor temperature of etch chamber is 20 degrees Celsius to 80 Celsius
Degree, for example, 30 degrees Celsius, 50 degrees Celsius or 70 degrees Celsius.
During forming contact hole 118, in the contact hole 118 of device region 110 and the second interlayer dielectric layer 106
Surface can also be attached with polymeric impurities, and rear extended meeting starts the cleaning processing the contact hole 118 of device region 110, removal devices area
110 polymeric impurities.
After forming the contact hole 118, photoresist layer 108 is removed.
Referring to FIG. 10, carrying out the first bevel edge etching processing to the polymeric layer 109 (referring to Fig. 9), remove described poly-
Close nitride layer 109.
During subsequent technique, it is easy to peel off from substrate 100 positioned at the polymeric layer 109 of external zones 120；And it is subsequent
In the technique for forming conductive plunger, although grinding technics can be undergone, still having segment thickness conductive plunger can also be located at
In 120 substrate 100 of external zones, if the conductive plunger of the segment thickness is in contact with polymeric layer 109, due to polymeric layer
109 is weak with the adhesiveness of segment thickness conductive plunger, and during subsequent technique, the segment thickness conductive plunger of external zones is easy
It is peeled off from polymeric layer 109, influences the production yield of device.
And subsequent wet clean process is easier to the polymeric impurities in removal devices area 110, removes the polymerization of external zones 120
The difficulty of nitride layer 109 is larger.
For this purpose, the present embodiment removes the polymeric layer 109 using the first bevel edge etching processing, carved in first bevel edge
After erosion processing, 120 substrate of external zones, 100 surface is not exposed.
In one embodiment, after carrying out the first bevel edge etching processing, 120 substrate of external zones, 100 surface
It is covered by the first interlayer dielectric layer 101.Alternatively, after carrying out the first bevel edge etching processing, 120 substrate of external zones
100 surfaces are covered by the second interlayer dielectric layer 106 of the first interlayer dielectric layer 101 and segment thickness.
So that subsequent in the technical process for forming conductive plunger, 120 substrate of external zones, 100 surface is by the first inter-level dielectric
101 covering of layer or 120 substrate of external zones, 100 surface are situated between by the second interlayer of the first interlayer dielectric layer 101 and segment thickness
Matter layer 106 covers, therefore subsequent after undergoing grinding technics, is located in the segment thickness conductive plunger that external zones 120 is formed
106 surface of first interlayer dielectric layer, 101 surface or the second interlayer dielectric layer, so that the conductive plunger of 120 segment thickness of external zones
Adhesiveness between substrate 100 is strong, to prevent the conductive plunger of 120 segment thickness of external zones from peeling off.
If the segment thickness conductive plunger that subsequent external zones 120 is formed directly is contacted with substrate 100, segment thickness conduction is inserted
Adhesiveness between plug and substrate 100 is very weak, therefore 120 segment thickness conductive plunger of external zones will be easy to peel off.
The first bevel edge etching processing is greater than to the first interlayer dielectric layer 101 etch rate of polymeric layer 109
Etch rate.The first bevel edge etching processing is carried out in bevel edge etching machine；The etching gas of the first bevel edge etching processing
Body is fluoro-gas.
As a specific embodiment, the fluoro-gas is CF4、CHF3、NF3Or SF6.In the present embodiment, described first
The technological parameter of bevel edge etching processing are as follows: etching gas includes CH4And SF6, CO is also passed through into etching cavity2And N2, CF4Flow
For 10sccm to 500sccm, SF6Flow is 10sccm to 100sccm, CO2Flow is 10sccm to 100sccm, N2Flow is
100sccm to 500sccm, providing source power is 200 watts to 1000 watts.
First bevel edge etching processing described in the present embodiment is multiple tracks etching technics, to guarantee the first bevel edge etching processing
Afterwards, 120 substrate of external zones, 100 surface is not exposed.In other embodiments, the first bevel edge etching processing may be one
Road etching technics, and the first bevel edge etching technics selects polymeric layer 109 with to the first interlayer dielectric layer 101 with larger etching
Select ratio.
Then, wet clean process is carried out to the contact hole 118；Then Ar plasma is carried out to the contact hole 118
Body bombardment processing.
The wet clean process can remove the polymeric impurities in contact hole 118.The wet clean process it is clear
Wash liq is hydrofluoric acid solution or hydrogen peroxide solution.
The Ar plasma bombardment can repair the interface performance in contact hole 118, mention to be subsequently formed conductive plunger
For good interface basis.
Figure 11 is please referred to, in 110 second interlayer dielectric layer of device region, 106 top surface, 120 substrate 100 of external zones
The upper and described 118 bottom and side wall surface of contact hole forms electrically conductive barrier 201, and formation is covered in 201 table of electrically conductive barrier
Face and the conductor layer 202 for filling full contact hole 118 (referring to Figure 10), and it is higher than device region 110 at the top of the conductor layer 202
Second interlayer dielectric layer, 106 top surface.
The material of the electrically conductive barrier 201 is Ti, TiN, Ta, TaN, WN, Cu, Al or W；The conductor layer 202
Material is Ti, TiN, Ta, TaN, WN, Cu, Al or W.
In the present embodiment, electrically conductive barrier 201 is different from the material of conductor layer 202, and the material of electrically conductive barrier 201 is
Ti, TiN, Ta, TaN or WN, the material of conductor layer 202 are Cu, Al or W, and the conductive plunger being accordingly subsequently formed is lamination knot
Structure.In other embodiments, the material of electrically conductive barrier 201 and conductor layer 202 can also be identical, and what is be accordingly subsequently formed leads
Electric plug is single layer structure.
In one embodiment, it is described when 120 substrate of external zones, 100 surface is covered by the first interlayer dielectric layer 101
Electrically conductive barrier 201 in external zones substrate 100 is located at 120 first interlayer dielectric layer of external zones, 101 surface.
In another embodiment, 120 substrate of external zones, 100 surface is thick by the first interlayer dielectric layer 101 and part
When the second interlayer dielectric layer 106 covering of degree, the electrically conductive barrier 201 in 120 substrate 100 of external zones is located at external zones
120 second interlayer dielectric layer, 106 surface.
Figure 12 is please referred to, grinding removal is higher than the conductor layer of 110 second interlayer dielectric layer of device region, 106 top surface
201 and electrically conductive barrier 202, form the conductive plunger of the full contact hole 118 (referring to Figure 10) of filling.
Specifically, removal is higher than 110 second interlayer dielectric layer of device region, 106 top table using CMP process
The conductor layer 202 and electrically conductive barrier 201 in face form the conductive plunger for filling the full contact hole.The conductive plunger
Include: positioned at 118 bottom and side wall surface of contact hole electrically conductive barrier 201 and positioned at 201 surface of electrically conductive barrier and fill out
Conductor layer 202 full of contact hole 118.
The present embodiment is by taking the conductive plunger is laminated construction as an example, the material of electrically conductive barrier 201 and conductor layer 202
It is different.In other embodiments, conductive plunger may be single layer structure, the material of electrically conductive barrier 201 and conductor layer 202
It is identical.
During the grinding process, the grinding rate of device region 110 is greater than the grinding rate of external zones 120；And due to being formed
After contact hole 118,120 second interlayer dielectric layer 106 of external zones is entirely removed or is partially removed, and is forming conductive barrier
Before layer 201, the overhead height of external zones 120 is less than the overhead height of device region 110.
As the above analysis, after milling, the electric conductor of 110 second interlayer dielectric layer of device region, 106 top surface
Layer 202 and electrically conductive barrier 201 be removed, and in 120 substrate 100 of external zones still have electrically conductive barrier 201 and
The conductor layer 202 of segment thickness.
In one embodiment, when 120 substrate of external zones, 100 surface is covered by the first interlayer dielectric layer 101, in institute
After stating grinding, 120 first interlayer dielectric layer of external zones, 101 surface is led by electrically conductive barrier 201 and segment thickness
Electrics layer 202 covers.
In another embodiment, 120 substrate of external zones, 100 surface is thick by the first interlayer dielectric layer 101 and part
When the second interlayer dielectric layer 106 covering of degree, after the grinding, 120 second interlayer dielectric layer of external zones, 106 surface
It is covered by the conductor layer 202 of electrically conductive barrier 201 and segment thickness.
Since the present embodiment is after the first bevel edge etching processing, 120 substrate of external zones, 100 surface is not exposed,
Correspondingly, 120 electrically conductive barrier 201 of external zones does not contact directly with 110 substrate surface of external zones, outside after the grinding
It encloses 120 electrically conductive barrier 201 of area to be in contact with the first interlayer dielectric layer 101 or the second interlayer dielectric layer 106, so that external zones
Adhesiveness between 120 electrically conductive barriers 201 and substrate 100 is good, prevents 120 electrically conductive barrier 201 of external zones and electric conductor
Layer 202 is peeled off from substrate 100, and the electrically conductive barrier 201 and conductor layer 202 for preventing external zones 120 from falling are fallen at it
In his substrate, device production yield is improved.
If 120 electrically conductive barrier 201 of external zones is directly contacted with 100 surface of substrate, due to the material of electrically conductive barrier 201
For Ti, TiN, Ta, TaN, WN, Cu, Al or W, and the material of substrate 100 is silicon, between electrically conductive barrier 201 and substrate 100
Poor adhesion, during subsequent technique, the electrically conductive barrier 201 and conductor layer 202 of external zones 120 are easy from substrate
It is peeled off on 100, falls in other substrates and other substrates are caused to damage or be polluted.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate and the first interlayer dielectric layer positioned at substrate surface are provided, the substrate includes device region and the encirclement device
The external zones in part area, is formed with grid conductive layer in the first interlayer dielectric layer of the device region, with the at the top of the grid conductive layer
It is flushed at the top of one interlayer dielectric layer；
The second interlayer dielectric layer is formed in the grid conductive layer surface, device region and external zones the first interlayer dielectric layer surface；
The photoresist layer with the first opening is formed in device region the second interlayer dielectric layer surface；
Etching cavity is provided, the substrate with the photoresist layer is placed in etching cavity, the external zones and etching cavity
The distance between cavity wall is less than the distance between device region and etching cavity cavity wall；
In the etching cavity, along first opening second interlayer dielectric layer of etched features area until exposing grid conductive layer
Surface, forms contact hole in second interlayer dielectric layer of device region, and the temperature of the cavity wall of the etching cavity is higher than etching
The indoor temperature of chamber, and polymeric layer is formed in the external zones substrate during forming contact hole；
Remove the photoresist layer；
First bevel edge etching processing is carried out to the polymeric layer, removes the polymeric layer；
Form the conductive plunger for filling the full contact hole.
2. the forming method of semiconductor structure according to claim 1, which is characterized in that form the work of the grid conductive layer
Skill step includes: that the second opening is formed in first interlayer dielectric layer of device region；Form full second opening of filling
Gate-conductive film, and the gate-conductive film is also covered in the first interlayer dielectric layer surface；Grinding removal is higher than the first interlayer dielectric layer
The gate-conductive film on surface forms grid conductive layer in second opening, and after milling, in the first inter-level dielectric of external zones
Layer surface forms conductive adhesive layer, and the material of the conduction adhesive layer is identical as grid conductive layer material.
3. the forming method of semiconductor structure according to claim 2, which is characterized in that formed the grid conductive layer it
Afterwards, it is formed before second interlayer dielectric layer, further comprises the steps of: and the conductive adhesive layer is carried out at the second bevel edge etching
Reason removes the conductive adhesive layer.
4. the forming method of semiconductor structure according to claim 1, which is characterized in that the cavity wall of the etching cavity
Temperature is 80 degrees Celsius to 200 degrees Celsius；The indoor temperature of etch chamber is 20 degrees Celsius to 80 degrees Celsius.
5. the forming method of semiconductor structure according to claim 1, which is characterized in that carry out institute in bevel edge etching machine
State the first bevel edge etching processing；The etching gas of the first bevel edge etching processing is fluoro-gas, wherein fluoro-gas includes
CF4、CHF3、NF3Or SF6。
6. the forming method of semiconductor structure according to claim 1, which is characterized in that the first bevel edge etching processing
Technological parameter are as follows: etching gas includes CH4And SF6, CO is also passed through into etching cavity2And N2, CF4Flow be 10sccm extremely
500sccm, SF6Flow is 10sccm to 100sccm, CO2Flow is 10sccm to 100sccm, N2Flow be 100sccm extremely
500sccm, providing source power is 200 watts to 1000 watts.
7. the forming method of semiconductor structure according to claim 1, which is characterized in that at the first bevel edge etching
After reason, the external zones substrate surface is not exposed.
8. the forming method of semiconductor structure according to claim 7, which is characterized in that carved carrying out first bevel edge
After erosion processing, the external zones substrate surface is covered by the first interlayer dielectric layer；Alternatively, carrying out at the first bevel edge etching
After reason, the external zones substrate surface is covered by the second interlayer dielectric layer of the first interlayer dielectric layer and segment thickness.
9. the forming method of semiconductor structure according to claim 7, which is characterized in that form the work of the conductive plunger
Skill step includes: in the second interlayer dielectric layer of device region top surface, external zones substrate and the contact hole bottom
Electrically conductive barrier is formed with sidewall surfaces, forms the conductor layer for being covered in conductive barrier layer surface and filling full contact hole, and
It is higher than the second interlayer dielectric layer of device region top surface at the top of the conductor layer；Grinding removal is higher than the second interlayer of device region and is situated between
The conductor layer and electrically conductive barrier of matter layer top surface form the conductive plunger for filling full contact hole.
10. the forming method of semiconductor structure according to claim 9, which is characterized in that the external zones substrate surface
When being covered by the first interlayer dielectric layer, after the grinding, the first interlayer of external zones dielectric layer surface is by conductive barrier
The covering of the conductor layer of layer and segment thickness.
11. the forming method of semiconductor structure according to claim 9, which is characterized in that the external zones substrate surface
When being covered by the second interlayer dielectric layer of the first interlayer dielectric layer and segment thickness, after the grinding, the external zones
Second interlayer dielectric layer surface is covered by the conductor layer of electrically conductive barrier and segment thickness.
12. the forming method of semiconductor structure according to claim 7, which is characterized in that at the first bevel edge etching
Reason is multiple tracks etching technics, and after guaranteeing the first bevel edge etching processing, external zones substrate surface is not exposed.
13. the forming method of semiconductor structure according to claim 9, which is characterized in that the material of the electrically conductive barrier
Material is Ti, TiN, Ta, TaN, WN, Cu, Al or W；The material of the conductor layer is Ti, TiN, Ta, TaN, WN, Cu, Al or W.
14. the forming method of semiconductor structure according to claim 1, which is characterized in that etching the device region the
While two interlayer dielectric layers form the contact hole, the second interlayer dielectric layer of external zones is etched.
15. the forming method of semiconductor structure according to claim 14, which is characterized in that forming the contact hole
Meanwhile the second interlayer dielectric layer of external zones is etched removal, the polymeric layer is located at external zones the first interlayer dielectric layer surface；
Alternatively, while forming the contact hole, the second interlayer dielectric layer of external zones segment thickness is etched removal, the polymerization
Nitride layer is located at the remaining second interlayer dielectric layer surface of external zones.
16. the forming method of semiconductor structure according to claim 1, which is characterized in that forming the conductive plunger
Before, it further comprises the steps of: and wet clean process is carried out to the contact hole；After the wet clean process, connect to described
Contact hole carries out the processing of Ar plasma bombardment.
17. the forming method of semiconductor structure according to claim 1, which is characterized in that the photoresist layer exposes
External zones the second interlayer dielectric layer surface；Using the method for wafer edge exposure, the photoresist layer is formed.
18. the forming method of semiconductor structure according to claim 17, which is characterized in that form the photoresist layer
Processing step includes: to form initial lithographic glue-line in the device region and external zones the second interlayer dielectric layer surface；To periphery
The initial lithographic glue-line of area's the second interlayer dielectric layer surface is exposed processing, while to the initial lithographic of the first opening to be formed
Glue-line region is exposed processing；After being exposed processing, development treatment is carried out to initial lithographic glue-line, forms the light
Photoresist layer.
19. the forming method of semiconductor structure according to claim 1, which is characterized in that first interlayer dielectric layer
Material be silica, low k dielectric materials or ultra-low k dielectric material；The material of second interlayer dielectric layer is silica, low
K dielectric material or ultra-low k dielectric material.
20. the forming method of semiconductor structure according to claim 1, which is characterized in that the material of the grid conductive layer
Including Ti, TiN, Ta, TaN, WN, Cu, Al or W；Gate dielectric layer is also formed between the device region substrate and grid conductive layer.
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| EP1055463A2 (en) * | 1999-05-19 | 2000-11-29 | Ebara Corporation | Wafer cleaning apparatus |
| US6607983B1 (en) * | 1999-11-05 | 2003-08-19 | Samsung Electronics Co., Ltd. | Method of processing a defect source at a wafer edge region in a semiconductor manufacturing |
| CN101271831A (en) * | 2007-03-23 | 2008-09-24 | 海力士半导体有限公司 | Method for fabricating semiconductor device |
| CN104091772A (en) * | 2014-07-11 | 2014-10-08 | 上海华力微电子有限公司 | Wafer edge amorphous carbon thin film removing device and method |
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| DE102005035728B3 (en) * | 2005-07-29 | 2007-03-08 | Advanced Micro Devices, Inc., Sunnyvale | A method of reducing contamination by removing an interlayer dielectric from the substrate edge |
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|---|---|---|---|---|
| EP1055463A2 (en) * | 1999-05-19 | 2000-11-29 | Ebara Corporation | Wafer cleaning apparatus |
| US6607983B1 (en) * | 1999-11-05 | 2003-08-19 | Samsung Electronics Co., Ltd. | Method of processing a defect source at a wafer edge region in a semiconductor manufacturing |
| CN101271831A (en) * | 2007-03-23 | 2008-09-24 | 海力士半导体有限公司 | Method for fabricating semiconductor device |
| CN104091772A (en) * | 2014-07-11 | 2014-10-08 | 上海华力微电子有限公司 | Wafer edge amorphous carbon thin film removing device and method |
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