CN105741802B

CN105741802B - Shift register cell and its driving method, gate driving circuit, display device

Info

Publication number: CN105741802B
Application number: CN201610184185.5A
Authority: CN
Inventors: 马占洁
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2016-03-28
Filing date: 2016-03-28
Publication date: 2018-01-30
Anticipated expiration: 2036-03-28
Also published as: CN105741802A; US20170278450A1; US10002558B2

Abstract

The present invention provides a kind of shift register cell and its driving method, gate driving circuit, display device, is related to display technology field, and GOA circuits can be adjusted per the pulsewidth of one-level output end signal.The shift register cell includes input module, the first pull-up control module, the second pull-up control module, drop-down control module, pull-up module, drop-down module and energy-storage module.Signal output to first node, the energy-storage module that input module inputs a signal into end is stored to the voltage of first node, or storage voltage is provided to first node.First pull-up control module is under the control of first node, the first clock signal terminal and second clock signal end, by the voltage output at first voltage end to pulling up control node；Second pull-up control module is under the control of first node, by the voltage output at second voltage end to pulling up control node；Pull down control module under the control of second clock signal end by the voltage output of first node to pulling down control node.

Description

Shift register cell and its driving method, gate driving circuit, display device

Technical field

The present invention relates to display technology field, more particularly to a kind of shift register cell and its driving method, grid to drive Dynamic circuit, display device.

Background technology

(Thin Film Transistor Liquid Crystal Display, TFT-LCD show TFT-LCD Show device) and OLED (Active Matrix Driving OLED, active matrix-driven organic light-emitting diode) display device Because it has the characteristics that small volume, low in energy consumption, radiationless and cost of manufacture are relatively low, and height is applied to more and more Among performance display field.

Above-mentioned display device is usually provided with GOA (Gate Driver on Array, the driving of array base palte row) circuit, should GOA circuits are connected per one-level output end with a line grid line, for exporting gated sweep signal to the grid line, to realize to grid line Progressive scan.However, the pulsewidth of GOA circuit outputs end signal is fixed value in the prior art, so that user can not root According to needing that the pulsewidth of above-mentioned signal is adjusted.

The content of the invention

Embodiments of the invention provide a kind of shift register cell and its driving method, gate driving circuit, display dress Put, GOA circuits can be adjusted per the pulsewidth of one-level output end signal.

To reach above-mentioned purpose, embodiments of the invention adopt the following technical scheme that：

The one side of the embodiment of the present invention, there is provided a kind of shift register cell, including including input module, the first pull-up Control module, the second pull-up control module, drop-down control module, pull-up module, drop-down module and energy-storage module.

Wherein, the input module connects the first clock signal terminal, signal input part and the first node respectively, uses By the voltage output of the signal input part to the first node under the control in first clock signal terminal.Described One pull-up control module connect respectively first voltage end, the first clock signal terminal, second clock signal end, the first node with And pull-up control node, in first clock signal terminal, the second clock signal end and the first node By the voltage output at the first voltage end to the pull-up control node under control.The second pull-up control module connects respectively Connect second voltage end, the pull-up control node and first node, under the control of the first node by institute The voltage output at second voltage end is stated to the pull-up control node.The drop-down control module connects the second clock respectively Signal end, the first node and drop-down control node, under the control of the second clock signal end by described the The voltage output of one node is to the drop-down control node.The pull-up module connects the pull-up control node, described respectively Second voltage end and signal output part, under the control of the pull-up control node by the voltage at the second voltage end Export to the signal output part.It is described drop-down module connect respectively it is described drop-down control node, the first voltage end and The signal output part, under the control of the drop-down control node by the voltage output at the first voltage end to described Signal output part.The energy-storage module is connected between the first node and the signal output part, for by described first The voltage of node is stored, or the first node is charged.

Further, the first pull-up control module includes the first transistor, second transistor, third transistor, the Four transistors and the first electric capacity.Wherein, the grid of the first transistor connects first clock signal terminal, and the first pole connects The first voltage end is connect, the second pole is connected with the grid of the second transistor.The pole of second transistor first connects institute First voltage end is stated, the second pole connects the first pole of the third transistor.The grid connection described the of the third transistor Two clock signal terminals, the second pole connect the pull-up control node.The grid of 4th transistor connects the first node, First pole connects the grid of the second transistor, and the second pole connects first clock signal terminal.The one of first electric capacity End connects the grid of the second transistor, and the other end is connected with the grid of the third transistor.

Further, the input module includes the 5th transistor, the grid connection described first of the 5th transistor Clock signal terminal, the first pole connect the signal input part, and the second pole connects the first node.

Further, the second pull-up control module includes the 6th transistor, the grid connection of the 6th transistor The first node, the first pole connect the second voltage end, and the second pole connects the pull-up control node.

Further, the drop-down control module includes the 7th transistor；Described in the grid connection of 7th transistor Second clock signal end, the first pole connect the first node, and the second pole connects the drop-down control node.

Further, the pull-up module includes the 8th transistor and the 3rd electric capacity.Wherein, the grid of the 8th transistor Pole connects the pull-up control node, and the first pole connects the second voltage end, and the second pole connects the signal output part.It is described One end of 3rd electric capacity connects the second voltage end, and the other end is connected with the grid of the 8th transistor.

Further, the drop-down module includes the 9th transistor and the 4th electric capacity.Wherein, the grid of the 9th transistor Pole connects the drop-down control node, and the first pole connects the first voltage end, and the second pole connects the signal output part；4th One end of electric capacity is connected with the grid of the 9th transistor, and the other end connects the second pole of the 9th transistor.

Further, the energy-storage module includes the second electric capacity, and one end of second electric capacity connects the first node, The other end is connected with the signal output part.

The opposing party of the present invention provides a kind of gate driving circuit, and the gate driving circuit includes at least two-stage cascade Any one above-mentioned shift register cell, wherein, the signal input part and initial signal of first order shift register cell End is connected, in addition to the first order shift register cell, the signal output part of upper level shift register cell with The signal input part of next stage shift register cell is connected.

Another aspect of the present invention provides a kind of display device, including above-mentioned gate driving circuit.

Another aspect of the invention provides a kind of driving method of above-mentioned shift register cell, in a picture frame, institute The method of stating includes：

First stage specifically performs following operation：Under the control of first clock signal terminal, input module is by signal The voltage output of input is to first node；The energy-storage module is stored the voltage of the first node simultaneously；First Pull-up control module is stored the voltage at first voltage end；Under the control of the first node, the second pull-up control mould Block is by the voltage output at second voltage end to the pull-up control node；Wherein, first pull-up control module, pull-up module, under Draw control module, drop-down module and the output of signal output part no signal；

Second stage specifically performs following operation：Under the control of the second clock signal end, the drop-down control mould Block by the voltage output that the energy-storage module stores in the first stage to pulling down control node, and in the drop-down control section Under the control of point, the drop-down module is by the voltage output at the first voltage end to signal output part, while by the drop-down The voltage of control node is stored；Wherein, the input module, the first pull-up control module, the second pull-up control Molding block, the pull-up module no signal output；

Phase III specifically performs following operation：Under the control of first clock signal terminal, the input module will The voltage output of the signal input part to the first node, the energy-storage module is deposited the voltage of the first node Storage；The first pull-up control module is stored the voltage of first clock signal terminal；It is described drop-down module by The voltage of the second stage storage is kept it turned on, and the voltage output at the second voltage end is defeated to the signal Go out end；Wherein, the first pull-up control module, the second pull-up control module, the pull-up module, the drop-down control module No signal exports；

Fourth stage specifically performs following operation：The first pull-up control module is in first clock signal terminal, institute Under the control for stating second clock signal end and the first node, by the voltage that is stored in the phase III by described The voltage output of one voltage end is to the pull-up control node so that the pull-up module by the voltage output of the second terminal voltage extremely The signal output part, and the voltage of the pull-up control node is stored；The energy-storage module is by the phase III The voltage output of storage is to the first node；The drop-down control module is by the voltage output of the first node under described Control node is drawn, and the voltage of the drop-down control node is stored；Wherein, the input module, second pull-up Control module, the drop-down module no signal output；

It is repeated in the signal input part, the first clock signal terminal and second clock signal of phase III and fourth stage The control signal at end so that signal output part keeps the voltage at output second voltage end；

5th stage specifically performed following operation：Under the control of first clock signal terminal, the input module will The voltage output of the signal input part is to the first node；The energy-storage module enters the voltage of the first node simultaneously Row storage；The first pull-up control module is stored the voltage of first clock signal terminal；In the first node Control under, the second pull-up control module is by the voltage output at second voltage end to the pull-up control node；On line In the presence of electric capacity, the signal output part keeps the voltage at output second voltage end；Wherein, the first pull-up control mould Block, the pull-up module, the drop-down module no signal output；

6th stage specifically performed following operation：Under the control of the second clock signal end, the drop-down control mould Block by the voltage output that the energy-storage module stores in the first stage to pulling down control node, and in the drop-down control section Under the control of point, the drop-down module is by the voltage output at the first voltage end to signal output part, while by the drop-down The voltage of control node is stored；Wherein, the input module, the first pull-up control module, the second pull-up control Molding block, the pull-up module no signal output；

Repeated before next image frame the signal input part in the 5th stage and the 6th stage, the first clock signal terminal and The control signal of second clock signal end so that signal output part keeps the voltage at output first voltage end.

The embodiment of the present invention provides a kind of shift register cell and its driving method, gate driving circuit, display device, Wherein, the shift register cell includes the first pull-up control module, input module, the second pull-up control module, drop-down control Molding block, pull-up module, drop-down module and energy-storage module.Specifically, the first pull-up control module connects first voltage respectively End, the first clock signal terminal, second clock signal end and pull-up control node, in the first clock signal terminal and second By the voltage output at first voltage end to pulling up control node under the control of clock signal end.Input module connects the first clock letter respectively Number end, signal input part and first node, the voltage for inputting a signal into end under the control of the first clock signal terminal it is defeated Go out to first node.Second pull-up control module connects second voltage end, pull-up control node and first node respectively, is used for By the voltage output at second voltage end to pulling up control node under the control of first node.Drop-down control module connects the respectively Two clock signal terminals, first node and drop-down control node, under the control of second clock signal end by first node Voltage output to pulling down control node.Pull-up module connects pull-up control node, second voltage end and signal output respectively End, under the control of pull-up control node by the voltage output at second voltage end to signal output part.Pull down module difference Connection drop-down control node, first voltage end and signal output part, for electric by first under the control of drop-down control node The voltage output of pressure side is to signal output part.Energy-storage module is connected between first node and signal output part, for by first The voltage of node is stored, or first node is charged.

So, input module can input a signal into the signal output at end to first node, and energy-storage module can The voltage of first node is stored, or storage voltage is provided to first node.In the case, the first pull-up control Module can be under the control of first node, the first clock signal terminal and second clock signal end, by the voltage at first voltage end Output extremely pull-up control node；Second pull-up control module can be under the control of first node, by the voltage at second voltage end Output extremely pull-up control node；Pulling down control module can be defeated by the voltage of first node under the control of second clock signal end Go out to drop-down control node.Based on this, it is defeated to signal that pull-up control node can control pull-up module to export second voltage end Go out end, and pulling down control node can control drop-down module to export at first voltage end to signal output part, and first voltage end The pulsewidth of signal output part output signal is enough determined with the voltage and can at second voltage end.

In summary, input module and energy-storage module can determine the current potential of first node, and be connected with first node First pull-up control module and second pull-up control module can control pull-up control node current potential, be connected with first node The drop-down module connect can control the current potential of drop-down control node, and pull-up control node and drop-down control node and can enough control arteries and veins It is wide.So, input module, first pull-up control module, second pull-up control module, drop-down control module, on drawing-die Under block, drop-down module, the collective effect of energy-storage module, the pulsewidth of signal output part output signal can be adjusted, so that The pulsewidth for obtaining the pulsewidth of signal output part output signal and the input signal of signal input part matches.So as to by letter The pulsewidth of number input end signal is adjusted, and every one-level shift register cell signal output end signal pulsewidth is carried out with reaching The purpose of regulation.

Brief description of the drawings

In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with Other accompanying drawings are obtained according to these accompanying drawings.

Fig. 1 is a kind of structural representation of shift register cell provided in an embodiment of the present invention；

Fig. 2 is the concrete structure schematic diagram of the shift register cell shown in Fig. 1；

Fig. 3 is the control signal timing diagram of the shift register cell shown in Fig. 1 or Fig. 2；

Fig. 4 is a kind of structural representation of gate driving circuit provided in an embodiment of the present invention.

Reference：

101- input modules；102- first pulls up control module；103- second pulls up control module；104- drop-down control moulds Block；105- pulls up module；106- pulls down module；107- energy-storage modules；M1- the first transistors；M2- second transistors；M3- the 3rd Transistor；The transistors of M4- the 4th；The transistors of M5- the 5th；The transistors of M6- the 6th；The transistors of M7- the 7th；The transistors of M8- the 8th； The transistors of M9- the 9th；PU- pulls up control node；PD- pulls down control node；NET1- first nodes；The clock signals of CLK1- first End；CLK2- second clock signal ends；IN- signal input parts；OUTPUT- signal output parts；VGL- first voltages end；VGH- Two voltage ends；The moment of T1- first.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made Embodiment, belong to the scope of protection of the invention.

The embodiment of the present invention provides a kind of shift register cell, including as shown in Figure 1, on input module 101, first Draw control module 102, second pull up control module 103, drop-down control module 104, pull-up module 105, drop-down module 106 and Energy-storage module 107.

Specifically, input module 101 connects the first clock signal terminal CLK1, signal input part IN and first node respectively NET1, for inputting a signal into end IN voltage output under the first clock signal terminal CLK1 control to first node NET1.

First pull-up control module 102 connects first voltage end VGL, the first clock signal terminal CLK1, second clock respectively Signal end CLK2, first node NET1 and pull-up control node PU, in the first clock signal terminal CLK1, second clock letter By first voltage end VGL voltage output to pulling up control node PU under number end CLK2 and first node NET1 control.

Second pull-up control module 103 connects second voltage end VGH, pull-up control node PU and first node respectively NET1, for second voltage end VGH voltage output extremely to be pulled up into control node PU under first node NET1 control.

Drop-down control module 104 connects second clock signal end CLK2, first node NET1 and drop-down control section respectively Point PD, under second clock signal end CLK2 control by first node NET1 voltage output to pulling down control node PD。

Pull-up module 105 connects pull-up control node PU, second voltage end VGH and signal output part OUTPUT respectively, For under pull-up control node PU control by second voltage end VGH voltage output to signal output part OUTPUT.

Drop-down module 106 connects drop-down control node PD, first voltage end VGL and signal output part OUTPUT respectively, For under drop-down control node PD control by first voltage end VGL voltage output to signal output part OUTPUT.

Energy-storage module 107 is connected between first node NET1 and signal output part OUTPUT, for by first node NET1 voltage is stored, or first node NET1 is charged.

Above as can be seen that input module 101 can input a signal into end IN signal output to first node NET1, and Energy-storage module 107 can be stored to first node NET1 voltage, or storage voltage is provided to first node NET1. In the case, the first pull-up control module 102 can be in first node NET1, the first clock signal terminal CLK1 and second clock Under signal end CLK2 control, by first voltage end VGL voltage output to pull-up control node PU；Second pull-up control module 103 can be under first node NET control, by second voltage end VGH voltage output to pull-up control node PU；Drop-down control Molding block 104 can save first node NET1 voltage output to control is pulled down under second clock signal end CLK2 control Point PD.Based on this, pull-up control node PU can control pull-up module 105 to export second voltage end VGH to signal output part OUTPUT, and pulling down control node PD can control drop-down module 106 to export first voltage end VGL to signal output part OUTPUT, and first voltage end VGL and second voltage end VGH voltage and can enough determine signal output part OUTPUT output signals Pulsewidth.

In summary, input module 101 and energy-storage module 107 can determine first node NET1 current potential, and with first The first pull-up control module 102 and second that node NET1 is connected, which pulls up control module 103, can control pull-up control node PU current potential, the drop-down module 106 being connected with first node NET1 can control drop-down control node PD current potential, pull-up control Node PU processed and drop-down control node PD and cans enough control OUTPUT pulsewidth.So, on input module 101, first Control module 102, second is drawn to pull up control module 103, drop-down control module 105, pull-up module 105, drop-down module 106, storage Under the collective effect of energy module 107, the pulsewidth of signal output part OUTPUT output signals can be adjusted, to cause signal The pulsewidth of the pulsewidth and signal input part IN input signal of output end OUTPUT output signals matches.So as to by right The pulsewidth of signal input part IN signals is adjusted, and every one-level shift register cell signal output part OUTPUT is believed with reaching Feel the pulse the wide purpose being adjusted.

Herein it should be noted that the present invention is for the pulsewidth by adjusting signal input part IN signals, to reach to every The concrete application that one-level shift register cell signal output part OUTPUT signal pulsewidths are adjusted does not limit.

For example, when the GOA circuits that above-mentioned shift register cell is formed are applied to OLED display, by above-mentioned displacement , can be by the grid when gate driving circuit that register cell cascade is formed progressively scans to the grid line of display The signal input part IN output signal pulses width adjustments of drive circuit, effective luminosity of light emitting diode is entered with realizing Row controls line by line, so as to reach the purpose that whole screen brightness is adjusted.

In another example when the GOA circuits that above-mentioned shift register cell is formed are applied to TFT-LCD, if TFT-LCD shows Show that the size of panel is larger, can be by increasing the pulsewidths of signal input part IN signals, to cause each grade of shift register list The pulsewidth of first signal output part OUTPUT signals also accordingly increases, so as to avoid the pixel list apart from the GOA circuits farther out There is the phenomenon of undercharge because the pulsewidth of signal output part OUTPUT signals is narrower in member.

As shown in Fig. 2 below by way of specific embodiment to the tool of each submodule in above-mentioned shift register cell Body structure carries out detailed illustration.

Above-mentioned first pull-up control module 102 includes the first transistor M1, second transistor M2, third transistor M3, the Four transistor M4 and the first electric capacity C1.

Wherein, the first transistor M1 grid connects the first clock signal terminal CLK1, the first pole connection first voltage end VGL, the second pole are connected with second transistor M2 grid.

The poles of second transistor M2 first connect first voltage end VGL, the second pole connection third transistor M3 the first pole.

Third transistor M3 grid connection second clock signal end CLK2, the second pole connection pull-up control node PU.

4th transistor M4 grids connect first node NET1, the first pole connection second transistor M2 grid, the second pole Connect the first clock signal terminal CLK1.

First electric capacity C1 one end connection second transistor M2 grid, the other end are connected with third transistor M3 grid Connect.

Above-mentioned input module 101 includes the 5th transistor M5, and the 5th transistor M5 grid connects the first clock signal Hold CLK1, the first pole connection signal input part IN, the second pole connection first node NET1.

Above-mentioned second pull-up control module 103 includes the 6th transistor M6, the 6th transistor M6 grid connection first Node NET1, the first pole connection second voltage end VGH, the second pole connection pull-up control node PU.

Above-mentioned drop-down control module 104 includes the 7th transistor M7, the 7th transistor M7 grid connection second clock Signal end CLK2, the first pole connection first node NET, the second pole connection drop-down control node PD.

Above-mentioned pull-up module 105 includes the 8th transistor M8 and the 3rd electric capacity C3.

Wherein, the 8th transistor M8 grid connection pull-up control node PU, the first pole connection second voltage end VGH, the Two poles connection signal output part OUTPUT.

3rd electric capacity C3 one end connection second voltage end VGH, the other end are connected with the 8th transistor M8 grid.

Above-mentioned drop-down module 106 includes the 9th transistor M9 and the 4th electric capacity C4.

Wherein, the 9th transistor M9 grid connection drop-down control node PD, the first pole connection first voltage end VGL, the Two poles connection signal output part OUTPUT.

4th electric capacity C4 one end is connected with the 9th transistor M9 grid, and the other end connects the second of the 9th transistor Pole.

Above-mentioned energy-storage module 107 includes the second electric capacity C2, second electric capacity C2 one end connection first node NET1, another End is connected with signal output part OUTPUT.

The on off operating mode of each transistor in shift register cell as shown in Figure 2 is carried out below in conjunction with Fig. 3 detailed Explanation.It is with first voltage end VGL input low levels or ground connection, second voltage it should be noted that in the embodiment of the present invention The explanation that carries out exemplified by the VGH input high levels of end, the switching process of transistor is with all transistors in the embodiment of the present invention For the explanation carried out exemplified by P-type transistor.

The first stage S1, IN=0, CK1=0, CK2=1 of one picture frame；Wherein " 0 " represents low level, and " 1 " represents high Level.

First clock signal terminal CLK1 input low levels, the first transistor M1 and the 5th transistor M5 conductings.Signal inputs End IN voltage is exported to first node NET1 by the 5th transistor M5, and first node NET1 voltage is stored to the Two electric capacity C2.

Under first node NET1 control, the 4th transistor M4 conducting, and by first node NET1 voltage store to First electric capacity C1.In addition, first voltage end VGL voltage is exported to second transistor M2 grid by the first transistor M1, Second transistor M2 is turned on, and stored first voltage end VGL voltage by the first electric capacity C1.

Second clock signal end CLK2 input high levels, third transistor M3 and the 7th transistor M7 are in ending shape State；Because third transistor M3 ends, therefore third transistor M3 pulls up the input of control node PU no signals.

Under above-mentioned first node NET1 low level control, the 6th transistor M6 conductings, second voltage end VGH voltage Exported by the 6th transistor M6 to pull-up control node PU, and under pull-up control node PU control, the 8th transistor M8 In cut-off state, so that the 8th transistor M8 exports to signal output part OUTPUT no signals.

On this basis, because the 7th transistor M7 ends, the 9th transistor M9 grid no signal input is in cut-off State so that the 9th transistor M9 exports to signal output part OUTPUT no signals.

In summary, signal output part OUTPUT exports in this stage no signal.

The second stage S2, IN=0, CK1=1, CK2=0 of one picture frame.

It should be noted that the first clock signal terminal CLK1 switchs to high level, second clock by low level on last stage Signal end CLK2 switchs to low level by high level on last stage, can there is the first clock signal terminal during above-mentioned conversion At the time of CLK1 and second clock signal end CLK2 exports high level simultaneously, i.e., the first moment T1 as shown in Figure 3.In this situation Under, the second electric capacity C2 is by the low level output stored on last stage to first node NET1, in first node NET1 control Under, the 6th transistor M6 and the 4th transistor M4 are opened.Second voltage end VGH voltage is exported supreme by the 6th transistor M6 Control node PU is drawn, and pull-up control node PU voltage is stored to the 3rd electric capacity C3.In addition, the first clock signal terminal CLK1 high level is stored to the first electric capacity C1 by the 4th transistor M4, while the high level is inputted to second transistor M2 Grid, second transistor M2 cut-off.

Next, second clock signal CLK2 exports low level, the first clock signal terminal CLK1 still exports high level, the One transistor M1 and the 5th transistor M5 cut-offs.First electric capacity C1 is by the high level output that above-mentioned first moment T1 stores to second Transistor M2 grid, second transistor M2 cut-offs.Because the 5th transistor M5 ends, the input of first node NET1 no signals.

Second clock signal end CLK2 exports low level, and third transistor M3 and the 7th transistor M7 are opened.Due to second Transistor M2 ends, therefore pulls up control node PU no signals by third transistor M3 and export.

In addition, the second electric capacity C2 by the low level output stored on last stage to first node NET1, in first node Under NET1 low level control, the 4th transistor M4 and the 6th transistor M6 are opened.The height electricity of first clock signal terminal CLK outputs It is flat to be stored by the 4th transistor M4 into the first electric capacity C1.In addition, second voltage end VGH by the 6th transistor M6 export to 8th transistor M8 grid, while the 3rd electric capacity C3 also exports the high level that above-mentioned first moment T1 stores to the 8th crystal Pipe M8 grid, the 8th transistor M8 are remained turned-off, and are exported to signal output part OUTPUT no signals.

Because the 7th transistor M7 is opened, the low level output stored on last stage is passed through the 7th crystal by the second electric capacity C2 Pipe M7 is stored to the 4th electric capacity C4, while is exported to the 9th transistor M9 grid, the 9th transistor M9 and opened, first voltage end VGL is exported to signal output part OUTPUT by the 9th transistor M9.

In summary, signal output part OUTPUT exports low level in this stage.

Herein it should be noted that in above-mentioned second stage S2, low level that the second electric capacity C2 will be stored on last stage Stored by pulling down control node PD to the 4th electric capacity C4, therefore in order to ensure that the current potential for pulling down control node PD connects as far as possible Low level in nearly second electric capacity C2, and the fully charged normal outputs to maintain next stage of the 4th electric capacity C4 can be given, will Second electric capacity C2 capacitance is set greater than the 4th electric capacity C4 capacitance.

The phase III S3, IN=1, CK1=0, CK2=1 of one picture frame.

First clock signal terminal CLK1 exports low level, the first transistor M1 and the 5th transistor M5 conductings.Signal inputs End IN voltage is exported to first node NET1 by the 5th transistor M5, and first node NET1 voltage is stored to the Two electric capacity C2.First voltage end VGL voltage is exported to second transistor M2 grid by the first transistor M1, brilliant by second Body pipe M2 is turned on, and is stored first voltage end VGL voltage by the first electric capacity C1.

In addition, under first node NET1 control, the 4th transistor M4 and the 6th transistor M6 are in cut-off state. Because the 6th transistor M6 and third transistor M3 are in cut-off state, therefore the 8th transistor M8 grid no signal is defeated Enter, exported in cut-off state, and to signal output part OUTPUT no signals.

Second clock signal end CLK2 input high levels, third transistor M3 and the 7th transistor M7 are in ending shape State；Because third transistor M3 ends, the first pull-up control module 102 pulls up the input of control node PU no signals.Due to Seven transistor M7 end, the input of the 9th transistor M9 grid no signal, in cut-off state, to signal output part OUTPUT without Signal output.

4th electric capacity C4 exports the low level output stored on last stage to the 9th crystal by pulling down control node PD Pipe M9 grid, the 9th transistor M9 are opened, and first voltage end VGL is exported to signal output part by the 9th transistor M9 OUTPUT。

In summary, signal output part OUTPUT exports low level in this stage.

The fourth stage S4, IN=1, CK1=1, CK2=0 of one picture frame.

First clock signal terminal CLK1 exports high level, the first transistor M1 and the 5th transistor M5 cut-offs.

Second clock signal end CLK2 exports low level, and third transistor M3 and the 7th transistor M7 are opened.First electric capacity By the low level output second transistor M2 stored on last stage grid, second transistor M2 is opened C1, and by first voltage VGL voltage is held to be exported by third transistor M3 to pull-up control node PU, the 8th under pull-up control node PU control Transistor M8 is opened, and by second voltage end VGH voltage output to signal output part OUTPUT, while control node will be pulled up PU low level is stored to the 3rd electric capacity C3.

Second electric capacity C2 is by the high level output that phase III S3 is stored to first node NET1；First node NET1's The lower 6th transistor M6 cut-offs of high level control, pull up the output of control node PU no signals.

Further, since the 7th transistor M7 is opened, pass through the 7th transistor under first node NET1 high level control M7 is exported to drop-down control node PD, under drop-down control node PD control, the 9th transistor M9 cut-offs, to signal output part OUTPUT no signals are exported, while the voltage for pulling down control node PD is stored to the 4th electric capacity C4.

Meanwhile in the second electric capacity C2 by under the control of the high level stored on last stage, the 4th transistor M4.

In summary, signal output part OUTPUT exports high level in this stage.

Next, phase III S3 and fourth stage S4 signal input part IN, the first clock signal can be repeated in CLK1 and second clock signal end CLK2 control signal is held, enables to signal output part OUTPUT to keep the electricity of output second Pressure side VGH voltage, that is, keep high level output.

5th stage S5 of one picture frame, IN=0, CK1=0, CK2=1.

Second clock signal end CLK2 input high levels, third transistor M3 and the 7th transistor M7 are in ending shape State；Because third transistor M3 ends, the input of control node PU no signals is pulled up.

Under above-mentioned first node NET1 low level control, the 6th transistor M6 conductings, second voltage end VGH voltage Exported by the 6th transistor M6 to pull-up control node PU, and under pull-up control node PU control, the 8th transistor M8 In cut-off state, exported to signal output part OUTPUT no signals.

On this basis, because the 7th transistor M7 ends, the 9th transistor M9 grid no signal input is in cut-off State, exported to signal output part OUTPUT no signals.

Now, electric capacity on line, i.e., in the presence of signal wire selfcapacity, signal output part OUTPUT keeps output second Voltage end VGH voltage.

In summary, signal output part OUTPUT keeps output high level in this stage.

6th stage S6 of one picture frame, IN=0, CK1=1, CK2=0.

Due to the 6th stage S6 and second stage S2 signal input part IN, the first clock signal terminal CLK1 and second when The signal of clock signal end CLK2 inputs is identical, the switching state consistency of each transistor, each electric capacity charge and discharge state also one Causing so that signal output part OUTPUT output signal is also identical, therefore, the 6th stage S6 and second stage S2 detailed process Identical, i.e. signal output part OUTPUT also exports low level in this stage, and detailed process can be found in second stage S2, herein no longer Repeat.

Herein it should be noted that due to second stage S2 and the 6th stage S6 the first moment T1 (i.e. the first clock believe Number end CLK1 and second clock signal end CLK2 exports high level simultaneously) in, low electricity that the second electric capacity C2 will be stored on last stage Flat output, the 6th transistor M6 and the 4th transistor M4 are opened so that the first clock signal terminal CLK1 and second clock signal end The high electricity of CLK2 outputs stores to the first electric capacity C1 and the 3rd electric capacity C3 respectively, so as to ensure that working as second clock signal CLK2 exports During low level, second transistor M2 and the 8th transistor M8 are in cut-off state, and first voltage end VGL can be brilliant by the 9th Body pipe M9 is exported to signal output part OUTPUT, i.e. ensure that the stage can export low level.

In addition, the stage in addition to second stage S2 and the 6th stage S6 there is also above-mentioned first moment T1, but by The first moment T1 can't export high level to signal output part OUTPUT and produce conclusive influence in these stages, therefore The on off operating mode of each transistor is not described in detail the present invention in the first moment T1 to the above-mentioned stage.

Next, can before next image frame repeat the 5th stage S5 and the 6th stage S6 signal input part IN, First clock signal terminal CLK1 and second clock signal end CLK2 control signal so that signal output part OUTPUT keeps defeated Go out first voltage end VGL voltage.

Herein it should be noted that the switching process of transistor is using all transistors as P-type crystal in above-described embodiment Illustrated exemplified by pipe, when all transistors are N-type, it is necessary to which each control signal is overturn in Fig. 3, and will figure Second voltage end VGH is connected to the first voltage end VGL modules being connected or transistor in 1- Fig. 2, with second voltage end The module or transistor that VGH is connected are connected to first voltage end VGL.

Embodiments of the invention also provide a kind of gate driving circuit, as shown in figure 4, including at least two-stage cascade as above Any one described shift register cell, have with previous embodiment provide shift register cell identical structure and Beneficial effect, due to previous embodiment, the structure to the shift register cell and beneficial effect have carried out detailed retouch State, here is omitted.

Wherein, first order shift register cell RS1 signal input part IN connection initial signal end STV, except first Beyond level shift register cell RS1, upper level shift register cell RS (n-1) signal output part OUTPUT and next stage Shift register cell RS (n) signal input part IN is connected.Wherein, initial signal end STV is used to export initial signal, should The first order shift register cell RS1 of gate driving circuit start after above-mentioned initial signal is received to grid line (G1, G2 ... Gn) progressively scanned.

The embodiment of the present invention provides a kind of display device, including gate driving circuit as described above, has and foregoing reality The gate driving circuit identical structure and beneficial effect of example offer are provided.Because previous embodiment is to gate driving circuit Structure and beneficial effect are described in detail, and here is omitted.

It should be noted that in embodiments of the present invention, display device specifically can at least include liquid crystal display panel and Organic LED display panel, for example, the display panel can apply to liquid crystal display, LCD TV, DPF, In any product or part with display function such as mobile phone or tablet personal computer.

The embodiment of the present invention provides a kind of method for driving any one above-mentioned shift register cell.In an image In frame, this method includes：

First stage S1 specifically performs following operation：

Under the first clock signal terminal CLK1 control, input module 101 inputs a signal into end IN voltage output to the One node NET1；Energy-storage module 107 is stored first node NET1 voltage simultaneously.

First pull-up control module 102 is stored first voltage end VGL voltage.In first node NET1 control Under, second voltage end VGH voltage output is extremely pulled up control node PU by the second pull-up control module 103.

Wherein, first pull-up control module 102, pull-up module 105, drop-down control module 104, drop-down module 106 and Signal output part no signal exports.

Specifically, the first clock signal terminal CLK1 input low levels, the 5th transistor M5 conductings in input module 101, End IN voltage output is input a signal into first node NET1, meanwhile, the second electric capacity C2 in energy-storage module 107 by this first Node NET1 voltage is stored.

Next, the first clock signal terminal CLK1 input low levels, first pulls up the first transistor in control module 102 M1 is turned on, and first voltage end VGL voltage is stored to the first electric capacity C1；The high electricity of second clock signal end CLK2 inputs simultaneously It is flat, the third transistor M3 cut-offs in the first pull-up control module 102 so that the first pull-up control module 102 pulls up control Node PU no signals export.

Next, under above-mentioned first node NET1 low level control, the 6th in the second pull-up control module 103 is brilliant Body pipe M6 is turned on, and second voltage end VGH voltage output is extremely pulled up into control node PU.

Next, under above-mentioned pull-up control node PU high level control, pull up in module 105 at the 8th transistor M8 In cut-off state, exported to signal output part OUTPUT no signals.

Finally, second clock signal end CLK2 input high levels, the 7th transistor M7 cut-offs in control module 104 are pulled down Pull down control node PD so that the grid no signal input of the 9th transistor M9 in drop-down module 106 is also at cut-off shape State, and exported to signal output part OUTPUT no signals.

In summary, signal output part OUTPUT exports in this stage no signal.

Second stage S2 specifically performs following operation：

Under second clock signal end CLK2 control, drop-down control module 104 deposits energy-storage module 107 in the first stage The voltage output of storage pulls down module 106 by first voltage to drop-down control node PD, and under drop-down control node PD control VGL voltage output is held to signal output part OUTPUT, while the voltage for pulling down control node PD is stored.

Wherein, input module 101, first pulls up control module 102, second and pulls up control module 103, pull-up module 105 No signal exports.

Specifically, the first clock signal terminal CLK1 exports high level, the 5th transistor M5 cut-offs in input module 101, Inputted to first node NET1 no signals, and then cause the 6th transistor M6 cut-offs in the second pull-up control module 103, upwards Draw the input of control node PU no signals.

Next, this stage has the first clock signal terminal CLK1 and second clock signal end CLK2 exports high level simultaneously At the time of, i.e., the first moment T1 as shown in Figure 3.In the case, the second electric capacity C2 is defeated by the low level stored on last stage Go out to first node NET1, under first node NET1 control, the 4th transistor M4 is opened in the first pull-up control module 102 Open, and the first clock signal terminal CLK1 high level stored to the first electric capacity C1, while under first node NET1 control, The 6th transistor M6 is opened in second pull-up control module 103, and second voltage end VGH high level is stored to the 3rd electric capacity C3。

Next, when second clock signal end CLK2 exports low level, first in the first pull-up control module 102 is brilliant Body pipe M1 ends, and third transistor M3 conductings, the first electric capacity C1 is by the high level output that above-mentioned first moment T1 stores to second Transistor M2 grid, second transistor M2 cut-off so that first pull-up control module 102 pull up control node PU without Signal output.Meanwhile the 3rd the high level outputs that are stored at above-mentioned first moment T1 of electric capacity C3 to the 8th transistor M8 grid, So that pull-up module 105 exports to signal output part OUTPUT no signals.

Next, when second clock signal end CLK2 exports low level, the 7th transistor in control module 104 is pulled down M7 is opened, and by the second electric capacity C2 in energy-storage module 107 by the low level output stored on last stage to pulling down control node PD, under drop-down control node PD low level control, the 9th transistor M9 pulled down in module 106 is opened, and electric by first Pressure side VGL voltage output is stored to the 4th electric capacity to signal output part OUTPUT, while by the voltage for pulling down control node PD C4。

In summary, signal output part OUTPUT exports low level in this stage.

Phase III S3 specifically performs following operation：

Under the first clock signal terminal CLK1 control, input module 107 inputs a signal into end IN voltage output to the One node NET1, energy-storage module 107 are stored first node NET1 voltage.First pulls up control module 102 by first Clock signal terminal CLK1 voltage is stored.Drop-down module 106 keeps it turned on shape by the voltage that is stored in second stage State, and by second voltage end VGH voltage output to signal output part OUTPUT.

Wherein, the first pull-up control module 102, second pulls up control module 103, pull-up module 105, drop-down control module 104 no signals export.

Specifically, the first clock signal terminal CLK1 exports low level, the 5th transistor M5 conductings in input module 107, The high level for inputting a signal into end IN is exported to first node NET1 by the 5th transistor M5, and second in energy-storage module 107 Electric capacity C2 is stored first node NET1 high level.In addition, under first node NET1 high level control, on second The 6th transistor M6 cut-offs in control module 103 are drawn, pull up the output of control node PU no signals.

Next, the first clock signal terminal CLK1 exports low level, the first transistor M1 conductings, second clock signal end CLK2 exports high level, third transistor M3 cut-offs so that the first pull-up control module 102 pulls up control node PU no signals Output, and then cause the 8th transistor M8 cut-offs in pull-up module 105, exported to signal output part OUTPUT no signals.Together When, the first transistor M1 conductings in the first pull-up control module 102, the first clock signal terminal CLK1 voltage is stored to the One electric capacity C1.

Next, second clock signal end CLK2 exports high level, the 7th transistor M7 pulled down in control module 104 is cut Only, the output of control node PD no signals is pulled down.

Finally, the 4th electric capacity C4 in module 106 is pulled down by the low level stored on last stage by pulling down control node PD is exported to the 9th transistor M9 grid, and the 9th transistor M9 is opened, and first voltage end VGL is exported to signal output part OUTPUT。

In summary, signal output part OUTPUT exports low level in this stage.

Fourth stage S4 specifically performs following operation：

First pull-up control module 102 is in the first clock signal terminal CLK1, second clock signal end CLK2 and first segment Under point NET1 control, by the voltage that is stored in phase III S3 by first voltage end VGL voltage output to pulling up control Node PU so that pull-up module 105 controls the second terminal voltage VGH voltage output to signal output part OUTPUT, and by pull-up Node PU processed voltage is stored.

Energy-storage module 107 is by the voltage output that phase III S3 is stored to first node NET1.Pulling down control module 106 will First node NET1 voltage output is stored to drop-down control node PD, and by the voltage for pulling down control node PD.

Wherein, input module 101, second pulls up control module 103, the no signal output of drop-down module 106.

Specifically, the first clock signal terminal CLK1 exports high level, the 5th transistor M5 cut-offs in input module 101, Exported to first node NET1 no signals.

Next, second clock signal end CLK2 exports low level, third transistor M3 is opened, while the first electric capacity C1 exists The low level output stored on last stage is to second transistor M2 grid, second transistor M2 conductings, and by first voltage end VGL voltage by third transistor M3 export to pull-up control node PU, pull-up control node PU low level control under, Pull up the 8th transistor M8 conductings in control node PU, and by the second terminal voltage VGH voltage output to signal output part OUTPUT, while the low level for pulling up control node PU is stored to the 3rd electric capacity C3.

In addition, the second electric capacity C2 in energy-storage module 107 is by the high level output that phase III S3 is stored to first node NET1；Under first node NET1 high level control, the 6th transistor M6 cut-offs in the second pull-up control module 103, to Pull up the output of control node PU no signals.

In addition, second clock signal end CLK2 exports low level, the 7th transistor M7 pulled down in control module 106 is led It is logical, and will be exported in first node NET1 high level by the 7th transistor M7 to drop-down control node PD, controlled in drop-down Under node PD high level control, the 9th transistor M9 pulled down in module 106 is in cut-off state, to signal output part OUTPUT no signals are exported, while the high level for pulling down control node PD is stored to the 4th electric capacity C4.

In summary, signal output part OUTPUT exports high level in this stage.

Next, phase III S3 and fourth stage S4 signal input part IN, the first clock signal can be repeated in Hold CLK1 and second clock signal end CLK2 control signal so that signal output part OUTPUT keeps output second voltage end VGH voltage.

Herein it should be noted that during phase III S3 is repeated, although the input signal with phase III S3 It is completely the same, but due in fourth stage S4 the 3rd electric capacity C3 store low level, can keep the 8th transistor M8 turn on, 4th electric capacity C4 stores high level so that the 9th transistor M9 ends, so that second voltage end VGH can be by the Eight transistor M8 are exported to signal output part OUTPUT, therefore repeat the input signal of phase III S3, not repeatedly the 3rd rank Section S3 low-level output signal, and keep high level signal to continue to output.

5th stage S5 specifically performs following operation：

Under the first clock signal terminal CLK1 control, input module 107 inputs a signal into end IN voltage output to the One node NET1；Energy-storage module 107 is stored first node NET1 voltage simultaneously.

First pull-up control module 102 is stored the first clock signal terminal CLK1 voltage.In first node NET1 Control under, the second pull-up control module 103 is by second voltage end VGH voltage output to pulling up control node PU.On line In the presence of electric capacity, i.e. signal wire selfcapacity, signal output part OUTPUT keeps output second voltage end VGH voltage.

Wherein, the first pull-up control module 103, pull-up module 105, drop-down module 106 no signal output

In addition, the first clock signal terminal CLK1 input low levels, first pulls up the first transistor M1 in control module 102 Conducting, and first voltage end VGL voltage is stored to the first electric capacity C1；The high electricity of second clock signal end CLK2 inputs simultaneously It is flat, the third transistor M3 cut-offs in the first pull-up control module 102 so that the first pull-up control module 102 pulls up control Node PU no signals export.

Next, under above-mentioned first node NET1 low level control, the 6th in the second pull-up control module 103 is brilliant Body pipe M6 is turned on, and second voltage end VGH voltage output is extremely pulled up into control node PU.In pull-up control node PU height electricity Under flat control, pull up the 8th transistor M8 in module 105 and be in cut-off state, exported to signal output part OUTPUT no signals.

Next, second clock signal end CLK2 input high levels, the 7th transistor M7 pulled down in control module 104 is cut Only pull down control node PD so that the grid no signal input of the 9th transistor M9 in drop-down module 106 is also at cut-off State, exported to signal output part OUTPUT no signals.

In summary, on line in the presence of electric capacity, signal output part OUTPUT exports high level in this stage.

6th stage S6 specifically performs following operation：

Next, with second stage S2 the first moment T1, by the second electric capacity C2 in the low level stored on last stage, The 4th transistor M4 and the 6th transistor M6 can be caused to turn on, the first clock signal terminal CLK1 high level passes through the 4th crystal Pipe M4 is stored to the first electric capacity C1；Second voltage end VGH high level is stored to the 3rd electric capacity C3 by the 6th transistor M6.

In addition, second clock signal end CLK2 exports low level, the 7th transistor M7 pulled down in control module 104 is opened Open, and the low level output stored on last stage is extremely pulled down into control node PD by the second electric capacity C2 in energy-storage module 107, Under the low level control for pulling down control node PD, the 9th transistor M9 pulled down in module 106 is opened, and by first voltage end VGL voltage output is stored to the 4th electric capacity C4 to signal output part OUTPUT, while by the voltage for pulling down control node PD.

In summary, signal output part OUTPUT exports low level in this stage.

On this basis, repeated before next image frame the 5th stage S5 and the 6th stage S6 signal input IN ends, First clock signal terminal CLK1 and second clock signal end CLK2 control signal so that signal output part OUTPUT keeps defeated Go out first voltage end VGL voltage.

It should be noted that the course of work of the shift register cell is same as above in next image frame, including above-mentioned first Stage S1 to the 6th stage S6., can be in fourth stage when needing to increase the output pulse width of next stage shift register cell Phase III S3 and fourth stage S4 control signal is repeated after S4, so that signal output part OUTPUT keeps high level defeated Go out, reach the purpose of increase signal output part OUTPUT output signal pulsewidths.Certainly, above-mentioned is to increase signal output part The explanation that OUTPUT pulsewidths are adjusted, when needing to reduce signal output part OUTPUT pulsewidths, it is possible to reduce in fourth stage Phase III S3 and fourth stage S4 number of repetition after S4.

In addition, above-mentioned shift register cell by first stage S1 to the 6th stage S6 process, even-multiple can be realized Pulsewidth width so that the shift register cell can realize the application of the pulsewidth of even-multiple.Need what is illustrated herein It is that the pulsewidth of even-multiple refers to, signal output part OUTPUT exports the stage of high level, is the first clock signal terminal CLK1 or the The even-multiple of a two clock signal terminal CKL2 square wave pulse width.

The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any Those familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, should all be contained Cover within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.

Claims

1. a kind of shift register cell, it is characterised in that including input module, the first pull-up control module, the second pull-up control Molding block, drop-down control module, pull-up module, drop-down module and energy-storage module；

The input module connects the first clock signal terminal, signal input part and first node respectively, for described first By the voltage output of the signal input part to the first node under the control of clock signal terminal；

The first pull-up control module connects first voltage end, the first clock signal terminal, second clock signal end, described respectively First node and pull-up control node, in first clock signal terminal, the second clock signal end and described By the voltage output at the first voltage end to the pull-up control node under the control of first node；

The second pull-up control module connects second voltage end, the pull-up control node and the first node respectively, For under the control of the first node by the voltage output at the second voltage end to the pull-up control node；

The drop-down control module connects the second clock signal end, the first node and drop-down control node respectively, For under the control of the second clock signal end by the voltage output of the first node to the drop-down control node；

The pull-up module connects the pull-up control node, the second voltage end and signal output part respectively, for By the voltage output at the second voltage end to the signal output part under the control of the pull-up control node；

The drop-down module connects drop-down control node, the first voltage end and the signal output part respectively, uses By the voltage output at the first voltage end to the signal output part under the control in the drop-down control node；

The energy-storage module is connected between the first node and the signal output part, for by the electricity of the first node Pressure is stored, or the first node is charged.

2. shift register cell according to claim 1, it is characterised in that the first pull-up control module includes the One transistor, second transistor, third transistor, the 4th transistor and the first electric capacity；

Grid connection first clock signal terminal of the first transistor, the first pole connection first voltage end, second Pole is connected with the grid of the second transistor；

The pole of second transistor first connects the first voltage end, and the second pole connects the first pole of the third transistor；

The grid of the third transistor connects the second clock signal end, and the second pole connects the pull-up control node；

The grid connection first node of 4th transistor, the grid of the first pole connection second transistor, second Pole connects first clock signal terminal；

One end of first electric capacity connects the grid of the second transistor, the other end and the grid phase of the third transistor Connection.

3. shift register cell according to claim 1, it is characterised in that the input module includes the 5th crystal Pipe, the grid of the 5th transistor connect first clock signal terminal, and the first pole connects the signal input part, the second pole Connect the first node.

4. shift register cell according to claim 1, it is characterised in that the second pull-up control module includes the Six transistors, the grid of the 6th transistor connect the first node, and the first pole connects the second voltage end, the second pole Connect the pull-up control node.

5. shift register cell according to claim 1, it is characterised in that it is brilliant that the drop-down control module includes the 7th Body pipe；

The grid of 7th transistor connects the second clock signal end, and the first pole connects the first node, the second pole Connect the drop-down control node.

6. shift register cell according to claim 1, it is characterised in that the pull-up module includes the 8th transistor With the 3rd electric capacity；

The grid of 8th transistor connects the pull-up control node, and the first pole connects the second voltage end, the second pole Connect the signal output part；

One end of 3rd electric capacity connects the second voltage end, and the other end is connected with the grid of the 8th transistor.

7. shift register cell according to claim 1, it is characterised in that the drop-down module includes the 9th transistor With the 4th electric capacity；

The grid of 9th transistor connects the drop-down control node, and the first pole connects the first voltage end, the second pole Connect the signal output part；

One end of 4th electric capacity is connected with the grid of the 9th transistor, and the other end connects the second of the 9th transistor Pole.

8. shift register cell according to claim 1, it is characterised in that the energy-storage module includes the second electric capacity, One end of second electric capacity connects the first node, and the other end is connected with the signal output part.

9. a kind of gate driving circuit, it is characterised in that including at least two-stage cascade as described in claim any one of 1-8 Shift register cell；

The signal input part of first order shift register cell is connected with initial signal end；

In addition to the first order shift register cell, the signal output part and next stage of upper level shift register cell The signal input part of shift register cell is connected.

10. a kind of display device, it is characterised in that including gate driving circuit as claimed in claim 9.

11. a kind of driving method for being used to drive the shift register cell as described in claim any one of 1-8, its feature exist In in a picture frame, methods described includes：

First stage specifically performs following operation：

Under the control of the first clock signal terminal, input module inputs a signal into the voltage output at end to first node；Institute simultaneously Energy-storage module is stated to be stored the voltage of the first node；

First pull-up control module is stored the voltage at first voltage end；Under the control of the first node, on second Control module is drawn by the voltage output at second voltage end to the pull-up control node；

Wherein, the first pull-up control module, pull-up module, drop-down control module, drop-down module and signal output part no signal Output；

Second stage specifically performs following operation：

Under the control of the second clock signal end, the drop-down control module is by the energy-storage module in the first stage The voltage output of storage is to pulling down control node, and under the control of the drop-down control node, the drop-down module will described in The voltage output at first voltage end is stored to signal output part, while by the voltage of the drop-down control node；

Wherein, the input module, the first pull-up control module, the second pull-up control module, the pull-up module No signal exports；

Phase III specifically performs following operation：

Under the control of first clock signal terminal, the input module is by the voltage output of the signal input part to described First node, the energy-storage module are stored the voltage of the first node；The first pull-up control module is by described in The voltage of first clock signal terminal is stored；The drop-down module is opened by the holding of the voltage stored in the second stage Open state, and by the voltage output at the second voltage end to the signal output part；Wherein, the first pull-up control mould Block, the second pull-up control module, the pull-up module, the drop-down control module no signal output；

Fourth stage specifically performs following operation：

The first pull-up control module is in first clock signal terminal, the second clock signal end and the first segment Under the control of point, the voltage output at the first voltage end to the pull-up is controlled by the voltage stored in the phase III Node processed so that the pull-up module controls the voltage output of the second terminal voltage to the signal output part, and by the pull-up The voltage of node processed is stored；The energy-storage module is by the voltage output that the phase III stores to the first node； The drop-down control module saves the voltage output of the first node to the drop-down control node, and by the drop-down control The voltage of point is stored；Wherein, the input module, the second pull-up control module, the drop-down module no signal are defeated Go out；

It is repeated in the signal input part of phase III and fourth stage, the first clock signal terminal and second clock signal end Control signal so that signal output part keeps the voltage at output second voltage end；

5th stage specifically performed following operation：

Under the control of first clock signal terminal, the input module is by the voltage output of the signal input part to described First node；The energy-storage module is stored the voltage of the first node simultaneously；The first pull-up control module will The voltage of first clock signal terminal is stored；Under the control of the first node, the second pull-up control module By the voltage output at second voltage end to the pull-up control node；On line in the presence of electric capacity, the signal output part is protected Hold the voltage at output second voltage end；Wherein, it is described first pull-up control module, it is described pull-up module, it is described drop-down module without Signal output；

6th stage specifically performed following operation：

Under the control of the second clock signal end, the drop-down control module is by the energy-storage module in the first stage The voltage output of storage is to pulling down control node, and under the control of the drop-down control node, the drop-down module will described in The voltage output at first voltage end is stored to signal output part, while by the voltage of the drop-down control node；Wherein, institute State input module, the first pull-up control module, the second pull-up control module, the pull-up module no signal output；

Signal input part, first clock signal terminal and second in the 5th stage and the 6th stage are repeated before next image frame The control signal of clock signal terminal so that signal output part keeps the voltage at output first voltage end.