CN111798788B

CN111798788B - Light emission control circuit, light emission control driver, and display panel

Info

Publication number: CN111798788B
Application number: CN202010668905.1A
Authority: CN
Inventors: 王东平; 朱杰; 卢慧玲; 胡思明
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd
Priority date: 2020-07-13
Filing date: 2020-07-13
Publication date: 2022-09-20
Anticipated expiration: 2040-07-13
Also published as: CN111798788A

Abstract

The invention discloses a light emission control circuit, a light emission control driver and a display panel. The light-emitting control circuit comprises an input unit, a node control unit, a first output unit, a second output unit and a stabilizing unit; the input unit is used for providing input signals for the node control unit and the second output unit; the node control unit is used for outputting a control signal to the first output unit; the first output unit is used for outputting a first light emitting control signal according to the control signal, and the second output unit is electrically connected with the first clock signal line through the stabilizing unit and used for stably outputting a second light emitting control signal according to the input signal. The stabilizing unit can disconnect the second output unit from the first clock signal line, reduce the delay of the first clock signal provided by the first clock signal line, and improve the output stability of the light-emitting control circuit. Moreover, the number of times of charging the second output unit by the first clock signal line can be reduced, and the power consumption of the light emitting control circuit can be further reduced.

Description

Light emission control circuit, light emission control driver, and display panel

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a light-emitting control circuit, a light-emitting control driver and a display panel.

Background

The display panel is provided with a light-emitting control circuit which provides light-emitting control signals for the pixel units and controls the light-emitting devices in the pixel units to emit light, so that the display of the display panel is realized. In the prior art, the light-emitting control circuit has a problem of poor reliability, which results in poor reliability of the light-emitting control signal output by the light-emitting control circuit, and further causes a problem of easy display of the display panel.

Disclosure of Invention

The invention provides a light-emitting control circuit, a light-emitting control driver and a display panel, which are used for improving the stability of the light-emitting control circuit and reducing the power consumption of the light-emitting control circuit.

In a first aspect, an embodiment of the present invention provides a light emission control circuit, including an input unit, a node control unit, a first output unit, a second output unit, and a stabilization unit;

the input unit is used for providing input signals for the node control unit and the second output unit;

the node control unit is used for outputting a control signal to the first output unit; the first output unit is used for outputting a first light-emitting control signal according to the control signal, and the second output unit is electrically connected with the first clock signal line through the stabilizing unit and used for stably outputting a second light-emitting control signal according to the input signal.

Optionally, the stabilizing unit comprises a first transistor and a second transistor;

a gate of the first transistor is electrically connected to the input unit, a first pole of the first transistor is electrically connected to the first clock signal line, and a second pole of the first transistor and a second pole of the second transistor are electrically connected to the second output unit; a gate of the second transistor is electrically connected to the node control unit, and a first pole of the second transistor is electrically connected to the first power supply signal line.

Optionally, the input unit comprises a third transistor;

a gate of the third transistor is electrically connected to a second clock signal line, a first pole of the third transistor is electrically connected to an input signal line, and a second pole of the third transistor is electrically connected to the gate of the first transistor, the node control unit, and the second output unit.

Optionally, the node control unit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a first capacitor;

a gate of the fourth transistor is electrically connected to a second pole of the third transistor, a first pole of the fourth transistor is electrically connected to the second clock signal line, a second pole of the fourth transistor is electrically connected to a second pole of the fifth transistor, a gate of the eighth transistor, and a first pole of the first capacitor, a gate of the fifth transistor is electrically connected to the second clock signal line, a first pole of the fifth transistor is electrically connected to the second power signal line, a first pole of the eighth transistor is electrically connected to the first clock signal line, a second pole of the eighth transistor is electrically connected to a second pole of the first capacitor, a first pole of the seventh transistor, and a gate of the second transistor, a gate of the seventh transistor is electrically connected to the first clock signal line, and a second pole of the seventh transistor is electrically connected to a second pole of the sixth transistor, a gate of the sixth transistor is electrically connected to the second pole of the third transistor, and a first pole of the sixth transistor is electrically connected to the first power supply signal line.

Optionally, the first output unit includes a ninth transistor and a second capacitor;

a gate of the ninth transistor and a first electrode of the second capacitor are electrically connected to a second electrode of the sixth transistor, the first electrode of the ninth transistor and a second electrode of the second capacitor are electrically connected to the first power signal line, and the second electrode of the ninth transistor serves as a light emission control signal output terminal of the light emission control circuit.

Optionally, the second output unit comprises a tenth transistor and a third capacitor;

a gate of the tenth transistor and a first pole of the third capacitor are electrically connected to a second pole of the third transistor, a first pole of the tenth transistor is electrically connected to the second power signal line, and a second pole of the tenth transistor is electrically connected to a second pole of the ninth transistor; a second pole of the third capacitor is electrically connected to the second pole of the first transistor and the second pole of the second transistor.

Optionally, the light emission control circuit further includes an eleventh transistor and a twelfth transistor;

a gate of the eleventh transistor and a gate of the twelfth transistor are electrically connected to the second power signal line, a second pole of the third transistor is electrically connected to a gate of the tenth transistor through the eleventh transistor, and a second pole of the fourth transistor and a second pole of the fifth transistor are electrically connected to a gate of the eighth transistor through the twelfth transistor.

Optionally, the light emission control circuit further comprises a fourth capacitor;

a first pole of the fourth capacitor is electrically connected with a second pole of the third transistor, and a second pole of the fourth capacitor is electrically connected with the second clock signal line; alternatively, the first and second electrodes may be,

a first pole of the fourth capacitor is electrically connected to a gate of the tenth transistor, and a second pole of the fourth capacitor is electrically connected to the second power signal line.

In a second aspect, the embodiment of the present invention further provides a light emission control driver, which includes at least two stages of light emission control circuits provided in any embodiment of the present invention, and at least two stages of the light emission control circuits are cascaded.

In a third aspect, embodiments of the present invention further provide a display panel including the light emission control driver provided in any of the embodiments of the present invention.

According to the technical scheme of the embodiment of the invention, the stabilizing unit is arranged in the light-emitting control circuit, the second output unit is electrically connected with the first clock signal line through the stabilizing unit, and when the second output unit does not need the first clock signal line to provide the first clock signal to maintain the potential of the second output unit, the stabilizing unit can disconnect the second output unit from the first clock signal line, so that the load of the first clock signal line can be reduced, and the delay of the first clock signal provided by the first clock signal line can be reduced when the first clock signal provided by the first clock signal line jumps. Therefore, the problem of unstable output of the light-emitting control circuit caused by the second output unit outputting the second light-emitting control signal by mistake according to the first clock signal can be solved, and the output stability of the light-emitting control circuit is improved. In addition, because the delay of the first clock signal is reduced, when the node control unit outputs the control signal according to the first clock signal, the problem of unstable control signal output caused by the delay of the first clock signal can be reduced, so that the first output unit can output the first light-emitting control signal more stably according to the control signal, and the output stability of the light-emitting control circuit is improved. In addition, the stabilizing unit disconnects the second output unit from the first clock signal line, so that the number of times of charging the second output unit by the first clock signal line can be reduced, and the power consumption of the light-emitting control circuit can be further reduced.

Drawings

Fig. 1 is a schematic structural diagram of a conventional light emission control circuit;

FIG. 2 is a timing diagram of the light-emitting control circuit of FIG. 1;

FIG. 3 is a simulated timing diagram of a corresponding one of the emission control signals of the emission control circuit of FIG. 1;

FIG. 4 is a simulated timing diagram of the light emission control signal when the threshold voltage of the TFT in the light emission control circuit shown in FIG. 1 is negatively biased by 4V;

FIG. 5 is a simulated timing diagram of the light emission control signal when the threshold voltage of the TFT in the light emission control circuit shown in FIG. 1 is biased forward by 4V;

fig. 6 is a schematic structural diagram of a light-emitting control circuit according to an embodiment of the present invention;

FIG. 7 is a simulated timing diagram of the emission control signals output by the different emission control circuits;

fig. 8 is a schematic structural diagram of another light-emitting control circuit according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of another light-emitting control circuit according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of another light-emitting control circuit according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of another light-emitting control circuit according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of another light-emitting control circuit according to an embodiment of the present invention;

FIG. 13 is a timing diagram corresponding to the light-emitting control circuit provided in FIG. 12;

FIG. 14 is a simulated timing diagram of the emission control signal when the threshold voltage of the seventh transistor in the emission control circuit provided in FIG. 12 is biased forward by 4V;

FIG. 15 is a simulated timing diagram of a light emission control signal corresponding to the light emission control circuit provided in FIG. 12;

fig. 16 is a simulated timing diagram of the light emission control signal when the threshold voltage of the seventh transistor in the light emission control circuit provided in fig. 12 is negatively biased by 4V;

fig. 17 is a schematic structural diagram of another light-emitting control circuit according to an embodiment of the present invention;

fig. 18 is a schematic structural diagram of another light-emitting control circuit according to an embodiment of the present invention;

fig. 19 is a schematic structural diagram of another light-emitting control circuit according to an embodiment of the present invention;

fig. 20 is a schematic structural diagram of a light emission control driver according to an embodiment of the present invention;

fig. 21 is a schematic structural diagram of a display panel according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some structures related to the present invention are shown in the drawings, not all of them.

Fig. 1 is a schematic structural diagram of a conventional light-emitting control circuit. As shown in fig. 1, the light emission control circuit includes a 10T3C, and specifically includes a first thin film transistor M1, a second thin film transistor M2, a third thin film transistor M3, a fourth thin film transistor M4, a fifth thin film transistor M5, a sixth thin film transistor M6, a seventh thin film transistor M7, an eighth thin film transistor M8, a ninth thin film transistor M9, a tenth thin film transistor M10, a first storage capacitor Cs1, a second storage capacitor Cs2, and a pull-down capacitor Cp. Wherein a gate of the first thin film transistor M1, a gate of the third thin film transistor M3, and a first pole of the second thin film transistor M2 are electrically connected to the first clock signal input terminal ECK1, a first pole of the first thin film transistor M1 is electrically connected to the initialization signal input terminal EIN, a second pole of the first thin film transistor M1 is electrically connected to the gate of the second thin film transistor M2, a second pole of the second thin film transistor M2 is electrically connected to the second pole of the third thin film transistor M3, the gate of the fourth thin film transistor M4, the first pole of the first storage capacitor Cs1, and the gate of the eighth thin film transistor M8, a first pole of the third thin film transistor M3 and a second pole of the tenth thin film transistor M10 are electrically connected to the first power signal input terminal VGL, a first pole of the fourth thin film transistor M4, a first pole of the sixth thin film transistor M6, a first pole of the second storage capacitor Cs2, and a second pole of the ninth thin film transistor M9 are electrically connected to the ninth thin film signal input terminal VGH, a second pole of the fourth thin film transistor M4 is electrically connected to the first pole of the fifth thin film transistor M5, a second pole of the fifth thin film transistor M5 is electrically connected to the second pole of the first thin film transistor M1, a gate of the fifth thin film transistor M5, a gate of the seventh thin film transistor M7, a first pole of the eighth thin film transistor M8, and a second pole of the pull-down capacitor Cp are electrically connected to the second clock signal input terminal ECK2, a second pole of the eighth thin film transistor M8 is electrically connected to the second pole of the first storage capacitor Cs1 and the first pole of the seventh thin film transistor M7, a second pole of the seventh thin film transistor M7 is electrically connected to the second pole of the sixth thin film transistor M6, the second pole of the second storage capacitor Cs2, and the gate of the ninth thin film transistor M9, a second pole of the ninth thin film transistor M9 is electrically connected to the first pole of the tenth thin film transistor M10 and serves as a light emission control signal EMOUT terminal of the light emission control circuit, a gate of the tenth thin film transistor M10 is electrically connected to the first pole of the pull-down capacitor Cp and the gate of the sixth thin film transistor M6. The thin film transistors in the light emission control circuit in fig. 1 are all illustrated by taking P-type thin film transistors as examples.

Fig. 2 is a timing diagram corresponding to the light-emitting control circuit of fig. 1. The first power signal provided by the first power signal input terminal VGL is at a low level, and the second power signal provided by the second power signal input terminal VGH is at a high level. Eck1 is the timing of the first clock signal supplied from the first clock signal input terminal Eck1, Eck2 is the timing of the second clock signal supplied from the second clock signal input terminal Eck2, Ein is the timing of the initialization signal supplied from the initialization signal input terminal Ein, and EMout is the timing of the emission control signal output terminal EMout. The operation of the lighting control circuit is explained in conjunction with fig. 1 and 2.

In the first stage t11, Ein is high, Eck1 is low, and Eck2 is high. At this time, the first thin film transistor M1 and the third thin film transistor M3 are turned on, the fifth thin film transistor M5 and the seventh thin film transistor M7 are turned off, and the initialization signal Ein is transmitted to the gate of the second thin film transistor M2 through the first thin film transistor M1, and since the initialization signal Ein is at a high level, the second thin film transistor M2 and the sixth thin film transistor M6 are controlled to be turned off, and the Eck2 is at a high level, the initialization signal Ein and the second clock signal Eck2 control the tenth thin film transistor M10 to be turned off. The first power signal Vgl is transmitted to the gate of the eighth thin film transistor M8 and the gate of the fourth thin film transistor M4 through the third thin film transistor M3, and controls the fourth thin film transistor M4 and the eighth thin film transistor M8 to be turned on. The gate potential of the ninth thin film transistor M9 is not changed, and the second storage capacitor Cs2 maintains the potential of the gate of the ninth thin film transistor M9 of the previous frame, so that the ninth thin film transistor M9 is turned off, and thus the emission control signal output terminal EMOUT outputs the level of the previous frame as a low level.

In the second stage t12, Ein is high, Eck1 is high, and Eck2 is low. At this time, the first thin film transistor M1 and the third thin film transistor M3 are turned off, the fifth thin film transistor M5 and the seventh thin film transistor M7 are turned on, the gate potential of the fourth thin film transistor M4 and the gate potential of the eighth thin film transistor M8 are maintained at a low level by the first storage capacitor Cs1, and the fourth thin film transistor M4 and the eighth thin film transistor M8 are turned on. The second clock signal Eck2 is transmitted to the seventh tft M7 through the eighth tft M8, and transmitted to the gate of the ninth tft M9 through the seventh tft M7, so as to control the ninth tft M9 to be turned on, so that the light-emitting control signal output terminal EMOUT outputs the second power signal VGH provided by the second power signal input terminal VGH, and the second power signal VGH is at a high level. Meanwhile, the second power signal Vgh is output to the gate of the tenth thin film transistor M10 through the fourth thin film transistor M4 and the fifth thin film transistor M5, and controls the tenth thin film transistor M10 to be turned off.

In addition, due to the coupling effect of the pull-down capacitor Cp, the impedance load of the second clock signal provided by the second clock signal input terminal ECK2 is increased, so that the second clock signal ECK2 has a larger delay. When the fifth tft M5 cannot be rapidly controlled to be turned on by the second clock signal Eck2, the gate potential of the tenth tft M10 is lowered due to the coupling effect of the pull-down capacitor Cp, so that the tenth tft M10 is turned on, and the emission control signal output terminal EMOUT outputs the first power signal VGL provided by the first power signal input terminal VGL, so that the emission control circuit outputs an abnormal output. Fig. 3 is a simulated timing diagram of a corresponding one of the light emission control signals of the light emission control circuit provided in fig. 1. As shown in fig. 3, the abscissa is time, and the ordinate is the voltage of the light emission control signal. During the period when the light emission control signal is at the high level, the light emission control signal may output an abnormal 01, which may cause the light emission control circuit to output an unstable output. At the same time, the second clock signal has a larger load, which also increases the power consumption of the lighting control circuit. Moreover, when the threshold voltage of the seventh thin film transistor M7 has a negative bias, the seventh thin film transistor M7 is hard to turn on, and the large delay of the second clock signal Eck2 further increases the difficulty of turning on the seventh thin film transistor M7, so that the seventh thin film transistor M7 cannot turn on normally at the second stage t12, and the gate of the ninth thin film transistor M9 cannot write a low level normally, thereby causing the abnormal output of the emission control signal output terminal EMOUT. Fig. 4 is a simulated timing diagram of light-emitting control signals when the threshold voltage of the thin film transistor in the light-emitting control circuit provided in fig. 1 is negatively biased by 4V. As shown in fig. 4, the abscissa is time, and the ordinate is the voltage of the light emission control signal. When the threshold voltage of the seventh thin film transistor M7 is negatively biased by 4V, the emission control signal output terminal EMOUT cannot normally output a high level, which results in an unstable output of the emission control circuit.

In the third stage t13, Ein is high, Eck1 is low, and Eck2 is high. At this time, the first thin film transistor M1 and the third thin film transistor M3 are turned on, the second thin film transistor M2, the fifth thin film transistor M5, the sixth thin film transistor M6 and the seventh thin film transistor M7 are turned off, the second storage capacitor Cs2 maintains the gate potential of the ninth thin film transistor M9, and controls the ninth thin film transistor M9 to be turned on, so that the emission control signal output terminal EMOUT outputs the second power supply signal VGH supplied from the second power supply signal input terminal VGH, and becomes a high level. The initialization signal Ein and the second clock signal Eck2 control the tenth thin film transistor M10 to be turned off.

In the fourth stage t14, Ein is low, Eck1 is high, and Eck2 is low. At this time, the first thin film transistor M1 and the third thin film transistor M3 are turned off, the fifth thin film transistor M5 and the seventh thin film transistor M7 are turned on, the gate potential of the fourth thin film transistor M4 and the gate potential of the eighth thin film transistor M8 are maintained at a low level by the first storage capacitor Cs1, and the fourth thin film transistor M4 and the eighth thin film transistor M8 are turned on. The second clock signal Eck2 is transmitted to the seventh tft M7 through the eighth tft M8, and transmitted to the gate of the ninth tft M9 through the seventh tft M7, so as to control the ninth tft M9 to be turned on, so that the light-emitting control signal output terminal EMOUT outputs the second power signal VGH provided by the second power signal input terminal VGH, and the second power signal VGH is at a high level. Meanwhile, the second power signal Vgh is output to the gate of the tenth thin film transistor M10 through the fourth thin film transistor M4 and the fifth thin film transistor M5, and controls the tenth thin film transistor M10 to be turned off. The second clock signal Eck2 has a large delay due to the coupling effect of the pull-down capacitor Cp. When the fifth tft M5 cannot be rapidly controlled to be turned on by the second clock signal Eck2, the gate potential of the tenth tft M10 is lowered due to the coupling effect of the pull-down capacitor Cp, so that the tenth tft M10 is turned on, and the emission control signal output terminal EMOUT outputs the first power signal VGL provided by the first power signal input terminal VGL, so that the emission control circuit outputs an abnormal output.

In the fifth stage t15, Ein is low, Eck1 is low, and Eck2 is high. At this time, the first thin film transistor M1, the second thin film transistor M2, the third thin film transistor M3, the sixth thin film transistor M6, and the eighth thin film transistor M8 are turned on, and the fifth thin film transistor M5 and the seventh thin film transistor M7 are turned off. The second power signal Vgh is transmitted to the gate of the ninth thin film transistor M9 through the sixth thin film transistor M6, and controls the ninth thin film transistor M9 to be turned off. The initialization signal Ein is transmitted to the tenth tft M10 through the first tft M1, and controls the tenth tft M10 to be turned on, so that the emission control signal output terminal EMOUT outputs the first power signal VGL provided by the first power signal input terminal VGL at a low level. Moreover, when the threshold voltage of the seventh thin film transistor M7 is positively biased, the seventh thin film transistor M7 is hard to turn off, the large delay of the second clock signal Eck2 further increases the difficulty of turning off the seventh thin film transistor M7, so that the seventh thin film transistor M7 cannot be turned off normally in the fifth stage t15, and the gate of the ninth thin film transistor M9 continues to write a low level, thereby causing the abnormal output of the emission control signal output terminal EMOUT. Fig. 5 is a simulated timing diagram of light-emitting control signals when the threshold voltage of the thin film transistor in the light-emitting control circuit provided in fig. 1 is positively biased to 4V. As shown in fig. 5, the abscissa is time, and the ordinate is the voltage of the light emission control signal. When the threshold voltage of the seventh thin film transistor M7 is biased positively by 4V, the light emission control signal output terminal EMOUT has a high level output during the output of the low level, resulting in an unstable output of the light emission control circuit.

In view of the above technical problems, embodiments of the present invention provide a light emitting control circuit. Fig. 6 is a schematic structural diagram of a light-emitting control circuit according to an embodiment of the present invention. As shown in fig. 6, the light emission control circuit includes an input unit 110, a node control unit 120, a first output unit 130, a second output unit 140, and a stabilization unit 150; the input unit 110 is used for providing input signals for the node control unit 120 and the second output unit 140; the node control unit 120 is configured to output a control signal to the first output unit 130; the first output unit 130 is configured to output a first light emission control signal according to a control signal, and the second output unit 140 is electrically connected to the first clock signal line CK1 through the stabilizing unit 150 and configured to stably output a second light emission control signal according to an input signal.

In particular, the light emission control circuit may be applied to a display panel for controlling light emission time of a pixel unit in the display panel. The display panel further includes a first power signal line VH, an input signal line EN, a second power signal line VL, a first clock signal line CK1, and a second clock signal line CK2 for supplying a driving signal to the light emission control circuit to drive the light emission control circuit to output a light emission control signal. The first power signal supplied from the first power signal line VH may be at a high level, the second power signal supplied from the second power signal line VL may be at a low level, and the first clock signal supplied from the first clock signal line CK1 and the second clock signal supplied from the second clock signal line CK2 may be clock signals having opposite phases. A control terminal of the input unit 110 is electrically connected to the second clock signal line CK2, an input terminal of the input unit 110 is electrically connected to the input signal line EN, and an output terminal of the input unit 110 is electrically connected to the node control unit 120, the second output unit 140, and the stabilization unit 150, respectively. When the control terminal of the input unit 110 controls the input terminal and the output terminal of the input unit 110 to be turned on by the second clock signal supplied from the second clock signal line CK2, the initialization signal supplied from the input signal line EN is transmitted to the node control unit 120, the second output unit 140, and the stabilizing unit 150 through the input unit 110. The node control unit 120 is electrically connected to the first clock signal line CK1, the second clock signal line CK2, the first power signal line VH, the second power signal line VL, the first output unit 130, and the stabilizing unit 150, respectively, and controls the first output unit 130 to output the first light emission control signal according to signal output control signals provided from the first clock signal line CK1, the second clock signal line CK2, the first power signal line VH, and the second power signal line VL, and simultaneously controls the stabilizing unit 150 to output the first power signal to the second output unit 140. The first output unit 130 is electrically connected to the first power signal line VH, and is configured to output a first power signal according to a control signal provided by the node control unit 120, where the first lighting control signal is a first power signal, i.e., a high level. The second output unit 140 is electrically connected to the second power signal line VL, and is configured to output a second power signal according to the input signal provided by the input unit 110, where the second light-emitting control signal is a second power signal, i.e., a low level. The stabilizing unit 150 is electrically connected to the first clock signal line CK1 and also electrically connected to the second output unit 140. That is, the first clock signal line CK1 is electrically connected to the second output unit 140 through the stabilizing unit 150. When the second output unit 140 does not need the first clock signal line CK1 to supply the first clock signal to maintain the voltage level of the second output unit 140, the stabilizing unit 150 may disconnect the second output unit 140 from the first clock signal line CK1, so that the load of the first clock signal line CK1 may be reduced, and the delay of the first clock signal supplied from the first clock signal line CK1 may be reduced when the first clock signal supplied from the first clock signal line CK1 transitions. Therefore, the problem of unstable output of the light emitting control circuit caused by the second output unit 140 outputting the second light emitting control signal by mistake according to the first clock signal can be reduced, and the output stability of the light emitting control circuit is improved. In addition, since the delay of the first clock signal is reduced, when the node control unit 120 outputs the control signal according to the first clock signal, the problem of unstable output of the control signal due to the delay of the first clock signal can be reduced, so that the first output unit 120 can more stably output the first light emission control signal according to the control signal, and the output stability of the light emission control circuit can be improved. Fig. 7 is a simulated timing diagram of light emission control signals output from different light emission control circuits. Wherein the abscissa is time, and the ordinate is the output voltage of the light emission control signal. Curve 1 is a timing sequence of a light emitting control signal output by the light emitting control circuit provided in the prior art, and curve 2 is a timing sequence of a light emitting control signal output by the light emitting control circuit provided in the embodiment of the present invention. As can be seen from the curves 1 and 2, the low level output fluctuation of the light emission control signal output by the light emission control circuit provided in the embodiment of the present invention is relatively small, so that the stability of the light emission control signal output by the light emission control circuit is improved. In addition, the stabilizing unit 150 disconnects the second output unit 140 from the first clock signal line CK1, so that the number of times that the first clock signal line CK1 charges the second output unit 140 can be reduced, and the power consumption of the light emission control circuit can be reduced.

Fig. 8 is a schematic structural diagram of another light-emitting control circuit according to an embodiment of the present invention. As shown in fig. 8, the stabilizing unit includes a first transistor T1 and a second transistor T2; a gate of the first transistor T1 is electrically connected to the input unit 110, a first pole of the first transistor T1 is electrically connected to the first clock signal line CK1, and a second pole of the first transistor T1 and a second pole of the second transistor T2 are electrically connected to the second output unit 140; a gate of the second transistor T2 is electrically connected to the node control unit 120, and a first pole of the second transistor T2 is electrically connected to the first power supply signal line VH.

Specifically, it is exemplarily shown in fig. 8 that the first transistor T1 and the second transistor T2 are P-type transistors. The gate of the first transistor T1 is electrically connected to the input unit 110, and thus the first transistor T1 is turned on or off according to an input signal provided from the input unit 110. When the input signal provided by the input unit 110 is at a low level, the first transistor T1 is turned on, and the first clock signal provided by the first clock signal line CK1 can be transmitted to the second output unit 140 through the first transistor T1, so as to provide a holding potential effect for the second output unit 140. When the input signal provided by the input unit 110 is at a high level, the first transistor T1 is turned off, and the first clock signal line CK1 is disconnected from the second output unit 140, so that the load of the first clock signal line CK1 can be reduced, and further, when the first clock signal provided by the first clock signal line CK1 jumps, the delay of the first clock signal provided by the first clock signal line CK1 can be reduced, and further, the problem of unstable output of the light emitting control circuit caused by the second output unit 140 mistakenly outputting the second light emitting control signal according to the first clock signal can be reduced, and the output stability of the light emitting control circuit is improved. In addition, since the delay of the first clock signal is reduced, when the node control unit 120 outputs the control signal according to the first clock signal, the problem of unstable output of the control signal due to the delay of the first clock signal can be reduced, so that the first output unit 120 can more stably output the first light emission control signal according to the control signal, and the output stability of the light emission control circuit can be improved.

Fig. 9 is a schematic structural diagram of another light-emitting control circuit according to an embodiment of the present invention. As shown in fig. 9, the input unit 110 includes a third transistor T3; a gate of the third transistor T3 is electrically connected to the second clock signal line CK2, a first pole of the third transistor T3 is electrically connected to the input signal line EN, and a second pole of the third transistor T3 is electrically connected to the gate of the first transistor T1, the node control unit 120, and the second output unit 140.

Specifically, it is exemplarily shown in fig. 9 that the third transistor T3 is a P-type transistor. When the second clock signal provided by the second clock signal line CK2 is at a low level and the input signal provided by the input signal line EN is at a high level, the input signal controls the second output unit 140 to disable outputting the second light-emitting control signal after passing through the third transistor T3, and the light-emitting control circuit outputs the first light-emitting control signal at a high level. When the second clock signal provided by the second clock signal line CK2 is at a low level and the input signal provided by the input signal line EN is at a low level, the input signal passes through the third transistor T3 and then controls the second output unit 140 to output the second light-emitting control signal, and the light-emitting control circuit outputs the second light-emitting control signal at a low level.

Fig. 10 is a schematic structural diagram of another light-emitting control circuit according to an embodiment of the present invention. As shown in fig. 10, the node control unit 120 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a first capacitor C1; a gate of the fourth transistor T4 is electrically connected to a second pole of the third transistor T3, a first pole of the fourth transistor T4 is electrically connected to the second clock signal line CK2, a second pole of the fourth transistor T4 is electrically connected to a second pole of the fifth transistor T5, a gate of the eighth transistor T8 and a first pole of the first capacitor C1, a gate of the fifth transistor T5 is electrically connected to the second clock signal line CK2, a first pole of the fifth transistor T5 is electrically connected to the second power signal line VL, a first pole of the eighth transistor T8 is electrically connected to the first clock signal line CK1, a second pole of the eighth transistor T8 is electrically connected to the second pole of the first capacitor C1, a first pole of the seventh transistor T7 and a gate of the second transistor T2, a gate of the seventh transistor T7 is electrically connected to the first clock signal line CK1, a second pole of the seventh transistor T7 is electrically connected to the second pole of the sixth transistor T6, a gate of the sixth transistor T6 is electrically connected to the third transistor T3, a first pole of the sixth transistor T6 is electrically connected to the first power supply signal line VH.

Specifically, it is exemplarily shown in fig. 10 that the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all P-type transistors. The seventh transistor T7 is electrically connected to the first output unit 130 through the node 160. When the second clock signal supplied from the second clock signal line CK2 is at a low level, the fifth transistor T5 is turned on, the second power supply signal supplied from the second power supply signal line VL is input to the gate of the eighth transistor T8, and the eighth transistor T8 is turned on. When the first clock signal provided from the first clock signal line CK1 is at a low level, the seventh transistor T7 is turned on, the first clock signal is transmitted to the node 160 through the seventh transistor T7, and the first output unit 130 outputs the first power signal according to the first clock signal at the node 160, i.e., at a high level. When the sixth transistor T6 is turned on, the first power signal provided by the first power signal line VH is transmitted to the node 160 through the sixth transistor T6, i.e., the potential of the node 160 is at a high level, and the first output unit 130 cannot output the first power signal according to the first power signal at the node 160.

In addition, when the second clock signal is at a low level, the second transistor T2 is turned on, and the first power signal provided by the first power signal line VH may be transmitted to the second output unit 140 through the second transistor T2 to maintain the potential of the second output unit 140.

Fig. 11 is a schematic structural diagram of another light-emitting control circuit according to an embodiment of the present invention. As shown in fig. 11, the first output unit 130 includes a ninth transistor T9 and a second capacitor C2; a gate of the ninth transistor T9 and a first pole of the second capacitor C2 are electrically connected to the second pole of the sixth transistor T6, a first pole of the ninth transistor T9 and a second pole of the second capacitor C2 are electrically connected to the first power signal line VH, and a second pole of the ninth transistor T9 serves as a light emission control signal output terminal OUT of the light emission control circuit.

Specifically, it is exemplarily shown in fig. 11 that the ninth transistor T9 is a P-type transistor. When the control signal supplied from the node 160 is at the low level, the ninth transistor T9 is turned on, so that the first power signal supplied from the first power signal line VH is output through the ninth transistor T9, and the light emission control signal output terminal OUT of the light emission control circuit outputs the first light emission control signal. When the control signal provided at the node 160 is at a high level, the ninth transistor T9 is turned off, and the first power signal provided by the first power signal line VH cannot be output through the ninth transistor T9. In addition, when the node 160 is in a floating state, the second capacitor C2 may maintain the state of the previous stage of the node 160, thereby maintaining the state of the previous stage of the ninth transistor T9.

Fig. 12 is a schematic structural diagram of another light-emitting control circuit according to an embodiment of the present invention. As shown in fig. 12, the second output unit 140 includes a tenth transistor T10 and a third capacitor C3; a gate of the tenth transistor T10 and a first pole of the third capacitor C3 are electrically connected to the second pole of the third transistor T3, a first pole of the tenth transistor T10 is electrically connected to the second power signal line VL, and a second pole of the tenth transistor T10 is electrically connected to the second pole of the ninth transistor T9; a second pole of the third capacitor C3 is electrically connected to the second pole of the first transistor T1 and the second pole of the second transistor T2.

In particular, fig. 12 exemplarily shows that the tenth transistor T10 is a P-type transistor. When the second clock signal supplied from the second clock signal line CK2 is at a low level and the input signal supplied from the input signal line EN is at a low level, the input signal is transmitted to the gate of the tenth transistor T10 through the third transistor T3 to control the tenth transistor T10 to be turned on, the second power signal supplied from the second power signal line VL is output through the tenth transistor T10, and the light emission control signal output terminal OUT of the light emission control circuit outputs the second light emission control signal. When the second clock signal supplied from the second clock signal line CK2 is at a low level and the input signal supplied from the input signal line EN is at a high level, the input signal is transmitted to the gate of the tenth transistor T10 through the third transistor T3, so that the tenth transistor T10 is controlled to be turned off, and the second power signal supplied from the second power signal line VL cannot be output through the tenth transistor T10. When the third transistor T3 is turned off, the gate of the tenth transistor T10 is in a floating state, and the state of the previous stage of the tenth transistor T10 can be maintained by the coupling action of the third capacitor C3 according to the first clock signal of the first clock signal line CK 1.

Fig. 13 is a timing diagram corresponding to the light-emitting control circuit provided in fig. 12. Where Vh is a timing of the first power supply signal supplied from the first power supply signal line Vh, Vl is a timing of the second power supply signal supplied from the second power supply signal line Vl, CK1 is a timing of the first clock signal supplied from the first clock signal line CK1, CK2 is a timing of the second clock signal supplied from the second clock signal line CK2, EN is a timing of the input signal supplied from the input signal line EN, and out is a timing of the light emission control signal output from the light emission control circuit. The operation of the light emission control circuit will be described with reference to fig. 12 and 13.

In the first stage t21, en is low, ck1 is high, ck2 is low, Vl is low, and Vh is high. The third transistor T3 and the fifth transistor T5 are turned on, and the seventh transistor T7 is turned off. The input signal provided by the input signal line EN is transmitted to the gate of the fourth transistor T4, the gate of the sixth transistor T6, the gate of the tenth transistor T10 and the gate of the first transistor T1 through the third transistor T3, so that the tenth transistor T10 and the first transistor T1 are controlled to be turned on, and the second power supply signal provided by the second power supply signal line VL is transmitted to the emission control signal output terminal OUT of the emission control circuit through the tenth transistor T10, so that the emission control circuit outputs the second emission control signal at a low level. In addition, when the input signal maintains the gate potential of the tenth transistor T10 at a low level and the first transistor T1 is turned on, the gate potential of the tenth transistor T10 does not vary according to the first clock signal supplied from the first clock signal line CK1, and the tenth transistor T10 is kept turned on. Meanwhile, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned on, the gate of the eighth transistor T8 is at a low level, the eighth transistor T8 is turned on, and the first clock signal provided from the first clock signal line CK1 is transmitted to the first pole of the seventh transistor T7 and the gate of the second transistor T2 through the eighth transistor T8. The seventh transistor T7 is turned off and cannot be transmitted to the node 160 through the seventh transistor T7. And the second transistor T2 is controlled to be turned off, so that the first power signal supplied from the first power signal line VH cannot be transmitted to the second pole of the third capacitor C3. Meanwhile, the sixth transistor T6 is turned on, the first power signal supplied from the first power signal line VH is transmitted to the node 160 through the sixth transistor T6, thereby controlling the ninth transistor T9 to be turned off, and the light emission control signal output terminal OUT cannot output the first light emission control signal.

In the second stage t22, en is low, ck1 is low, ck2 is high, Vl is low, and Vh is high. The third transistor T3 and the fifth transistor T5 are turned off, and the seventh transistor T7 is turned on. The gate of the eighth transistor T8 is in a floating state at this time. Since the first capacitor C1 is connected in series between the gate and the second pole of the eighth transistor T8, the first capacitor C1 can maintain the gate potential of the eighth transistor T8. That is, the gate potential of the eighth transistor T8 is maintained at a low level by the sustaining action of the first capacitor C1, the eighth transistor T8 is turned on, the first clock signal supplied from the first clock signal line CK1 is transmitted to the gate of the second transistor T2 and the first pole of the seventh transistor T7 through the eighth transistor T8, the second transistor T2 is turned on, the first power signal supplied from the first power signal line VH is transmitted to the second pole of the third capacitor C3 through the second transistor T2, and the second pole of the third capacitor C3 is maintained at a high level. While the gates of the tenth transistor T10 and the first transistor T1 are in a floating state, the gate of the tenth transistor T10 is kept at a low level by the holding action of the third capacitor C3, the tenth transistor T10 and the first transistor T1 are turned on, and the second power supply signal supplied from the second power supply signal line VL is transmitted to the light emission control signal output terminal OUT of the light emission control circuit through the tenth transistor T10 to be outputted as a low level. Meanwhile, the sixth transistor T6 is turned on, the first power signal supplied from the first power signal line VH is transmitted to the node 160 through the sixth transistor T6, thereby controlling the ninth transistor T9 to be turned off, and the light emission control signal output terminal OUT cannot output the first light emission control signal.

In the third stage t23, en is high, ck1 is high, ck2 is low, Vl is low, and Vh is high. The third transistor T3 and the fifth transistor T5 are turned on, and the seventh transistor T7 is turned off. The input signal provided by the input signal line EN is transmitted to the gate of the fourth transistor T4, the gate of the sixth transistor T6, the gate of the tenth transistor T10 and the gate of the first transistor T1 through the third transistor T3, and controls the fourth transistor T4, the sixth transistor T6, the tenth transistor T10 and the first transistor T1 to be turned off. Since the fifth transistor T5 is turned on, the second power signal supplied from the second power signal line VL is transmitted to the gate of the eighth transistor T8, the gate of the eighth transistor T8 is at a low level, the eighth transistor T8 is turned on, and the first clock signal supplied from the first clock signal line CK1 is transmitted to the first pole of the seventh transistor T7 and the gate of the second transistor T2 through the eighth transistor T8. The seventh transistor T7 and the second transistor T2 are turned off and cannot be transmitted to the node 160 through the seventh transistor T7. The node 160 is in a floating state, and the second capacitor C2 holds the potential of the node 160 at a previous stage, so that the ninth transistor T9 is turned off, and the light-emitting control signal output terminal OUT cannot output the first light-emitting control signal. Moreover, the gate of the tenth transistor T10 is an input signal, i.e., high level, the tenth transistor T10 is turned off, and the second power signal provided by the second power signal line VL cannot be transmitted to the light emission control signal output terminal OUT of the light emission control circuit through the tenth transistor T10. At this time, the output potential of the emission control signal output OUT is a potential at which the capacitor on the emission control signal line maintains its previous stage, and is at a low level. Meanwhile, the gate of the first transistor T1 is at a high level, the first transistor T1 is turned off, and the first clock signal line CK1 is disconnected from the third capacitor C3, so that the capacitive load of the first clock signal line CK1 can be reduced, and further, the delay when the first clock signal jumps from a low level to a high level at the beginning of the third stage T23 can be reduced, and when the threshold voltage of the seventh transistor T7 is positively biased, the first clock signal jumps to a high level quickly at the third stage T23, which is favorable for the seventh transistor T7 to be turned off, so that the difficulty in turning off the seventh transistor T7 due to the shift of the threshold voltage is reduced, so that the seventh transistor T7 is turned off quickly at the third stage T23, the first clock signal is transmitted to the gate of the ninth transistor T9, the ninth transistor T9 is controlled to be turned off, and the phenomenon that the emission control signal output terminal OUT outputs the first emission control signal due to the false turn-on of the ninth transistor T9 is reduced, the stability of the light-emitting control signal output by the light-emitting control circuit is improved. Fig. 14 is a simulated timing diagram of the light emission control signal when the threshold voltage of the seventh transistor in the light emission control circuit provided in fig. 12 is positively biased to 4V. The abscissa is time, and the ordinate is voltage of the light emission control signal. As can be seen from fig. 5 and 14, when the threshold voltage of the seventh transistor T7 is biased forward by 4V, the light emission control signal output terminal OUT can reduce the erroneous output of the high level when outputting the low level, thereby improving the stability of the light emission control signal.

In the fourth phase t24, en is high, ck1 is low, ck2 is high, Vl is low, and Vh is high. The third transistor T3 and the fifth transistor T5 are turned off, and the seventh transistor is turned on. The gate of the eighth transistor T8 is in a floating state at this time. Due to the holding function of the first capacitor C1, the gate voltage of the eighth transistor T8 can be maintained at the previous stage, and is at a low level, and the eighth transistor T8 is turned on. The first clock signal supplied from the first clock signal line CK1 is transmitted to the gate of the second transistor T2 and the first pole of the seventh transistor T7 through the eighth transistor T8, the first clock signal is transmitted to the node 160 through the seventh transistor T7 to control the ninth transistor T9 to be turned on, and the first power signal supplied from the first power signal line VH is transmitted to the light emission control signal output terminal OUT through the ninth transistor T9 to be outputted as the first light emission control signal at a high level. Meanwhile, the second transistor T2 is turned on, the gates of the tenth transistor T10 and the first transistor T1 are in a floating state, and the second pole potential of the third capacitor C3 is the first power signal and is at a high level. The third capacitor C3 maintains the gate potential of the tenth transistor T10 at a high level, the tenth transistor T10 and the first transistor T1 are turned off, and the second power signal provided by the second power signal line VL cannot be transmitted to the light emission control signal output terminal OUT of the light emission control circuit through the tenth transistor T10. At this time, the first transistor T1 is turned off, and the first clock signal line CK1 is prevented from being electrically connected to the third capacitor C3, so that the capacitive load of the first clock signal line CK1 can be reduced, and further, the delay when the first clock signal jumps from a high level to a low level at the start of the fourth stage T24 can be reduced, so that the delay when the first clock signal jumps to a low level can be reduced, which results in the turn-on delay of the second transistor T2. Meanwhile, the second pole of the third capacitor C3 is coupled to the first pole of the third capacitor C3 at a low level due to the reduction of the potential, so that the problem of unstable output high level of the light emitting control signal output OUT caused by the misconduction of the tenth transistor T10 is caused, and the output stability of the light emitting control circuit is improved. Fig. 15 is a simulated timing diagram of a light emission control signal corresponding to the light emission control circuit provided in fig. 12. Wherein the abscissa is time, and the ordinate is voltage of the light emission control signal. With reference to fig. 3 and 15, compared with the light emission control signal in fig. 3, the light emission control signal output by the light emission control circuit in the present embodiment is not output erroneously at a low level during a high level period, thereby improving the output stability of the light emission control circuit. Meanwhile, the charging times of the third capacitor C3 by the first clock signal can be reduced, and the power consumption of the light-emitting control circuit is reduced. Illustratively, the average current on the first power signal input terminal VGL in the light emitting control circuit provided by the prior art is 1.01E-06A, and the average current on the second power signal line VL in the light emitting control circuit provided by the embodiment of the invention is 7.66E-07A. It can be seen that, when the load on the first power signal input terminal VGL in the light emitting control circuit provided by the prior art is the same as the load on the second power signal line VL in the light emitting control circuit provided by the embodiment of the present invention, the power consumption on the second power signal line VL in the light emitting control circuit provided by the embodiment of the present invention is relatively small. Similarly, the average current of the second power signal input terminal VGH in the light emitting control circuit provided by the prior art is 9.67E-07A, and the average current of the first power signal line VH in the light emitting control circuit provided by the embodiment of the invention is 7.10E-07A. It can be seen that, when the load on the second power signal input terminal VGH in the light emitting control circuit provided by the prior art is the same as the load on the first power signal line VH in the light emitting control circuit provided by the embodiment of the present invention, the power consumption on the first power signal line VH in the light emitting control circuit provided by the embodiment of the present invention is relatively small. In summary, the power consumption of the light emitting control circuit provided by the embodiment of the invention is relatively low.

In addition, since the delay of the first clock signal jumping from the high level to the low level is relatively small, in the fourth stage T24, when the threshold voltage of the seventh transistor T7 has a negative bias, the first clock signal jumps quickly to the low level to facilitate the seventh transistor T7 to be turned on, thereby reducing the difficulty of turning on the seventh transistor T7 due to the shift of the threshold voltage, so that the seventh transistor T7 is turned on quickly in the fourth stage T24, the first clock signal is transmitted to the gate of the ninth transistor T9, the ninth transistor T9 is controlled to output the first power signal, and the stability of the light emitting control signal output by the light emitting control circuit is improved. Fig. 16 is a simulated timing diagram of the light emission control signal when the threshold voltage of the seventh transistor in the light emission control circuit provided in fig. 12 is negatively biased by 4V. The abscissa is time, and the ordinate is voltage of the light emission control signal. As can be seen from fig. 4 and 16, when the threshold voltage of the seventh transistor T7 is negatively biased by 4V, the emission control signal output terminal OUT can normally output a high level, thereby improving the stability of the emission control signal.

In the fifth phase t25, en is high, ck1 is high, ck2 is low, Vl is low, and Vh is high. The third transistor T3 and the fifth transistor T5 are turned on, and the seventh transistor T7 is turned off. The input signal provided from the input signal line EN is transmitted to the gate of the fourth transistor T4, the gate of the sixth transistor T6, the gate of the tenth transistor T10, and the gate of the first transistor T1 through the third transistor T3, and controls the fourth transistor T4, the sixth transistor T6, the tenth transistor T10, and the first transistor T1 to be turned off. Since the fifth transistor T5 is turned on, the second power signal supplied from the second power signal line VL is transmitted to the gate of the eighth transistor T8, the gate of the eighth transistor T8 is at a low level, the eighth transistor T8 is turned on, and the first clock signal supplied from the first clock signal line CK1 is transmitted to the first pole of the seventh transistor T7 and the gate of the second transistor T2 through the eighth transistor T8. The seventh transistor T7 is turned off and cannot be transmitted to the node 160 through the seventh transistor T7. The node 160 is in a floating state, the second capacitor C2 holds the potential of the node 160 at a previous stage, so that the ninth transistor T9 is turned on, and the light-emitting control signal output terminal OUT outputs the first light-emitting control signal, i.e. a high level. Moreover, the gate of the tenth transistor T10 is an input signal, i.e., high level, the tenth transistor T10 is turned off, and the second power signal provided by the second power signal line VL cannot be transmitted to the light emission control signal output terminal OUT of the light emission control circuit through the tenth transistor T10.

In the sixth phase t26, en is low, ck1 is low, ck2 is high, Vl is low, and Vh is high. The third transistor T3 and the fifth transistor T5 are turned off, and the seventh transistor T7 is turned on. The gate of the eighth transistor T8 is in a floating state at this time. The first capacitor C1 maintains a potential at a first stage on the gate of the eighth transistor T8, the eighth transistor T8 is turned on, the first clock signal provided by the first clock signal line CK1 is transmitted to the gate of the second transistor T2 and the first electrode of the seventh transistor T7 through the eighth transistor T8, the first clock signal is transmitted to the node 160 through the seventh transistor T7, the ninth transistor T9 is controlled to be turned on, and the first power signal provided by the first power signal line VH is transmitted to the light emission control signal output terminal OUT of the light emission control circuit through the ninth transistor T9, so that the first light emission control signal is output as a high level. The gates of the tenth transistor T10 and the first transistor T1 are in a floating state, and the first power signal provided by the first power signal line VH is transmitted to the second electrode of the third capacitor C3 through the second transistor T2, so that the second electrode of the third capacitor C3 is in a high level state, and the first electrode of the third capacitor C3 is coupled to a high level through the coupling effect of the third capacitor C3, so that the tenth transistor T10 is in an off state, and the second power signal provided by the second power signal line VL cannot be transmitted to the light emission control signal output terminal OUT of the light emission control circuit through the tenth transistor T10. In the sixth stage T26, the first clock signal is at a low level, and the first transistor T1 is controlled to be in an off state, so that the gate potential of the tenth transistor T10 is prevented from being pulled down by the first clock signal through the coupling action of the third capacitor C3, the problem of unstable output high level of the light-emitting control signal output OUT caused by the misconduction of the tenth transistor T10 in the sixth stage T26 can be avoided, and the output stability of the light-emitting control circuit is improved. Similarly, the disconnection between the first clock signal line CK1 and the third capacitor C3 can reduce the delay of the first clock signal from high level to low level, thereby reducing the difficulty of turning on the seventh transistor T7, enabling the seventh transistor T7 to be rapidly turned on in the fourth stage T24, transmitting the second clock signal to the gate of the ninth transistor T9, controlling the ninth transistor T9 to output the first light-emitting control signal which is high level, and improving the stability of the light-emitting control signal output by the light-emitting control circuit.

In the seventh phase t27, en is low, ck1 is high, ck2 is low, Vl is low, and Vh is high. The third transistor T3 and the fifth transistor T5 are turned on, and the seventh transistor T7 is turned off. The specific operation process is the same as that of the first stage t21, and is not described here.

Fig. 17 is a schematic structural diagram of another light-emitting control circuit according to an embodiment of the present invention. As shown in fig. 17, the light emission control circuit further includes an eleventh transistor T11 and a twelfth transistor T12; a gate of the eleventh transistor T11 and a gate of the twelfth transistor T12 are electrically connected to the second power supply signal line VL, a second pole of the third transistor T3 is electrically connected to a gate of the tenth transistor T10 through the eleventh transistor T11, and a second pole of the fourth transistor T4 and a second pole of the fifth transistor T5 are electrically connected to a gate of the eighth transistor T8 through the twelfth transistor T12.

In particular, it is exemplarily shown in fig. 17 that the eleventh transistor T11 and the twelfth transistor T12 are P-type transistors. Since the gate of the eleventh transistor T11 and the gate of the twelfth transistor T12 are electrically connected to the second power supply signal line VL, the eleventh transistor T11 and the twelfth transistor T12 are always in a conductive state. The gate of the eighth transistor T8 is electrically connected to the second pole of the fourth transistor T4 through the twelfth transistor T12, so that the gate of the eighth transistor T8 is at a low level, and especially when the gate of the eighth transistor T8 is at a lower level due to the coupling effect of the first capacitor C1, the potential of the second pole of the fourth transistor T4 is lower, and the gate-source voltage difference of the fourth transistor T4 is too large, which may cause the fourth transistor T4 to be damaged. Similarly, the gates of the tenth transistor T10 and the sixth transistor T6 may be electrically connected through the eleventh transistor T11, and when the gate of the tenth transistor T10 is at a low level, and especially when the gate of the tenth transistor T10 is at a lower potential due to the coupling effect of the third capacitor C3, the gate potential of the sixth transistor T6 is lower, and the gate-source voltage difference of the sixth transistor T6 is too large, so that the sixth transistor T6 is prevented from being damaged.

Fig. 18 is a schematic structural diagram of another light-emitting control circuit according to an embodiment of the present invention. As shown in fig. 18, the light emission control circuit further includes a fourth capacitor C4, a first pole of the fourth capacitor C4 is electrically connected to a second pole of the third transistor T3, and a second pole of the fourth capacitor C4 is electrically connected to the second clock signal line CK 2.

Specifically, the fourth capacitor C4 is electrically connected to the second pole of the third transistor T3, and has a stabilizing effect on the potential of the second pole of the third transistor T3. When the second clock signal provided by the first clock signal line CK1 is at a low level and the second clock signal provided by the second clock signal line CK2 is at a high level, the third transistor T3 is in a floating state, the potential of the second pole of the third transistor T3 is at a high level through the coupling action of the fourth capacitor C4 and is transmitted to the gate of the tenth transistor T10 through the eleventh transistor T11, so that the influence of the coupling action of the third capacitor C3 on the tenth transistor T10 at this time is reduced, the gate of the tenth transistor T10 is at a high level, and the tenth transistor T10 is controlled to be turned off, thereby avoiding a screen flicker phenomenon caused by the light emitting control circuit outputting a low level.

In other embodiments, the fourth capacitor C4 may also directly stabilize the potential of the gate of the tenth transistor T10. Fig. 19 is a schematic structural diagram of another light-emitting control circuit according to an embodiment of the present invention. As shown in fig. 19, the light emission control circuit further includes a fourth capacitor C4, a first pole of the fourth capacitor C4 is electrically connected to the gate of the tenth transistor T10, and a second pole of the fourth capacitor C4 is electrically connected to the second power source signal line VL.

Specifically, since the second pole of the fourth capacitor C4 is electrically connected to the second power signal line VL, the coupling effect of the fourth capacitor C4 makes the first pole potential of the fourth capacitor C4 relatively stable, that is, the coupling effect of the fourth capacitor C4 has a stabilizing effect on the tenth transistor T10, so that the influence of the coupling effect of the third capacitor C3 on the gate potential of the tenth transistor T10 is reduced, and the stability of the light emission control signal output by the light emission control circuit is improved.

The embodiment of the invention also provides a light-emitting control driver. Fig. 20 is a schematic structural diagram of a light emission control driver according to an embodiment of the present invention. As shown in fig. 20, the light emission control driver includes at least two stages of light emission control circuits 100, and the at least two stages of light emission control circuits 100 are cascaded.

Specifically, as shown IN fig. 20, the lighting control circuit 100 includes n stages, the lighting control circuit 100 includes an input terminal IN, a first clock signal terminal K1, a second clock signal terminal K2, a high-level input terminal V1, a low-level input terminal V2, and a signal output terminal OUT, the input terminal IN of the first stage lighting control circuit 100 is electrically connected to the initialization signal line EN, and the input terminal IN of the i +1(i is an integer greater than or equal to 1 and less than n) stage lighting control circuit 100 is electrically connected to the output terminal OUT of the previous stage lighting control circuit 100. The first clock signal terminal K1 of the jth-stage light emission control circuit 100 is electrically connected to the first clock signal line CK1, the second clock signal terminal K2 of the jth-stage light emission control circuit 100 is electrically connected to the second clock signal line CK2, the first clock signal terminal K1 of the jth + 1-stage light emission control circuit 100 is electrically connected to the second clock signal line CK2, and the second clock signal terminal K2 of the jth + 1-stage light emission control circuit 100 is electrically connected to the first clock signal line CK 1. Wherein j is an odd or even number greater than or equal to 1 and less than or equal to n. Therefore, the initialization signal of the next-stage light-emitting control circuit 100 is the light-emitting control signal output by the previous-stage light-emitting control circuit 100, and after the previous-stage light-emitting control circuit 100 outputs the light-emitting control signal, the next-stage light-emitting control circuit 100 is started to operate, and then the light-emitting control signal is output, so that the light-emitting control driver is enabled to output the light-emitting control signal step by step, and the high level output by each stage of light-emitting control circuit 100 can be ensured to be stable.

The embodiment of the invention also provides a display panel. Fig. 21 is a schematic structural diagram of a display panel according to an embodiment of the present invention. As shown in fig. 21, the display panel 20 includes a light emission control driver 201 provided in any embodiment of the present invention.

Specifically, the display panel 20 includes a display area 210 and a non-display area 220. The display region 210 includes pixel units (not shown), the light-emitting control driver 201 is disposed in the non-display region 220, and the light-emitting control driver 201 provides light-emitting control signals to the pixel units to control the pixel units to emit light.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A light emission control circuit includes an input unit, a node control unit, a first output unit, a second output unit, and a stabilization unit;

the node control unit is used for outputting a control signal to the first output unit; the first output unit is used for outputting a first light-emitting control signal according to the control signal, and the second output unit is electrically connected with the first clock signal line through the stabilizing unit and used for stably outputting a second light-emitting control signal according to the input signal;

the stabilizing unit includes a first transistor and a second transistor;

2. The light emission control circuit according to claim 1, wherein the input unit includes a third transistor;

3. The light emission control circuit according to claim 2, wherein the node control unit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a first capacitor;

a gate of the fourth transistor is electrically connected to a second pole of the third transistor, a first pole of the fourth transistor is electrically connected to the second clock signal line, a second pole of the fourth transistor is electrically connected to a second pole of the fifth transistor, a gate of the eighth transistor, and a first pole of the first capacitor, a gate of the fifth transistor is electrically connected to the second clock signal line, a first pole of the fifth transistor is electrically connected to a second power signal line, a first pole of the eighth transistor is electrically connected to the first clock signal line, a second pole of the eighth transistor is electrically connected to a second pole of the first capacitor, a first pole of the seventh transistor, and a gate of the second transistor, a gate of the seventh transistor is electrically connected to the first clock signal line, and a second pole of the seventh transistor is electrically connected to a second pole of the sixth transistor, a gate of the sixth transistor is electrically connected to the second pole of the third transistor, and a first pole of the sixth transistor is electrically connected to the first power supply signal line.

4. The light emission control circuit according to claim 3, wherein the first output unit includes a ninth transistor and a second capacitor;

5. The light emission control circuit according to claim 4, wherein the second output unit includes a tenth transistor and a third capacitor;

a gate of the tenth transistor and a first pole of the third capacitor are electrically connected to a second pole of the third transistor, a first pole of the tenth transistor is electrically connected to the second power signal line, and a second pole of the tenth transistor is electrically connected to a second pole of the ninth transistor; a second pole of the third capacitor is electrically coupled to the second pole of the first transistor and the second pole of the second transistor.

6. The light emission control circuit according to claim 5, further comprising an eleventh transistor and a twelfth transistor;

a gate of the eleventh transistor and a gate of the twelfth transistor are electrically connected to the second power supply signal line, a second pole of the third transistor is electrically connected to a gate of the tenth transistor through the eleventh transistor, and a second pole of the fourth transistor and a second pole of the fifth transistor are electrically connected to a gate of the eighth transistor through the twelfth transistor.

7. The lighting control circuit of claim 5, further comprising a fourth capacitor;

8. A lighting control driver comprising at least two stages of lighting control circuits according to any one of claims 1 to 7, the at least two stages of lighting control circuits being cascaded.

9. A display panel comprising the light emission control driver according to claim 8.