CN105720104B - Thin film transistor base plate and preparation method thereof - Google Patents
Thin film transistor base plate and preparation method thereof Download PDFInfo
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- CN105720104B CN105720104B CN201410711179.1A CN201410711179A CN105720104B CN 105720104 B CN105720104 B CN 105720104B CN 201410711179 A CN201410711179 A CN 201410711179A CN 105720104 B CN105720104 B CN 105720104B
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Abstract
The present invention relates to a kind of thin film transistor base plates and preparation method thereof.Thin film transistor base plate of the invention, it includes a substrate, the grid being set in the substrate, the gate insulating layer for covering the grid and the substrate, the active layer for being set on the gate insulating layer and corresponding to above the grid, an etch stop layer, the source electrode on the etch stop layer and a drain electrode and the passivation layer for covering the thin film transistor (TFT), which covers the active layer and the gate insulating layer.Thin film transistor (TFT) of the invention, the thickness of the etch stop layer above the active layer is less than the thickness of the etch stop layer other positions, the problem of can reducing the Terrain Elevation of thin film transistor base plate in this way and reduce rupture of membranes.
Description
Technical field
The present invention relates to a kind of thin film transistor base plates and preparation method thereof.
Background technique
Display has been widely used in each display field, as family, public place, office field and personal electric are related
Product etc..The metal-oxide semiconductor (MOS) being made of zinc oxide, indium gallium zinc (IGZO) etc. is as the active of thin film transistor (TFT)
Layer material, due to its high mobility, low deposition temperature and transparent optical characteristics are considered as follow-on display technology.
In the manufacturing process of metal oxide thin-film transistor substrate, the problems such as to avoid rupture of membranes, etch stop layer is whole
The thickness of body cannot be too thin, however, the etch stop layer thickness above active layer is larger and to will lead to TFT landform too high, may
Lead to substrate surface out-of-flatness and phenomena such as mura easily occurs.
Summary of the invention
The technical issues of to solve rupture of membranes, substrate surface out-of-flatness caused by above-mentioned etch stop layer thickness, it is necessary to mention
The thin film transistor and its manufacturing method for the technical issues of rupture of membranes, substrate surface out-of-flatness can be improved for one kind.
A kind of thin film transistor base plate.The thin film transistor base plate includes substrate, the grid being set in the substrate, covering
The gate insulating layer of the grid and the substrate, loses the active layer for being set on the gate insulating layer and corresponding to above the grid
It carves barrier layer, the source electrode on the etch stop layer and drain electrode and covers a passivation layer of the thin film transistor (TFT), etching resistance
Barrier covers the active layer and the gate insulating layer, which includes first part and second part, the first part
Positioned at the top of the active layer, which is located at at least side of the first part, and is set on the gate insulating layer,
The thickness of the first part is less than the thickness of the second part.
A kind of production method of thin film transistor base plate, includes the following steps:
One substrate is provided, and forms a grid on this substrate；
A gate insulating layer is formed to cover the substrate and the grid；
An active layer is formed on the gate insulating layer and patterns the active layer, makes the position of the active layer face grid
It sets；
Form the etch stop layer of covering gate insulating layer and the active layer；
The etch stop layer is etched, the etch stop layer is formed and is located above the active layer and this is completely covered
The first part of active layer, and the second part positioned at least one side of the first part, the second part are set to the grid
On insulating layer, the thickness of the first part is less than the thickness of the second part；
Source electrode, drain electrode and passivation layer are formed on the etch stop layer after patterning.
Compared to the prior art, thin film transistor base plate provided by the present invention and preparation method thereof, uses gray level mask
The etch stop layer is etched, the thickness for being located at the etch stop layer above the active layer is made to be less than the other positions of the etch stop layer
The thickness set, the problem of the Terrain Elevation of thin film transistor base plate can be reduced in this way and reduce rupture of membranes.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of specific embodiment of the invention thin film transistor base plate.
Fig. 2 is the flow chart of the production method of specific embodiment of the invention thin film transistor base plate.
Fig. 3 to Figure 14 is the section view of each portion's process of production method of specific embodiment of the invention thin film transistor base plate
Figure.
Main element symbol description
The present invention that the following detailed description will be further explained with reference to the above drawings.
Specific embodiment
As shown in Figure 1, for thin film transistor base plate 10 provided by the specific embodiment of the invention.The thin film transistor (TFT) base
Plate 10 includes substrate 11, grid 12, gate insulating layer 13, active layer 14, etch stop layer 15, source electrode 16, drain electrode 17, passivation layer
18 and electrode layer 19.
The grid 12 is arranged in the substrate 11.The gate insulating layer 13 covers the grid 12.The active layer 14 setting exists
Top on the gate insulating layer 13 and positioned at the grid 12.The etch stop layer 15 is layed on the gate insulating layer 13 and covers
Cover the active layer 14.The etch stop layer 15 include first part 151 and second part 152, the first part 151 and this second
Part 152 is connected, which is located on the active layer 14, and the active layer 14, the second part is completely covered
152 are located at the two sides of the first part 151, and cover the gate insulating layer 13 not by the active layer 14 and the first part 151
The separation of the region of covering, the first part 151 and the second part 152 is the etch stop layer 15 along the active layer 14
Edge starts downwards bending place, and the highest point of the highest point of the second part 152 and the first part 151 is in same horizontal line
On, the thickness of the first part 151 is less than the thickness of the second part 152.The position of the corresponding active layer 14 of the first part 151
It sets and offers first through hole 1511 and the second through-hole 1512, the first through hole 1511 and second through-hole 1512 run through the etching
Barrier layer 15 is until expose the active layer 14.The source electrode 16, the drain electrode 17 are arranged on the etch stop layer 15, wherein the source
Pole 16 is electrically connected by the first through hole 1511 and the active layer 14, and the drain electrode 17 is active with this by second through-hole 1512
Layer 14 is electrically connected.The passivation layer 18 covers the source electrode 16, the etch stop layer 15, the drain electrode 17 and the gate insulating layer 13.
The position that the drain electrode 17 is corresponded on the passivation layer 18 offers contact hole 181, and the contact hole 181 is through the passivation layer 18 until sudden and violent
Expose the drain electrode 17.The electrode layer 19 is arranged on the passivation layer 18, and is electrically connected by the contact hole 181 and the drain electrode 17
It connects.It is appreciated that the thin film transistor base plate 10 further includes being formed in the substrate 11 and sweeping with what the grid 12 was electrically connected
The data line (not shown) etc. for retouching line (not shown) and being formed on the gate insulating layer 13 and being electrically connected with the source electrode 16
Structure, this is technology known by those skilled in the art, and details are not described herein.In present embodiment, the etch stop layer 15
Material be preferably photoresist, however, it is not limited to this, and in other embodiments, which also can be selected
Other materials.
In the present embodiment, which is selected from the materials such as metal oxide materials, such as IGZO, IZO or IAZO,
However, it is not limited to this.In other embodiments, which also can be selected other suitable material.
Although above-mentioned be described in detail the structure of the thin film transistor base plate of present embodiment, only use
It to illustrate technical solution of the present invention rather than limits, such as in other embodiments, etch stop layer can not be laying flood
The form of active layer and gate insulating layer is covered, in other embodiments, etch stop layer can be to be only located at corresponding grid
Top and the frame mode for covering active layer.
As shown in Fig. 2, for a kind of production method of thin film transistor base plate 10 provided by the specific embodiment of the invention
Flow chart, please refer to Fig. 3 to Figure 12, this method comprises the following steps:
Step S101 provides substrate 11, and grid 12 is formed in the substrate 11.Specifically, as shown in figure 3, mentioning first
For the substrate 11, and a first metal layer 121 is formed in the substrate 11.The material of the substrate 11 can selected from glass, quartz,
Organic polymer or other transparent materials applicatory.The material of the first metal layer 121 is usually metal material, but can also be with
Use other conductive materials, such as alloy, metal oxide, metal nitride or metal oxynitride etc..Then, such as Fig. 4 institute
Show, the position of the first metal layer 121 to define the grid 12 is patterned using light etching process.In addition, should being formed
While grid 12, the scan line (not shown) being electrically connected with the grid 12 can also be defined simultaneously.
Step S102 forms gate insulating layer 13 to cover substrate 11 and grid 12.Specifically, as shown in figure 5, in the base
Gate insulating layer 13 is deposited on bottom 11 and the grid 12.The material of the gate insulating layer 13 can selected from inorganic material (such as
Silica, silicon nitride and silicon oxynitride etc.), organic material or other materials applicatory and combinations thereof.The gate insulating layer
13 methods formed include plasma activated chemical vapour deposition technique etc..
Step S103, the position of the face grid forms active layer 14 on the gate insulating layer 13.Specifically, firstly,
As shown in fig. 6, depositing a metal oxide layer 141 on the gate insulating layer 13.The material of the metal oxide layer 141, example
It such as can be indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), indium gallium zinc oxide (Indium
Gallium Zinc Oxide, IGZO), indium-zinc oxide (Indium Zinc Oxide, IZO), gallium zinc oxide (Gallium
Zinc Oxide, GZO), zinc tin oxide (Zinc Tin Oxide, ZTO) or zinc oxide (Zinc Oxide, ZnO) etc..So
Afterwards, as shown in fig. 7, patterning the metal oxide layer 141 using etch process, with the face above the gate insulating layer 13
The position of the grid 12 forms the active layer 14.
Step S104 forms an etch stop layer 15 of covering gate insulating layer 13 and the active layer 14, to the etching
Barrier layer 15 carries out pattern etched, hinders the thickness for the etch stop layer 15 for being located at 14 top of active layer less than the etching
The thickness of 15 other parts of barrier.Specifically, as shown in figure 8, being formed on the gate insulating layer 13 and the active layer 14 first
The etch stop layer 15.Then, development is exposed to the etch stop layer 15 using a gray level mask or half rank exposure mask, and schemed
The caseization etch stop layer 15.As shown in figure 9, the etch stop layer 15 after making patterning has first part by etching
151 and second part 152, the first part 151 be located at the surface of the active layer 14, and the active layer 14 is completely covered, should
Second part 152 is located at the side of the first part 151, and cover the gate insulating layer 13 not by the active layer 14 and this first
The region that part 151 covers, the thickness of the first part 151 are less than the thickness of the second part 152, reduce height to reach
Difference, reduce follow-up process in rupture of membranes the problems such as.Meanwhile the etch stop layer 15 is also etched simultaneously by same etching step and is obtained
The first through hole 1511 being arranged on the corresponding grid 12 and second through-hole 1512.In present embodiment, the etch stop layer
15 material is preferably photoresist, therefore directly carries out patterning exposure to the etch stop layer 15 using a gray level mask
Photodevelopment, however, it is not limited to this, and in other embodiments, which can also choose other materials.When this
When the material of etch stop layer 15 is not photoresist, conventional method can be used, as shown in Figure 10, in the etch stop layer 15
It is upper to be first laid with a photoresist layer 154, development then is exposed to the photoresist layer 154 using a gray level mask or half rank exposure mask, then
Pattern etched is carried out to etch stop layer 15, it is as shown in Figure 9 with first part 151 and second part 152 to obtain
The etch stop layer 15.
In present embodiment, which is that flood is laid with and covers the gate insulating layer 13 and the active layer
14, kind structure that however, it is not limited to this.As in other embodiments, the etch stop layer 15 after patterning can be only located at pair
Should grid 12 top and cover the form of the active layer 14, and the etch stop layer 15 after patterning only has covering should
The first part 151 of active layer 14, as shown in figure 11.
Step S105 deposits a second metal layer on the etch stop layer 15 after patterning as shown in Figure 12 and 13
167 and one second photoresist layer 168.Similar with the first metal layer 121, the material of the second metal layer 167 is usually gold
Belong to material, but other conductive materials also can be used, such as alloy, metal oxide, metal nitride or metal oxynitride
Deng.Patterned exposure development is carried out to second photoresist layer 168 and the second metal layer 167 is etched, is obtained
Source electrode 16 and the drain electrode 17 relative to each other, the source electrode 16 and the drain electrode 17 and by the first through hole 1511 and this is second logical
What hole 1512 and the active layer 14 were electrically connected.In addition, can also determine simultaneously while forming the source electrode 16 and drain electrode 17
Justice goes out the data line (not shown) being electrically connected with the source electrode 16.
Step S106, as shown in figure 14, on the source electrode 16 and the drain electrode 17 formed cover the source electrode 16, the drain electrode 17 and
The passivation layer 18 of the etch stop layer 15, and the contact hole is formed in position corresponding with the drain electrode 17 on the passivation layer 18
181, the contact hole 181 is through the passivation layer until the drain electrode 17 is exposed, then in the corresponding drain electrode 17 of the passivation layer 18
Side deposits an electrode layer 19, which is electrically connected by the contact hole 181 and the drain electrode 17.The contact hole 181 can
To be to pattern the passivation layer 18 using light etching process etc. to be formed.The passivation layer 18 can by inorganic material such as silicon nitrides or
The organic materials such as acrylate are formed.The generally transparent conductive material of the material of the electrode layer 19, such as indium tin oxide, indium zinc
Oxide, aluminium zinc oxide, indium oxide or tin oxide etc..
So far, which completes.
Compared to the prior art, thin film transistor base plate provided by the present invention and preparation method thereof, uses gray level mask
The etch stop layer is etched, the thickness for being located at the etch stop layer above the active layer is made to be less than the other positions of the etch stop layer
The thickness set can reduce the Terrain Elevation of thin film transistor base plate in this way, and rupture of membranes is reduced in the case where not influencing production capacity
Problem.
The above examples are only used to illustrate the technical scheme of the present invention and are not limiting, although referring to preferred embodiment to this hair
It is bright to be described in detail, those skilled in the art should understand that, it can modify to technical solution of the present invention
Or equivalent replacement, without departing from the spirit and scope of the technical solution of the present invention.
Claims (12)
1. a kind of thin film transistor base plate comprising substrate, covers the grid and the substrate at the grid being set in the substrate
Gate insulating layer, etch stop layer, is located at the erosion at the active layer for being set on the gate insulating layer and corresponding to above the grid
It carves source electrode and drain electrode on barrier layer and covers a passivation layer of the thin film transistor (TFT), which covers the active layer
And gate insulating layer, which is characterized in that the etch stop layer includes first part and second part, which is located at should
Simultaneously the active layer is completely covered in the top of active layer, which is located at at least side of the first part, and is set to this
On gate insulating layer, the etch stop layer that is demarcated as of the first part and the second part is opened downwards along the edge of the active layer
Beginning bending place, and the highest point of the second part and the highest point of the first part are in same horizontal line, the first part
Thickness be less than the second part thickness.
2. thin film transistor base plate as described in claim 1, which is characterized in that the first part is connected with the second part
It connects.
3. thin film transistor base plate as described in claim 1, which is characterized in that the material of the etch stop layer is photoresist
Agent.
4. thin film transistor base plate as described in claim 1, which is characterized in that the first part corresponds to the position of the active layer
On offer first through hole and the second through-hole, the source electrode and the drain electrode pass through the first through hole and second through-hole respectively to be had with this
Active layer is electrically connected.
5. thin film transistor base plate as described in claim 1, which is characterized in that the thin film transistor (TFT) further includes electrode layer, should
Electrode layer is located on the passivation layer, and passivation layer position corresponding with the drain electrode is also provided with contact hole, which runs through should
Passivation layer is until the exposure drain electrode, the electrode layer are connected by the contact hole with the drain electrode.
6. a kind of production method of thin film transistor (TFT), includes the following steps:
One substrate is provided, and forms a grid on this substrate；
A gate insulating layer is formed to cover the substrate and the grid；
An active layer is formed on the gate insulating layer and patterns the active layer, makes the position of the active layer face grid；
Form the etch stop layer of covering gate insulating layer and the active layer；
The etch stop layer is etched, form the etch stop layer above the active layer and this is completely covered is active
The first part of layer, and the second part positioned at least one side of the first part, the second part are set to the gate insulator
On layer, the etch stop layer that is demarcated as of the first part and the second part starts to bend downwards along the edge of the active layer
Place, the highest point of the second part and the highest point of the first part are in same horizontal line, and the thickness of the first part is small
In the thickness of the second part；
Source electrode, drain electrode and passivation layer are formed on the etch stop layer after patterning.
7. thin film transistor base plate as claimed in claim 6, which is characterized in that the source electrode and the drain electrode are by the etching
A metal layer is deposited on barrier layer and patterns what the metal layer obtained.
8. thin film transistor base plate as claimed in claim 6, which is characterized in that the material of the etch stop layer is photoresist
Agent.
9. thin film transistor base plate as claimed in claim 6, which is characterized in that the first part corresponds to the position of the active layer
On offer first through hole and the second through-hole, the source electrode and the drain electrode pass through the first through hole and second through-hole respectively to be had with this
Active layer is electrically connected.
10. thin film transistor base plate as claimed in claim 6, which is characterized in that after forming the passivation layer, in the passivation layer
Upper position corresponding with the drain electrode opens up a contact hole, and an electrode layer is formed on the passivation layer, which is connect by this
Contact hole is electrically connected with the drain electrode.
11. thin film transistor base plate as claimed in claim 7, which is characterized in that the first part and the second part are logical
It crosses on the etch stop layer and is laid with the first photoresist, then etch stop layer etching is got using gray level mask
's.
12. thin film transistor base plate as claimed in claim 7, which is characterized in that the first part is connected with the second part
It connects.
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| CN201410711179.1A CN105720104B (en) | 2014-12-01 | 2014-12-01 | Thin film transistor base plate and preparation method thereof |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102646684A (en) * | 2012-02-17 | 2012-08-22 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN103578984A (en) * | 2012-07-26 | 2014-02-12 | 瀚宇彩晶股份有限公司 | Semiconductor element and manufacturing method thereof |
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| KR101750381B1 (en) * | 2011-04-06 | 2017-06-26 | 삼성디스플레이 주식회사 | Thin film transistor, organic luminescence display and method of manufacturing thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102646684A (en) * | 2012-02-17 | 2012-08-22 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN103578984A (en) * | 2012-07-26 | 2014-02-12 | 瀚宇彩晶股份有限公司 | Semiconductor element and manufacturing method thereof |
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