CN105720104A - Thin film transistor substrate and manufacturing method thereof - Google Patents
Thin film transistor substrate and manufacturing method thereof Download PDFInfo
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- CN105720104A CN105720104A CN201410711179.1A CN201410711179A CN105720104A CN 105720104 A CN105720104 A CN 105720104A CN 201410711179 A CN201410711179 A CN 201410711179A CN 105720104 A CN105720104 A CN 105720104A
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Abstract
The invention relates to a thin film transistor substrate and a manufacturing method thereof. The thin film transistor substrate comprises a substrate, a gate arranged on the substrate, a gate insulating layer covering the gate and the substrate, an active layer arranged on the gate insulating layer and corresponding to the upper part of the gate, an etching barrier layer, a source and a drain positioned on the etching barrier layer, and a passivation layer covering a thin film transistor, wherein the etching barrier layer covers the active layer and the gate insulating layer. According to the thin film transistor, the etching barrier layer above the active layer is thinner than that at other positions, so that the altitude of the thin film transistor substrate can be reduced and the problem of film breakage can be solved.
Description
Technical field
The present invention relates to a kind of thin film transistor base plate and preparation method thereof.
Background technology
Display is now widely used to each display field, such as family, public place, office field and personal electric Related product etc..The metal-oxide semiconductor (MOS) being made up of zinc oxide, indium gallium zinc (IGZO) etc. is as the active layer material of thin film transistor (TFT), owing to its high mobility, low deposition temperature and transparent optical characteristics are considered follow-on Display Technique.
In the manufacturing process of metal oxide thin-film transistor substrate, for avoiding rupture of membranes etc., the thickness of etch stop layer entirety can not be too thin, but, etch stop layer thickness above active layer can cause that again TFT landform is too high relatively greatly, it is possible to causes that the phenomenons such as mura easily occurs in substrate surface out-of-flatness.
Summary of the invention
For solving rupture of membranes, the irregular technical problem of substrate surface that above-mentioned etch stop layer thickness causes, it is necessary to provide a kind of thin film transistor (TFT) improving rupture of membranes, the irregular technical problem of substrate surface and preparation method thereof.
A kind of thin film transistor base plate.This thin film transistor base plate includes substrate, it is arranged at this suprabasil grid, cover the gate insulator of this grid and this substrate, it is arranged on this gate insulator and corresponding to the active layer above this grid, etch stop layer, it is positioned at the source electrode on this etch stop layer and drain electrode, and cover a passivation layer of this thin film transistor (TFT), this etch stop layer covers this active layer and this gate insulator, this etch stop layer includes Part I and Part II, this Part I is positioned at the top of this active layer, this Part II is positioned at least side of this Part I, and it is arranged on this gate insulator, the thickness of this Part I is less than the thickness of this Part II.
The manufacture method of a kind of thin film transistor base plate, it comprises the steps:
One substrate is provided, and forms a grid on this substrate；
Form a gate insulator to cover this substrate and this grid；
This gate insulator formed an active layer and patterns this active layer, making this active layer just position to this grid；
Form the etch stop layer covering this gate insulator and this active layer；
This etch stop layer is etched, this etch stop layer is made to form the Part I being positioned at above this active layer and being completely covered this active layer, and it is positioned at the Part II at least on one side of this Part I, this Part II is arranged on this gate insulator, and the thickness of this Part I is less than the thickness of this Part II；
This etch stop layer after patterning is formed source electrode, drain electrode and passivation layer.
Compared to prior art, thin film transistor base plate provided by the present invention and preparation method thereof, gray level mask is used to etch this etch stop layer, make the thickness being positioned at this etch stop layer above this active layer thickness less than this other position of etch stop layer, so can reduce the Terrain Elevation of thin film transistor base plate and reduce the problem of rupture of membranes.
Accompanying drawing explanation
Fig. 1 is the structural representation of specific embodiment of the invention thin film transistor base plate.
Fig. 2 is the flow chart of the manufacture method of specific embodiment of the invention thin film transistor base plate.
Fig. 3 to Figure 14 is the sectional view of manufacture method each portion flow process of specific embodiment of the invention thin film transistor base plate.
Main element symbol description
| Thin film transistor base plate | 10 |
| Substrate | 11 |
| Grid | 12 |
| Gate insulator | 13 |
| Active layer | 14 |
| Etch stop layer | 15 |
| Source electrode | 16 |
| Drain electrode | 17 |
| Passivation layer | 18 |
| Part I | 151 |
| Part II | 152 |
| First through hole | 1511 |
| Second through hole | 1512 |
| Electrode layer | 19 |
| Contact hole | 181 |
| The first metal layer | 121 |
| Metal oxide layer | 141 |
| First photoresist | 154 |
| Second metal level | 167 |
| Second photoresist | 168 |
| Contact hole | 181 |
Following detailed description of the invention will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Detailed description of the invention
As it is shown in figure 1, the thin film transistor base plate 10 provided for the specific embodiment of the invention.This thin film transistor base plate 10 includes substrate 11, grid 12, gate insulator 13, active layer 14, etch stop layer 15, source electrode 16, drain electrode 17, passivation layer 18 and electrode layer 19.
This grid 12 is arranged in this substrate 11.This gate insulator 13 covers this grid 12.This active layer 14 is arranged on this gate insulator 13 and is positioned at the top of this grid 12.This etch stop layer 15 is layed on this gate insulator 13 and covers this active layer 14.This etch stop layer 15 includes Part I 151 and Part II 152, this Part I 151 is connected with this Part II 152, this Part I 151 is positioned on this active layer 14, and this active layer 14 is completely covered, this Part II 152 is positioned at the both sides of this Part I 151, and cover the region that this gate insulator 13 is not covered by this active layer 14 and this Part I 151, the separation of this Part I 151 and this Part II 152 is this etch stop layer 15 starts downwards bending place along the edge of this active layer 14, the peak of the peak of this Part II 152 and this Part I 151 is on same level line, the thickness of this Part I 151 is less than the thickness of this Part II 152.This Part I 151 is to offering the first through hole 1511 and the second through hole 1512 on the position of active layer 14, and this first through hole 1511 and this second through hole 1512 run through this etch stop layer 15 until cruelly spilling this active layer 14.This source electrode 16, this drain electrode 17 are arranged on this etch stop layer 15, and wherein this source electrode 16 is electrically connected with this active layer 14 by this first through hole 1511, and this drain electrode 17 is electrically connected with this active layer 14 by this second through hole 1512.This passivation layer 18 covers this source electrode 16, this etch stop layer 15, this drain electrode 17 and this gate insulator 13.On this passivation layer 18 to should drain 17 position offer contact hole 181, this contact hole 181 runs through this passivation layer 18 until sudden and violent this drain electrode 17 of leak.This electrode layer 19 is arranged on this passivation layer 18, and is electrically connected with this drain electrode 17 by this contact hole 181.It is appreciated that, this thin film transistor base plate 10 also includes being formed in this substrate 11 and the scanning line (not shown) that is electrically connected with this grid 12 and the structure such as data wire (not shown) being formed on this gate insulator 13 and being electrically connected with this source electrode 16, this technology known by those skilled in the art, does not repeat them here.In present embodiment, the material of this etch stop layer 15 is preferably photoresist, but is not limited thereto, and in other embodiments, this etch stop layer 15 also can be selected for other materials.
In the present embodiment, this active layer 14 is selected from metal oxide materials, for instance the materials such as IGZO, IZO or IAZO, but is not limited thereto.In other embodiments, this active layer also can be selected for other material being suitable for.
The structure of the thin film transistor base plate of present embodiment is described in detail although above-mentioned, but only in order to technical scheme to be described and unrestricted, as in other embodiments, etch stop layer can not be lay flood to be coated with the form of active layer and gate insulator, in other embodiments, etch stop layer can be the frame mode being only located at above corresponding grid and being coated with active layer.
As in figure 2 it is shown, the flow chart of the manufacture method of a kind of thin film transistor base plate 10 provided for the specific embodiment of the invention, please refer to Fig. 3 to Figure 12, the method comprises the steps:
Step S101, it is provided that substrate 11, and in this substrate 11, form grid 12.Specifically, as it is shown on figure 3, first provide this substrate 11, and in this substrate 11, a first metal layer 121 is formed.The material of this substrate 11 can be selected from glass, quartz, organic polymer or other transparent material applicatory.The material of this first metal layer 121 is generally metal material but it also may use other conductive material, for instance alloy, metal-oxide, metal nitride or metal oxynitride etc..Then, as shown in Figure 4, utilize light etching process to pattern this first metal layer 121 to define the position of this grid 12.It addition, formed this grid 12 it is also possible to define simultaneously and this grid 12 be electrically connected scanning line (not shown).
Step S102, forms gate insulator 13 to cover substrate 11 and grid 12.Specifically, as it is shown in figure 5, in this substrate 11 with this grid 12 deposition of gate insulating barrier 13.The material of described gate insulator 13 can be selected from inorganic material (such as silicon oxide, silicon nitride and silicon oxynitride etc.), organic material or other material applicatory and combination thereof.The method that this gate insulator 13 is formed includes plasma activated chemical vapour deposition technique etc..
Step S103, is just formed with active layer 14 to the position of this grid on this gate insulator 13.Specifically, first, as shown in Figure 6, this gate insulator 13 deposits a metal oxide layer 141.The material of this metal oxide layer 141, can be such as indium gallium zinc oxide (IndiumGalliumZincOxide, IGZO), indium gallium zinc oxide (IndiumGalliumZincOxide, IGZO), indium-zinc oxide (IndiumZincOxide, IZO), gallium zinc oxide (GalliumZincOxide, GZO), zinc tin oxide (ZincTinOxide, ZTO), or zinc oxide (ZincOxide, ZnO) etc..Then, as it is shown in fig. 7, utilize etch process to pattern this metal oxide layer 141, form this active layer 14 with the position to this grid 12 upright on this gate insulator 13.
Step S104, form the etch stop layer 15 covering this gate insulator 13 and this active layer 14, this etch stop layer 15 is patterned etching, makes the thickness being positioned at this etch stop layer 15 above this active layer 14 thickness less than these etch stop layer 15 other parts.Specifically, as shown in Figure 8, first on this gate insulator 13 and this active layer 14, this etch stop layer 15 is formed.Then, utilize a gray level mask or half rank mask that this etch stop layer 15 is exposed development, and pattern this etch stop layer 15.As shown in Figure 9, by etching, this etch stop layer 15 after patterning is made to have Part I 151 and Part II 152, this Part I 151 is positioned at the surface of this active layer 14, and this active layer 14 is completely covered, this Part II 152 is positioned at the side of this Part I 151, and cover the region that this gate insulator 13 is not covered by this active layer 14 and this Part I 151, the thickness of this Part I 151 is less than the thickness of this Part II 152, to reach to reduce difference in height, reduce in successive process the problems such as rupture of membranes.Meanwhile, this etch stop layer 15 etches also by same etching step simultaneously and obtains this first through hole 1511 that should arrange on grid 12 and this second through hole 1512.In present embodiment, the material of this etch stop layer 15 is preferably photoresist, and therefore this etch stop layer 15 is directly patterned exposure imaging by an available gray level mask, but is not limited thereto, in other embodiments, this etch stop layer 15 can also choose other materials.When the material of this etch stop layer 15 is not photoresist, traditional method can be adopted, as shown in Figure 10, this etch stop layer 15 is first laid a photoresist layer 154, then utilize a gray level mask or half rank mask that this photoresist layer 154 is exposed development, etch stop layer 15 is patterned etching again, to obtain this etch stop layer 15 with Part I 151 and Part II 152 as shown in Figure 9.
In present embodiment, this etch stop layer 15 is laid for flood and covers this gate insulator 13 and this active layer 14, but is not limited thereto kind of a structure.As in other embodiments, this etch stop layer 15 after patterning can be only located at should the top of grid 12 cover the form of this active layer 14, and this etch stop layer 15 after patterning only has the Part I 151 covering this active layer 14, as shown in figure 11.
Step S105, as shown in Figure 12 and 13, deposition one second metal level 167 and one second photoresist oxidant layer 168 on this etch stop layer 15 after patterning.Similar with the first metal layer 121, the material of this second metal level 167 is generally metal material but it also may use other conductive material, for instance alloy, metal-oxide, metal nitride or metal oxynitride etc..This second photoresist oxidant layer 168 is patterned exposure imaging and this second metal level 167 is etched, obtain this source electrode 16 relative to each other and this drain electrode 17, this source electrode 16 and this drain electrode 17 and by this first through hole 1511 and this second through hole 1512 and the electric connection of this active layer 14.It addition, that form this source electrode 16 and this drain electrode 17 it is also possible to define and data wire (not shown) that this source electrode 16 is electrically connected simultaneously.
Step S106, as shown in figure 14, this passivation layer 18 covering this source electrode 16, this drain electrode 17 and this etch stop layer 15 is formed on this source electrode 16 and this drain electrode 17, and the position corresponding with this drain electrode 17 forms this contact hole 181 on this passivation layer 18, this contact hole 181 runs through this passivation layer until sudden and violent this drain electrode 17 of leak, then this passivation layer 18 to should drain 17 side deposit an electrode layer 19, this electrode layer 19 is electrically connected with this drain electrode 17 by this contact hole 181.This contact hole 181 can be utilize light etching process etc. to pattern this passivation layer 18 to be formed.This passivation layer 18 can be formed by organic materials such as inorganic material or acrylate such as silicon nitrides.The generally transparent conductive material of material of this electrode layer 19, for instance indium tin oxide, indium-zinc oxide, aluminum zinc oxide, Indium sesquioxide. or stannum oxide etc..
So far, this thin film transistor base plate 10 completes.
Compared to prior art, thin film transistor base plate provided by the present invention and preparation method thereof, gray level mask is used to etch this etch stop layer, make the thickness being positioned at this etch stop layer above this active layer thickness less than this other position of etch stop layer, so can reduce the Terrain Elevation of thin film transistor base plate, the problem reducing rupture of membranes when not affecting production capacity.
Above example is only in order to illustrate technical scheme and unrestricted, although the present invention being described in detail with reference to preferred embodiment, it will be understood by those within the art that, technical scheme can be modified or equivalent replacement, without deviating from the spirit and scope of technical solution of the present invention.
Claims (12)
1. a thin film transistor base plate, it includes substrate, it is arranged at this suprabasil grid, cover the gate insulator of this grid and this substrate, it is arranged on this gate insulator and corresponding to the active layer above this grid, etch stop layer, it is positioned at the source electrode on this etch stop layer and drain electrode, and cover a passivation layer of this thin film transistor (TFT), this etch stop layer covers this active layer and this gate insulator, it is characterized in that, this etch stop layer includes Part I and Part II, this Part I is positioned at the top of this active layer, this Part II is positioned at least side of this Part I, and it is arranged on this gate insulator, the thickness of this Part I is less than the thickness of this Part II.
2. thin film transistor base plate as claimed in claim 1, it is characterized in that, this Part I is connected with this Part II, this etch stop layer that is demarcated as of this Part I and this Part II starts downwards bending place along the edge of this active layer, and the peak of the peak of this Part II and this Part I is on same level line.
3. thin film transistor base plate as claimed in claim 1, it is characterised in that the material of this etch stop layer is photoresist.
4. thin film transistor base plate as claimed in claim 1, it is characterized in that, this Part I is electrically connected with this active layer respectively through this first through hole and this second through hole offering the first through hole and the second through hole, this source electrode and this drain electrode on the position of active layer.
5. thin film transistor base plate as claimed in claim 1, it is characterized in that, this thin film transistor (TFT) also includes electrode layer, this electrode layer is positioned on this passivation layer, the position that this passivation layer is corresponding with this drain electrode is further opened with contact hole, this contact hole runs through this passivation layer until exposing this drain electrode, and this electrode layer is connected with this drain electrode by this contact hole.
6. a manufacture method for thin film transistor (TFT), it comprises the steps:
One substrate is provided, and forms a grid on this substrate；
Form a gate insulator to cover this substrate and this grid；
This gate insulator formed an active layer and patterns this active layer, making this active layer just position to this grid；
Form the etch stop layer covering this gate insulator and this active layer；
This etch stop layer is etched, this etch stop layer is made to form the Part I being positioned at above this active layer and being completely covered this active layer, and it is positioned at the Part II at least on one side of this Part I, this Part II is arranged on this gate insulator, and the thickness of this Part I is less than the thickness of this Part II；
This etch stop layer after patterning is formed source electrode, drain electrode and passivation layer.
7. thin film transistor base plate as claimed in claim 6, it is characterised in that this source electrode and this drain electrode by depositing a metal level and patterning this metal level and obtain on this etch stop layer.
8. thin film transistor base plate as claimed in claim 6, it is characterised in that the material of this etch stop layer is photoresist.
9. thin film transistor base plate as claimed in claim 6, it is characterized in that, this Part I is electrically connected with this active layer respectively through this first through hole and this second through hole offering the first through hole and the second through hole, this source electrode and this drain electrode on the position of active layer.
10. thin film transistor base plate as claimed in claim 6, it is characterized in that, after forming this passivation layer, a contact hole is offered in position corresponding with this drain electrode on this passivation layer, and on this passivation layer, forming an electrode layer, this electrode layer is electrically connected with this drain electrode by this contact hole.
11. thin film transistor base plate as claimed in claim 7, it is characterised in that this Part I and this Part II are by laying the first photoresist on this etch stop layer, then utilize gray level mask that the etching of this etch stop layer is got.
12. thin film transistor base plate as claimed in claim 7, it is characterized in that, this Part I is connected with this Part II, this etch stop layer that is demarcated as of this Part I and this Part II starts downwards bending place along the edge of this active layer, and the peak of this Part II and the peak of this Part I are on same level line.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410711179.1A CN105720104B (en) | 2014-12-01 | 2014-12-01 | Thin film transistor base plate and preparation method thereof |
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| CN201410711179.1A CN105720104B (en) | 2014-12-01 | 2014-12-01 | Thin film transistor base plate and preparation method thereof |
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| CN105720104A true CN105720104A (en) | 2016-06-29 |
| CN105720104B CN105720104B (en) | 2019-01-25 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102646684A (en) * | 2012-02-17 | 2012-08-22 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| US20120256176A1 (en) * | 2011-04-06 | 2012-10-11 | Samsung Mobile Display Co., Ltd. | Thin film transistor, organic luminescence display including the same, and method of manufacturing the organic luminescence display |
| CN103578984A (en) * | 2012-07-26 | 2014-02-12 | 瀚宇彩晶股份有限公司 | Semiconductor element and manufacturing method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120256176A1 (en) * | 2011-04-06 | 2012-10-11 | Samsung Mobile Display Co., Ltd. | Thin film transistor, organic luminescence display including the same, and method of manufacturing the organic luminescence display |
| CN102646684A (en) * | 2012-02-17 | 2012-08-22 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN103578984A (en) * | 2012-07-26 | 2014-02-12 | 瀚宇彩晶股份有限公司 | Semiconductor element and manufacturing method thereof |
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