CN105704945B - A kind of method and device for realizing PCB via hole - Google Patents
A kind of method and device for realizing PCB via hole Download PDFInfo
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- CN105704945B CN105704945B CN201410709956.9A CN201410709956A CN105704945B CN 105704945 B CN105704945 B CN 105704945B CN 201410709956 A CN201410709956 A CN 201410709956A CN 105704945 B CN105704945 B CN 105704945B
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- via hole
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a kind of method and devices for realizing PCB via hole, are related to PCB via hole technical field, and method determines the via hole mode for forming via hole on the pcb the following steps are included: according to the thickness for being laminated PCB that is good and needing layer-exchange hole-through；If identified via hole mode is full plated via mode, by drilling and electroplating processes, the via hole with low conductivity metal layer is formed, on the pcb to reduce quarter-wave resonance point；If identified via hole mode is via hole mode of the plating in conjunction with back drill, then by carrying out back drill processing again after drilling and electroplating processes, forming a part on the pcb has low conductivity metal layer, via hole of the another part without metal layer, to reduce quarter-wave resonance point.The present invention can improve the stub effect of via hole in the case where not back drill or standby drilling depth not enough depth, reduce quarter-wave resonance point.
Description
Technical field
The present invention relates to PCB (Printed Circuit Board, printed circuit board) via hole technical fields, in particular to
A kind of method and device for realizing PCB via hole.
Background technique
It is increasingly various in electronics categories, today that function is become stronger day by day, the density of the core PCB as electronic product
Also increasing, the number of plies is also more and more.It is that not can avoid that layer-exchange hole-through is used for the signal on complicated multi-layer PCB
's.Meanwhile the upper signal bandwidth of PCB comes into the field Gigahertz, and with the extension of signal bandwidth, PCB upper conductor channel
Impedance continuity also become more and more important.However, when signal change layer using via hole, useless stub part (Stub)
The impedance that channel can be damaged is continuous, to influence signal integrity.With the raising of frequency, signal quality can be greatly by this
The influence of a little open circuit stubs, caused by quarter-wave resonance point can damage the transmission of high speed signal.Industry is common at present
The method of reduction stub effect include: one kind be to add terminating resistor, capacitor or inductance in difference through hole end, it is another kind of just
It is the method using back drill.Wherein plus the method for terminating resistor will lead to the additional loss of low frequency part, and termination capacitor and electricity
Quarter-wave resonance can be made to click through line displacement for sense but the resonance point still has；Using the advantages of back drill it is obvious that can
With the highly effective Insertion Loss that must improve via hole and return loss, but back drill also has its limitation, uses firstly for connector via hole
When back drill, there may be contradictions with back drill depth for remaining hole length, and followed by back drill depth is deeper, and tolerance is bigger, for super
Back drill tolerance for the back drill design of 3mm is crossed to be difficult to control.
Currently, the signal of multi-layer PCB would generally be designed using layer is changed, and Via Design will be used by changing layer, with signal
Stub (Stub) effect of the continuous raising of rate, layer-exchange hole-through will be more and more obvious to influence signal integrity.Usually
In order to reduce the influence of stub effect, we can take via hole back drill technique, but back drill also has certain limitation, example
Such as connector via hole, back drill depth will there are the long matter to guarantee connector crimping in enough holes to connector pin
Amount, but Kong Changyu back drill depth is contradictory, if the hole that need to retain is longer, back drill is just unable to satisfy corresponding residual
Stake constraint requirements；If having again be exactly back drill depth is more than 3mm, producer not can guarantee the machining accuracy of back drill, this for 3mm with
On back plate design for be very unfavorable.
During studying this method, at least there are the following problems for the discovery prior art:
1, using the method for terminating resistor, the DC (Direct Current, direct current) in channel can be made to be lost excessive, and used
Termination capacitor, the method for inductance cannot eliminate the point of quarter-wave resonance caused by via hole stub and can only make these resonance points
It is deviated；
2, when via hole uses back drill, back drill is deeper, and back drill tolerance is bigger, and Stub control is poorer, and plate thickness is more than tolerance after 3mm
It is difficult to control；
3, when the connector via hole of back board system uses back drill, there may be contradictions with back drill depth for remaining hole length.
To solve the above problems, the present invention provides a kind of method and devices for realizing PCB via hole.
Summary of the invention
The purpose of the present invention is to provide a kind of method and devices for realizing PCB via hole, solve and change layer in the prior art
The problem of stub effects signal integrity of via hole.
According to an aspect of the invention, there is provided a kind of method for realizing PCB via hole, comprising the following steps:
According to the thickness for being laminated PCB that is good and needing layer-exchange hole-through, the via hole side for forming via hole on the pcb is determined
Formula；
If identified via hole mode is full plated via mode, pass through drilling and electroplating processes, on the pcb shape
At the via hole with low conductivity metal layer, to reduce quarter-wave resonance point；
If identified via hole mode is via hole mode of the plating with back drill ining conjunction with, by drill with after electroplating processes again
Carry out back drill processing, on the pcb formed a part have low conductivity metal layer, via hole of the another part without metal layer,
To reduce quarter-wave resonance point.
Preferably, described by drilling and electroplating processes, the via hole with low conductivity metal layer is formed on the pcb
Include:
It drills on the PCB for need layer-exchange hole-through, forms via hole；
One layer of low conductivity metal is electroplated to via hole is formed by, makes to be formed on the pcb with low conductivity metal
The via hole of layer.
Preferably, described by carrying out back drill processing again after drilling and electroplating processes, a part tool is formed on the pcb
There is low conductivity metal layer, via hole of the another part without metal layer includes:
It drills on the PCB for need layer-exchange hole-through, forms via hole；
One layer of low conductivity metal is electroplated to via hole is formed by, makes to be formed on the pcb with low conductivity metal
The via hole of layer.
Back drill processing is carried out on forming the via hole with low conductivity metal layer, makes the mistake formed on the pcb
Hole a part has low conductivity metal layer, and another part is without metal layer.
Preferably, the thickness according to the PCB that lamination is good and needs layer-exchange hole-through, determination were formed on the pcb
The via hole mode in hole includes:
If the thickness of the PCB is no more than the preset thickness threshold value of PCB, it is determined that via hole mode on the pcb is
Full plated via mode；
If the thickness of the PCB is greater than the preset thickness threshold value of PCB, it is determined that via hole mode on the pcb is electricity
Plate the via hole mode in conjunction with back drill.
Preferably, the back drill includes from the downward back drill of top layer and from bottom-up back drill, and the low conductivity is golden
Belong to is that conductivity is lower than 5.8*107The metal of S/m.
According to another aspect of the present invention, a kind of device for realizing PCB via hole is provided, comprising:
Via hole mode module is determined, for determining described according to the thickness for being laminated PCB that is good and needing layer-exchange hole-through
The via hole mode of via hole is formed on PCB；
First via hole mode module, for when identified via hole mode be full plated via mode, then by drilling and
Electroplating processes form the via hole with low conductivity metal layer, on the pcb to reduce quarter-wave resonance point；
Second via hole mode module, for being via hole mode of the plating in conjunction with back drill when identified via hole mode, then
By carrying out back drill processing again after drilling and electroplating processes, forming a part on the pcb has low conductivity metal layer, separately
Via hole of a part without metal layer, to reduce quarter-wave resonance point.
Preferably, the first via hole mode module includes:
Units form via hole for drilling on the PCB for need layer-exchange hole-through；
Electroplating unit, for via hole one layer of low conductivity metal of plating is formed by, making to be formed on the pcb to have
The via hole of low conductivity metal layer.
Preferably, the second via hole mode module includes:
Units form via hole for drilling on the PCB for need layer-exchange hole-through；
Electroplating unit, for via hole one layer of low conductivity metal of plating is formed by, making to be formed on the pcb to have
The via hole of low conductivity metal layer.
Back drill unit makes for carrying out back drill processing on forming the via hole with low conductivity metal layer described
The via hole a part formed on PCB has low conductivity metal layer, and another part is without metal layer.
Preferably, the determining via hole mode module includes:
First determination unit, the thickness threshold value preset no more than PCB for the thickness as the PCB, it is determined that described
Via hole mode on PCB is full plated via mode；
Second determination unit is greater than the preset thickness threshold value of PCB for the thickness as the PCB, it is determined that in the PCB
On via hole mode be via hole mode of the plating in conjunction with back drill.
Preferably, the back drill includes from the downward back drill of top layer and from bottom-up back drill, and the low conductivity is golden
Belong to is that conductivity is lower than 5.8*107The metal of S/m.
Compared with prior art, the beneficial effects of the present invention are:
The present invention reduces stub Stub to influence to signal integrity bring, enables to a quarter caused by Stub
The depth of wave resonance point is substantially reduced.
Detailed description of the invention
Fig. 1 is a kind of method flow diagram for realizing PCB via hole provided in an embodiment of the present invention；
Fig. 2 is a kind of schematic device for realizing PCB via hole provided in an embodiment of the present invention；
Fig. 3 is PCB lamination pressing schematic diagram provided in an embodiment of the present invention；
Fig. 4 is that the embodiment of the present invention provides PCB drilling schematic diagram；
Fig. 5 is PCB via hole plating low conductivity metal schematic diagram provided in an embodiment of the present invention；
Fig. 6 is that plating low conductivity metal provided in an embodiment of the present invention and bottom-up back drill combine schematic diagram；
Fig. 7 is that three kinds of metal quarter-wave resonance point signals are electroplated in PCB difference through hole provided in an embodiment of the present invention
Figure；
Fig. 8 is PCB blind hole plating low conductivity metal schematic diagram provided in an embodiment of the present invention；
Fig. 9 is PCB buried via hole plating low conductivity metal schematic diagram provided in an embodiment of the present invention；
Figure 10 is the schematic diagram that plating low conductivity metal and the downward back drill of top layer provided in an embodiment of the present invention combine；
Description of symbols: 1- cabling；2- copper foil；3- prepreg；4- drilling；5- drilling plating metal；6- pad；7-
Back drill；8 blind holes；9- buried via hole.
Specific embodiment
Below in conjunction with attached drawing to a preferred embodiment of the present invention will be described in detail, it should be understood that described below is excellent
Select embodiment only for the purpose of illustrating and explaining the present invention and is not intended to limit the present invention.
Fig. 1 shows a kind of method flow diagram for realizing PCB via hole provided in an embodiment of the present invention, as shown in Figure 1, including
Following steps:
Step S101: according to the thickness for being laminated PCB that is good and needing layer-exchange hole-through, determination forms via hole on the pcb
Via hole mode；
Step S102: if identified via hole mode is full plated via mode, by drilling and electroplating processes, in institute
The via hole for being formed on PCB and there is low conductivity metal layer is stated, to reduce quarter-wave resonance point；
Step S103: if identified via hole mode is via hole mode of the plating in conjunction with back drill, pass through drilling and electricity
Back drill processing is carried out after plating again, forming a part on the pcb has low conductivity metal layer, and another part is without metal
The via hole of layer, to reduce quarter-wave resonance point.
Wherein, described by drilling and electroplating processes, the via hole packet with low conductivity metal layer is formed on the pcb
It includes: drilling on the PCB for need layer-exchange hole-through, form via hole；One layer of low conductivity metal is electroplated to via hole is formed by,
Make to form the via hole with low conductivity metal layer on the pcb.It is described by drilling and electroplating processes after carry out back drill again
Processing, forming a part on the pcb has low conductivity metal layer, and via hole of the another part without metal layer includes: to need
It wants to drill on the PCB of layer-exchange hole-through, forms via hole；One layer of low conductivity metal is electroplated to via hole is formed by, makes in institute
State the via hole for being formed on PCB and there is low conductivity metal layer.It is carried on the back on forming the via hole with low conductivity metal layer
Brill processing, makes the via hole a part formed on the pcb have low conductivity metal layer, another part is without metal layer.
Thickness of the present invention according to the PCB that lamination is good and needs layer-exchange hole-through, determination form via hole on the pcb
If via hole mode include: the thickness of the PCB no more than the preset thickness threshold value of PCB, it is determined that via hole on the pcb
Mode is full plated via mode；If the thickness of the PCB is greater than the preset thickness threshold value of PCB, it is determined that on the pcb
Via hole mode is via hole mode of the plating in conjunction with back drill.
The back drill includes from the downward back drill of top layer and from bottom-up back drill, and the low conductivity metal is conductance
Rate is lower than 5.8*107The metal of S/m.
Fig. 2 shows a kind of schematic device for realizing PCB via hole provided in an embodiment of the present invention, as shown in Fig. 2, packet
It includes: determining via hole mode module 201, the first via hole mode module 202 and the second via hole mode module 203.Wherein, described true
Via hole mode module 201 is determined, for according to the thickness for being laminated PCB that is good and needing layer-exchange hole-through, determination to be formed on the pcb
The via hole mode of via hole；The first via hole mode module 202, for being full plated via side when identified via hole mode
Formula forms the via hole with low conductivity metal layer, on the pcb then by drilling and electroplating processes to reduce by four points
One of wave resonance point；The second via hole mode module 203, for being plating in conjunction with back drill when identified via hole mode
Via hole mode, then by drilling and electroplating processes after carry out back drill processing again, on the pcb formed a part have low electricity
Conductivity metal layer, via hole of the another part without metal layer, to reduce quarter-wave resonance point.
Specifically, the determining via hole mode module 201 includes: the first determination unit, for working as the thickness of the PCB
The thickness threshold value preset no more than PCB, it is determined that via hole mode on the pcb is full plated via mode；Second determines
Unit is greater than the preset thickness threshold value of PCB for the thickness as the PCB, it is determined that via hole mode on the pcb is electricity
Plate the via hole mode in conjunction with back drill.The first via hole mode module 202 includes: units, for needing to change a layer mistake
It drills on the PCB in hole, forms via hole；Electroplating unit, for making to via hole one layer of low conductivity metal of plating is formed by
The via hole with low conductivity metal layer is formed on the pcb.The second via hole mode module 203 includes: units,
For drilling on the PCB for need layer-exchange hole-through, via hole is formed；Electroplating unit, for be formed by via hole plating one
Layer low conductivity metal, makes to form the via hole with low conductivity metal layer on the pcb.Back drill unit, in institute's shape
At back drill processing is carried out on the via hole with low conductivity metal layer, there is the via hole a part formed on the pcb low
Conductivity metal layer, another part is without metal layer.
Back drill of the present invention includes from the downward back drill of top layer and from bottom-up back drill, the low conductivity metal
It is lower than 5.8*10 for conductivity7The metal of S/m.
The content that the present invention completes the processing of PCB via hole is illustrated below with reference to Fig. 3 to Fig. 6, is included the following steps:
Step S01: relevant prepreg pp is first chosen according to demand and substrate core is laminated.
When doing multi-layer board, it is superimposed prepreg 3 respectively on a substrate, is superimposed copper foil 2, root again on prepreg 3
After setting cabling 1 according to demand, the PCB for choosing relevant prepreg 3 and substrate is laminated, as shown in Figure 3.
Step S02: it drills on the PCB being laminated.
Drilling operation is carried out to the PCB being laminated, forms drilling 4 as shown in Figure 4.
Step S03: being electroplated the drilling on PCB, and plating metal selects conductivity lower than the metal of copper.
Electroplating operations are carried out to the drilling on the PCB in Fig. 4, plating metal is the metal that conductivity is lower than copper, is formed
Drilling plating metal 5 as shown in Figure 5, and pad 6 is formed by PCB.
Step S04:, can be using back drill and plating if back drill depth is greater than 3mm for the especially thick PCB of plate thickness
The mode that low conductivity metal phase combines ignores this step if plate thickness is lower than 3mm.
It pair, can be using back drill by the way of being electroplated in conjunction with low conductivity metal phase, i.e., if back drill depth is greater than 3mm
It is formed by via hole and one layer of low conductivity metal is electroplated, make to form the via hole with low conductivity metal layer on the pcb,
It is formed and carries out back drill processing on the via hole with low conductivity metal layer, have the via hole a part formed on the pcb
There is low conductivity metal layer, another part is without metal layer.The back drill with plating low conductivity metal phase in conjunction with mode include
Mode and top layer back drill side with plating low conductivity metal phase in conjunction with of the bottom back drill in conjunction with plating low conductivity metal phase
Formula.As shown in figs. 6 and 10, Fig. 6 is mode of the bottom back drill in conjunction with plating low conductivity metal phase, and back drill 7 is bottom in figure
The upward back drill of layer, Figure 10 be top layer back drill with the mode that is electroplated in conjunction with low conductivity metal phase, back drill 7 is top layer to lower back in figure
It bores.
Typical 3mm plate thickness, the PCB of Megtron6 plate, pitch of holes 1mm, the difference through hole of diameter 0.25mm, Stub length
100mil, the quarter-wave resonance point in copper facing, nickel plating and plating iron are as shown in Figure 7, it can be seen that, via hole plating
Iron can reduce quarter-wave resonance point 22dB than electro-coppering.
Low conductivity metal plating via hole of the present invention also includes blind hole (Blind Via) and buried via hole other than through-hole
(Buried Via), as shown in Figure 8 and Figure 9, the process sequence of blind hole are to carry out quadratic-layer pressure after completing lamination, drilling and plating
Two symmetrical PCB constructions are grouped together to form blind hole, blind hole 8 as shown in Figure 8, that is to say, that if PCB layer number
If being N, the blind hole of top half is exactly the layer from top layer to N/2, and the blind hole of lower half portion is exactly from+1 layer of (N/2) to bottom.
The process sequence of buried via hole is also to carry out quadratic-layer pressure after completing lamination, drilling and plating, only in the PCB comprising via hole
Upper and lower two sides all increase lamination, buried via hole 9 as shown in Figure 9, and the connection on PCB between any two layers may be implemented in blind hole in principle.
In conclusion the invention proposes the design scheme that high speed signal layer-exchange hole-through uses low conductivity metal plating,
The stub effect of via hole can be improved in the case where not back drill or back drill depth not enough depth.
In conclusion the present invention has following technical effect that
The present invention is continuous come the impedance for improving layer-exchange hole-through lower than the metal of copper using conductivity is electroplated in PCB drilling
Property, reduce influence of the point of quarter-wave resonance caused by stub Stub to channel signal integrality.
Although describing the invention in detail above, but the invention is not restricted to this, those skilled in the art of the present technique
It can be carry out various modifications with principle according to the present invention.Therefore, all to be modified according to made by the principle of the invention, all it should be understood as
Fall into protection scope of the present invention.
Claims (8)
1. a kind of method for realizing PCB via hole, which comprises the following steps:
According to the thickness for being laminated PCB that is good and needing layer-exchange hole-through, the via hole mode for forming via hole on the pcb, tool are determined
If body includes: the thickness of the PCB thickness threshold value preset no more than PCB, it is determined that via hole mode on the pcb is complete
Plated via mode, if the thickness of the PCB is greater than the preset thickness threshold value of PCB, it is determined that via hole mode on the pcb
For the via hole mode in conjunction with back drill is electroplated；
If the via hole mode is confirmed as full plated via mode, by drilling and electroplating processes, formed on the pcb
Via hole with its conductivity lower than the low conductivity metal layer of copper, to reduce quarter-wave resonance point；
If the via hole mode is confirmed as that via hole mode with back drill ining conjunction with is electroplated, by drill with after electroplating processes again into
Row back drill processing, on the pcb formed a part have its conductivity be lower than copper low conductivity metal layer, another part without
The via hole of metal layer, to reduce quarter-wave resonance point.
2. the method according to claim 1, wherein described pass through drilling and electroplating processes, on the pcb shape
Include: at the via hole with low conductivity metal layer
It drills on the PCB for need layer-exchange hole-through, forms via hole；
One layer of low conductivity metal is electroplated to via hole is formed by, makes to be formed on the pcb with low conductivity metal layer
Via hole.
3. according to the method described in claim 2, it is characterized in that, described by being carried out at back drill again after drilling and electroplating processes
Reason, forming a part on the pcb has low conductivity metal layer, and via hole of the another part without metal layer includes:
It drills on the PCB for need layer-exchange hole-through, forms via hole；
One layer of low conductivity metal is electroplated to via hole is formed by, makes to be formed on the pcb with low conductivity metal layer
Via hole；
Back drill processing is carried out on forming the via hole with low conductivity metal layer, makes the via hole one formed on the pcb
Part has low conductivity metal layer, and another part is without metal layer.
4. method according to claim 1 to 3, which is characterized in that the back drill include from the downward back drill of top layer and
From bottom-up back drill.
5. a kind of device for realizing PCB via hole characterized by comprising
Via hole mode module is determined, for determining on the pcb according to the thickness for being laminated PCB that is good and needing layer-exchange hole-through
The via hole mode of via hole is formed, specifically, if the thickness of the PCB is not more than the preset thickness threshold value of PCB, it is determined that described
Via hole mode on PCB is full plated via mode, if the thickness of the PCB is greater than the preset thickness threshold value of PCB, it is determined that
Via hole mode on the PCB is via hole mode of the plating in conjunction with back drill；
First via hole mode module, for passing through drilling and electricity when the via hole mode is confirmed as full plated via mode
Plating, formed has its conductivity lower than the via hole of the low conductivity metal layer of copper on the pcb, so as to reduce by four/
Wave resonance point；
Second via hole mode module, for leading to when the via hole mode is confirmed as that the via hole mode in conjunction with back drill is electroplated
Back drill processing is carried out again after crossing drilling and electroplating processes, and forming a part on the pcb has its conductivity low lower than copper
Conductivity metal layer, via hole of the another part without metal layer, to reduce quarter-wave resonance point.
6. device according to claim 5, which is characterized in that the first via hole mode module includes:
Units form via hole for drilling on the PCB for need layer-exchange hole-through；
Electroplating unit, for making to be formed on the pcb with low electricity to via hole one layer of low conductivity metal of plating is formed by
The via hole of conductivity metal layer.
7. device according to claim 6, which is characterized in that the second via hole mode module includes:
Units form via hole for drilling on the PCB for need layer-exchange hole-through；
Electroplating unit, for making to be formed on the pcb with low electricity to via hole one layer of low conductivity metal of plating is formed by
The via hole of conductivity metal layer；
Back drill unit makes on the pcb for carrying out back drill processing on forming the via hole with low conductivity metal layer
Via hole a part of formation has low conductivity metal layer, and another part is without metal layer.
8. according to any device of claim 5-7, which is characterized in that the back drill include from the downward back drill of top layer and
From bottom-up back drill.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410709956.9A CN105704945B (en) | 2014-11-28 | 2014-11-28 | A kind of method and device for realizing PCB via hole |
| PCT/CN2015/080796 WO2016082518A1 (en) | 2014-11-28 | 2015-06-04 | Method and device for forming via-holes in pcb |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410709956.9A CN105704945B (en) | 2014-11-28 | 2014-11-28 | A kind of method and device for realizing PCB via hole |
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| Publication Number | Publication Date |
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| CN105704945A CN105704945A (en) | 2016-06-22 |
| CN105704945B true CN105704945B (en) | 2019-09-24 |
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| WO (1) | WO2016082518A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108595839B (en) * | 2018-04-25 | 2021-11-02 | 郑州云海信息技术有限公司 | Method and system for generating compression joint back drilling via file based on Cadence skip |
| CN111031709B (en) * | 2019-12-27 | 2020-11-06 | 生益电子股份有限公司 | PCB manufacturing method for realizing multiple networks with same via hole |
| CN113224516A (en) * | 2020-02-04 | 2021-08-06 | 大唐移动通信设备有限公司 | Active antenna array |
| CN112328554B (en) * | 2020-11-23 | 2022-09-13 | 迈普通信技术股份有限公司 | Method and device for generating secondary drilling file, electronic equipment and storage medium |
| US11482802B2 (en) | 2020-12-04 | 2022-10-25 | Cisco Technology, Inc. | High speed traceless interconnect |
| CN114423147B (en) * | 2022-01-21 | 2023-08-15 | 苏州浪潮智能科技有限公司 | Printed circuit board link connection device, method, printed circuit board and equipment |
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| JP3822123B2 (en) * | 2002-03-22 | 2006-09-13 | 三菱電機株式会社 | Multilayer printed wiring board |
| CN102835196A (en) * | 2010-03-31 | 2012-12-19 | 弗莱克斯电子有限责任公司 | Improved backdrilling of multilayer printed circuit boards |
| CN103298259A (en) * | 2012-02-22 | 2013-09-11 | 深南电路有限公司 | Drilling technology eliminating high-speed backboard noise |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105704945A (en) | 2016-06-22 |
| WO2016082518A1 (en) | 2016-06-02 |
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