CN105679705B - The production method of array substrate - Google Patents
The production method of array substrate Download PDFInfo
- Publication number
- CN105679705B CN105679705B CN201610065012.1A CN201610065012A CN105679705B CN 105679705 B CN105679705 B CN 105679705B CN 201610065012 A CN201610065012 A CN 201610065012A CN 105679705 B CN105679705 B CN 105679705B
- Authority
- CN
- China
- Prior art keywords
- layer
- type
- array substrate
- heavily doped
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Abstract
The present invention provides a kind of production method of array substrate, after carrying out a N-type heavy doping to polysilicon layer, p-type heavy doping twice is carried out to polysilicon layer using one of halftone mask processing procedure, using forming N-type lightly doped district in p-type ion pair N-type ion and on the polysilicon layer of NMOS area, both light shield is saved, the cost of manufacture of array substrate is effectively reduced, while the length of N-type lightly doped district can be accurately controlled, ensures that array substrate obtained has good electric property.
Description
Technical field
The present invention relates to display technology field more particularly to a kind of production methods of array substrate.
Background technology
With the development of display technology, the planes such as liquid crystal display (Liquid Crystal Display, LCD) display dress
It sets because having many advantages, such as that high image quality, power saving, fuselage is thin and has a wide range of application, and is widely used in mobile phone, TV, a number
The various consumer electrical products such as word assistant, digital camera, laptop, desktop computer, become the master in display device
Stream.
Liquid crystal display device on existing market is largely backlight liquid crystal display comprising liquid crystal display panel and
Backlight module (backlight module).Usual liquid crystal display panel is brilliant by color film (CF, Color Filter) substrate, film
Body pipe (TFT, Thin Film Transistor) substrate, the liquid crystal being sandwiched between color membrane substrates and thin film transistor base plate (LC,
Liquid Crystal) and sealing glue frame (Sealant) composition.
Low temperature polycrystalline silicon (Low Temperature Poly Silicon, LTPS) is widely used in medium and small electronic product
A kind of LCD technology.The electron mobility of traditional amorphous silicon material about 0.5-1.0cm2/ V.S, and low temperature polycrystalline silicon
Electron mobility up to 30-300cm2/V.S.Therefore, low-temperature polysilicon liquid crystal on silicon displays has high-res, reaction speed
Soon, many advantages, such as high aperture.
CMOS complementary metal-oxide-semiconductor (CMOS) thin film transistor (TFT) includes that P type metal oxide semiconductor (PMOS) are thin
Film transistor and N-type metal-oxide semiconductor (MOS) (NMOS) thin film transistor (TFT).The advantages of cmos tft is can be real
It is difficult to the various circuits realized and system when a kind of in PMOS or NMOS tft is now only used only.It is thin to improve CMOS
The reliability of the hot carrier's effect of film transistor reduces the maximum field strength in raceway groove, and industry is to NMOS tft at present
Mostly use LDD (Lightly Doped Drain, lightly doped district) structure.
As shown in Figs. 1-2, it is a kind of making side of the LDD region of NMOS tft in existing array substrate processing procedure
Method includes the following steps：
Step 1, as shown in Figure 1, provide a substrate 100, buffer layer 120 and polycrystalline are sequentially formed on the substrate 100
Silicon layer 130；Photoresist layer 140 is coated on the polysilicon layer 130, the photoresist layer 140 is exposed using one of light shield,
After development, only retains the part corresponding to 130 intermediate region of the polysilicon layer, be mask with remaining photoresist layer 140, to more
The both ends of crystal silicon layer 130 carry out N-type heavy doping, obtain two N-type heavily doped regions 131 and between two N-type heavily doped regions 131
Undoped with region 132；
Step 2, as shown in Fig. 2, on the polysilicon layer 130 deposit gate insulating layer 150, in the gate insulating layer
A metal layer is deposited on 150, processing is patterned to the metal layer by one of lithographic process, obtains corresponding to polysilicon
The grid 160 of 132 top of undoped region of layer 130, and the width of the grid 160 is less than the undoped region 132
Width is mask with the grid 160, and carrying out N-type to the both ends in the undoped region 132 of polysilicon layer 130 is lightly doped, and obtains
Two N-type lightly doped districts (LDD) 133.
As shown in Figure 3-4, it is the making side of the LDD region of NMOS tft in another existing array substrate processing procedure
Method includes the following steps：
Step 1, as shown in figure 3, provide a substrate 100, buffer layer 120 and polycrystalline are sequentially formed on the substrate 100
Silicon layer 130；Gate insulating layer 150 is deposited on the polysilicon layer 130, and a metal is deposited on the gate insulating layer 150
Layer, processing is patterned by one of lithographic process to the metal layer, obtains the intermediate region corresponding to polysilicon layer 130
Grid 160, be mask with the grid 160, N-type heavy doping carried out to the both ends of polysilicon layer 130, it is heavily doped to obtain two N-types
Miscellaneous area 131 and the undoped region 132 between two N-type heavily doped regions 131；
Step 2, as shown in figure 4, etched again to the grid 160, until the width of the grid 160 be less than it is described
The undoped region 132 of polysilicon layer 130, then with the grid 160 be mask, to the undoped area of the polysilicon layer 130
The both ends in domain 132 carry out N-type and are lightly doped, and obtain two N-type lightly doped districts (LDD) 133.
As seen in figs. 5-6, it is the making side of the LDD region of NMOS tft in another existing array substrate processing procedure
Method includes the following steps：
Step 1, as shown in figure 5, provide a substrate 100, buffer layer 120 and polycrystalline are sequentially formed on the substrate 100
Silicon layer 130；Silicon oxide layer 151, silicon nitride layer 152 and metal layer 153 are sequentially depositing on the polysilicon layer 130；
Step 2, as shown in fig. 6, by one lithographic process (including etch process twice) to the metal layer 153 and nitrogen
SiClx layer 152 is patterned processing, obtains grid 160 and patterned silicon nitride layer 152, the patterned silicon nitride
The width of layer 152 is more than grid 160, and both sides exceed both sides a distance of the grid 160, with the grid 160 and
Patterned silicon nitride layer 152 is mask, N-type heavy doping is carried out to the polysilicon layer 130, in the polysilicon layer 130
Both sides form two N-type heavily doped regions 131, by the region of 152 both sides of silicon nitride layer covering in the polysilicon layer 130
Form two N-type lightly doped districts (LDD) 133.
The production method of the LDD region of NMOS tft in three of the above array substrate processing procedure, first method need
One of light shield is mostly used, therefore the cost of manufacture of one of light shield need to be increased so that the production cost of array substrate is higher；Second
Although light shield need not be increased with the third method, it is difficult to accurately control the length of LDD region；Therefore, it is necessary to provide one kind
The production method of array substrate, to solve the technical problem.
Invention content
The purpose of the present invention is to provide a kind of production methods of array substrate, when making the LDD region of NMOS transistor,
Light shield need not be increased, can effectively reduce the cost of manufacture of array substrate, and the length of LDD region can be accurately controlled.
To achieve the above object, the present invention provides a kind of production method of array substrate, includes the following steps：
Step 1 provides a substrate, defines NMOS area and the areas PMOS on the substrate, is deposited on the substrate 10
The first metal layer is patterned processing by lithographic process to the first metal layer, obtains hiding positioned at the first of NMOS area
Photosphere and the second light shield layer positioned at the areas PMOS；
Step 2 forms buffer layer on first light shield layer, the second light shield layer and substrate, sinks on the buffer layer
Product amorphous silicon layer, converts the amorphous silicon layer to polysilicon layer, by lithographic process to described more using low temperature crystallization technique
Crystal silicon layer is patterned processing, obtains the second polysilicon layer positioned at the first polysilicon layer of NMOS area and positioned at the areas PMOS；
Step 3 deposits gate insulating layer on first polysilicon layer, the second polysilicon layer and buffer layer, described
Depositing second metal layer on gate insulating layer is patterned processing to the second metal layer by lithographic process, is divided
First grid and second grid that Dui Yingyu be above the first polysilicon layer and the second polysilicon layer；
It is light shield to the both ends of first polysilicon layer and the second polysilicon layer using the first grid, second grid
Both ends carry out N-type heavy doping, obtain the two first N-type heavily doped regions for being located at first polysilicon layer both sides and difference
The two second N-type heavily doped regions positioned at second polysilicon layer both sides；
Step 4 is coated with photoresist layer on first grid, second grid and gate insulating layer, using a halftone mask pair
The photoresist layer is patterned processing, and the inside that described two first N-type heavily doped regions are corresponded on the photoresist layer forms two
Groove, while corresponding to described two second N-type heavily doped regions on the photoresist layer and forming two first through hole；It is with the photoresist layer
Mask carries out p-type heavy doping to described two second N-type heavily doped regions；
Ashing processing is carried out to the photoresist layer, keeps its thickness thinning, it is logical to make two groove be converted into two second
Hole；Using the photoresist layer as mask, the part to corresponding to two second through-holes on described two first N-type heavily doped regions carries out p-type
Heavy doping passes through the neutralization of p-type ion pair N-type ion so that the subregion is converted into N-type lightly doped district；Simultaneously to described
Two second N-type heavily doped regions carry out p-type heavy doping so that described two second N-type heavily doped regions are after p-type heavy doping twice
It is converted into two p-type heavily doped regions；
Remaining photoresist layer is completely exfoliated using photoresist stripping processing procedure.
Further include following steps：
Step 5 deposits interlayer insulating film on the first grid, second grid and gate insulating layer, passes through optical graving
Journey is patterned processing to the interlayer insulating film and gate insulating layer, obtains being located on described two first N-type heavily doped regions
The first via and the second via above the p-type heavily doped region of side；
Step 6, on the interlayer insulating film deposit third metal layer, by lithographic process to the third metal layer into
Row graphical treatment obtains the first source electrode, the first drain electrode, the second source electrode, the second drain electrode, first source electrode, the first drain electrode point
It is not in contact with two first N-type heavily doped regions by the first via, second source electrode, the second drain electrode pass through the second via respectively
It is in contact with p-type heavily doped region；
Step 7 is formed on first source electrode, the first drain electrode, the second source electrode, the second drain electrode and interlayer insulating film and is put down
Smooth layer is patterned processing by lithographic process to the flatness layer, obtains the third mistake for being located at first drain electrode top
Hole；
Step 8 deposits the first including transparent conducting oxide layer on the flatness layer, saturating to described first by lithographic process
Bright conductive oxide layer is patterned processing, obtains public electrode；
Step 9 deposits passivation protection layer on the public electrode and flatness layer, described in passivation protection layer cladding
Third via on flatness layer is patterned processing by lithographic process to the passivation protection layer later, obtains being located at institute
State the 4th via on the passivation protection layer of third via bottom；
Step 10 deposits the second including transparent conducting oxide layer on the passivation protection layer, by lithographic process to described
Second including transparent conducting oxide layer is patterned processing, obtains pixel electrode, and the pixel electrode passes through the 4th via and
One drain electrode is in contact.
The step 2 further includes：P-type is carried out to first polysilicon layer and the second polysilicon layer to be lightly doped, to realize
To the channel doping of first polysilicon layer and the second polysilicon layer.
In the step 2, the low temperature crystallization technique is quasi-molecule laser annealing method or metal-induced lateral crystallization method.
In the step 3, the width of the first grid and second grid is 6 μm.
In the step 3, the N-type ion being implanted into the N-type heavy doping processing procedure is phosphonium ion.
It is boron that the p-type ion being implanted into processing procedure and the p-type heavy doping processing procedure of the step 4, which is lightly doped, in the p-type of the step 2
Ion.
The step 5 further includes：Dehydrogenation and activation process are carried out to the interlayer insulating film.
Dehydrogenation and activation process are carried out to the interlayer insulating film using rapid thermal anneal process.
The substrate is glass substrate；The first metal layer, second metal layer, third metal layer material be molybdenum, titanium,
One or more heap stack combinations in aluminium, copper；The buffer layer, gate insulating layer, interlayer insulating film and passivation protection layer are
Silicon oxide layer, silicon nitride layer or the composite layer constituted is superimposed with silicon nitride layer by silicon oxide layer；The material of the flatness layer is
Organic photoresist；First including transparent conducting oxide layer, the second including transparent conducting oxide layer material be metal oxide.
Beneficial effects of the present invention：A kind of production method of array substrate provided by the invention, carries out to polysilicon layer
After N-type heavy doping, using one of halftone mask processing procedure to polysilicon layer carry out p-type heavy doping twice, using p-type from
Son both saves light shield, effectively reduces array to forming N-type lightly doped district in N-type ion and on the polysilicon layer of NMOS area
The cost of manufacture of substrate, while it can be accurately controlled the length of N-type lightly doped district, it is good to ensure that array substrate obtained has
Electric property.
For further understanding of the features and technical contents of the present invention, it please refers to below in connection with the detailed of the present invention
Illustrate and attached drawing, however, the drawings only provide reference and explanation, is not intended to limit the present invention.
Description of the drawings
Below in conjunction with the accompanying drawings, it is described in detail by the specific implementation mode to the present invention, technical scheme of the present invention will be made
And other beneficial effects are apparent.
In attached drawing,
Fig. 1-2 is a kind of signal of the production method of the LDD region of NMOS tft in existing array substrate processing procedure
Figure；
Fig. 3-4 is that the production method of the LDD region of NMOS tft is shown in another existing array substrate processing procedure
It is intended to；
Fig. 5-6 is that the production method of the LDD region of NMOS tft in another existing array substrate processing procedure is shown
It is intended to；
Fig. 7 is the schematic diagram of the step 1 of the production method of the array substrate of the present invention；
Fig. 8 is the schematic diagram of the step 2 of the production method of the array substrate of the present invention；
Fig. 9 is the schematic diagram of the step 3 of the production method of the array substrate of the present invention；
Figure 10 A-10C are the schematic diagram of the step 4 of the production method of the array substrate of the present invention；
Figure 11 is the schematic diagram of the step 5 of the production method of the array substrate of the present invention；
Figure 12 is the schematic diagram of the step 6 of the production method of the array substrate of the present invention；
Figure 13 is the schematic diagram of the step 7 of the production method of the array substrate of the present invention；
Figure 14 is the schematic diagram of the step 8 of the production method of the array substrate of the present invention；
Figure 15 is the schematic diagram of the step 9 of the production method of the array substrate of the present invention；
Figure 16 is the schematic diagram of the step 10 of the production method of the array substrate of the present invention.
Specific implementation mode
Further to illustrate the technological means and its effect of the invention taken, below in conjunction with the preferred implementation of the present invention
Example and its attached drawing are described in detail.
Fig. 7-16 is please referred to, the present invention provides a kind of production method of array substrate, includes the following steps：
Step 1, as shown in fig. 7, provide a substrate 10, NMOS area and the areas PMOS are defined on the substrate 10, in institute
It states and deposits the first metal layer on substrate 10, processing is patterned to the first metal layer by lithographic process, is located at
First light shield layer 21 of NMOS area and the second light shield layer 22 positioned at the areas PMOS.
Step 2, as shown in figure 8, forming buffer layer on first light shield layer 21, the second light shield layer 22 and substrate 10
30, the deposition of amorphous silicon layers on the buffer layer 30 converts the amorphous silicon layer to polysilicon layer using low temperature crystallization technique,
Processing is patterned to the polysilicon layer by lithographic process, obtains the first polysilicon layer 40 positioned at NMOS area and position
The second polysilicon layer 90 in the areas PMOS；
P-type is carried out to first polysilicon layer, 40 and second polysilicon layer 90 to be lightly doped, to realize to more than described first
The channel doping (Channel Doping) of crystal silicon layer 40 and the second polysilicon layer 90.
Specifically, the low temperature crystallization technique can be quasi-molecule laser annealing method (Excimer Laser
Annealing, ELA) or metal-induced lateral crystallization method (Metal Induced lateral Crystallization,
MILC) etc..
Specifically, in the step 2, it is boron ion that the p-type ion being implanted into processing procedure, which is lightly doped, in the p-type.
Step 3, as shown in figure 9, being deposited on first polysilicon layer 40, the second polysilicon layer 90 and buffer layer 30
Gate insulating layer 51, the depositing second metal layer on the gate insulating layer 51, by lithographic process to the second metal layer
Be patterned processing, obtain corresponding respectively to the first grid 52 of 90 top of the first polysilicon layer 40 and the second polysilicon layer with
Second grid 93；
With the first grid 52, second grid 93 for both ends and second polycrystalline of the light shield to first polysilicon layer 40
The both ends of silicon layer 90 carry out N-type heavy doping, obtain the two first N-type heavy doping for being located at 40 both sides of the first polysilicon layer
Area 41 and the two second N-type heavily doped regions 92 for being located at 90 both sides of the second polysilicon layer.
Preferably, the first grid 52 and the width of second grid 93 are 6 μm.
Specifically, in the step 2, the N-type ion being implanted into the N-type heavy doping processing procedure is phosphonium ion.
Step 4, as shown in Figure 10 A, be coated with photoresist layer on first grid 52, second grid 93 and gate insulating layer 51
31, processing is patterned to the photoresist layer 31 using a halftoning (Half Tone) light shield, it is right on the photoresist layer 31
It answers the inside of described two first N-type heavily doped regions 41 to form two grooves 32, while corresponding on the photoresist layer 31 described two the
Two N-type heavily doped regions 92 form two first through hole 33；It is mask with the photoresist layer 31, to described two second N-type heavily doped regions
92 carry out p-type heavy doping；
As shown in Figure 10 B, ashing processing is carried out to the photoresist layer 31, keeps its thickness thinning, to make two groove
32 are converted into two second through-holes 34；It is mask with the photoresist layer 31, to corresponding to two on described two first N-type heavily doped regions 41
The part of second through-hole 34 carries out p-type heavy doping, passes through the neutralization of p-type ion pair N-type ion so that the subregion is converted into
N-type lightly doped district (LDD) 43；P-type heavy doping is carried out to described two second N-type heavily doped regions 92 simultaneously so that described two the 2nd N
Type heavily doped region 92 is being converted into two p-type heavily doped regions 91 after p-type heavy doping twice；
As illustrated in figure 10 c, remaining photoresist layer 31 is completely exfoliated using photoresist stripping processing procedure.
Specifically, in the step 3, the p-type ion being implanted into the p-type heavy doping processing procedure is boron ion.
Specifically, the step 4 forms NMOS area by half optical cover process together in conjunction with the processing procedure of p-type heavy doping twice
The p-type heavily doped region 91 in N-type lightly doped district (LDD) 43 and the areas PMOS, both saves light shield, effectively reduces being fabricated to for array substrate
This, while it can be accurately controlled the length of N-type lightly doped district (LDD) 43, ensure that array substrate obtained has good electricity
Performance.
Step 5, as shown in figure 11, deposit interlayer on the first grid 52, second grid 93 and gate insulating layer 51
Insulating layer 53 is patterned processing to the interlayer insulating film 53 and gate insulating layer 51 by lithographic process, is located at
The first via 55 and the second via above the p-type heavily doped region 91 of 41 top of described two first N-type heavily doped regions
95, dehydrogenation and activation process are carried out to the interlayer insulating film 53 later.
Specifically, using rapid thermal anneal process (RTA, Rapid Thermal Annealing) to the layer insulation
Layer 53 carries out dehydrogenation and activation process.
Step 6, as shown in figure 12, the deposition third metal layer on the interlayer insulating film 53, by lithographic process to institute
It states third metal layer and is patterned processing, obtain the first source electrode 61, first the 62, second source electrode 96, second of drain electrode drain electrode 97, institute
It states the first source electrode 61, first drain electrode 62 to be in contact with two first N-type heavily doped regions 41 by the first via 55 respectively, described second
The drain electrode of source electrode 96, second 97 is in contact by the second via 95 with p-type heavily doped region 91 respectively.
Step 7, as shown in figure 13, first source electrode 61, first drain the 62, second source electrode 96, second drain electrode 97 and
Flatness layer 70 is formed on interlayer insulating film 53, and processing is patterned to the flatness layer 70 by lithographic process, is located at
The third via 71 of first drain electrode, 62 top.
Step 8, as shown in figure 14, the first including transparent conducting oxide layer is deposited on the flatness layer 70, passes through optical graving
Journey is patterned processing to first including transparent conducting oxide layer, obtains public electrode 80.
Step 9, as shown in figure 15, deposits passivation protection layer 81 on the public electrode 80 and flatness layer 70, described blunt
Change protective layer 81 coat the third via 71 on the flatness layer 70, later by lithographic process to the passivation protection layer 81 into
Row graphical treatment obtains the 4th via 85 on the passivation protection layer 81 of 71 bottom of third via.
Step 10, as shown in figure 16, deposit the second including transparent conducting oxide layer on the passivation protection layer 81, pass through light
It scribes journey and processing is patterned to second including transparent conducting oxide layer, obtain pixel electrode 82, the pixel electrode 82
It is in contact with the first drain electrode 62 by the 4th via 85.
Specifically, the substrate 10 is transparent substrate, preferably glass substrate.
Specifically, the material of the first metal layer, second metal layer, third metal layer is molybdenum (Mo), titanium (Ti), aluminium
(Al), one or more heap stack combinations in copper (Cu).
Specifically, the buffer layer 30, gate insulating layer 51, interlayer insulating film 53 and passivation protection layer 81 are silica
(SiOx) layer, silicon nitride (SiNx) layer or the composite layer constituted is superimposed with silicon nitride layer by silicon oxide layer.
Specifically, the material of the flatness layer 70 is organic photoresist.
Specifically, the equal material of first including transparent conducting oxide layer and the second including transparent conducting oxide layer is metal
Oxide, such as indium tin oxide, indium-zinc oxide, aluminium tin-oxide, aluminium zinc oxide, indium germanium zinc oxide or other suitable
Oxide.
In conclusion a kind of production method of array substrate provided by the invention, a N-type weight is being carried out to polysilicon layer
After doping, using one of halftone mask processing procedure to polysilicon layer carry out p-type heavy doping twice, using p-type ion pair N-type from
N-type lightly doped district is formed in son and on the polysilicon layer of NMOS area, both saves light shield, effectively reduces the making of array substrate
Cost, while it can be accurately controlled the length of N-type lightly doped district, ensure that array substrate obtained has good electric property.
The above for those of ordinary skill in the art can according to the technique and scheme of the present invention and technology
Other various corresponding change and deformations are made in design, and all these change and distortions should all belong to the claims in the present invention
Protection domain.
Claims (10)
1. a kind of production method of array substrate, which is characterized in that include the following steps：
Step 1 provides a substrate (10), NMOS area and the areas PMOS is defined on the substrate (10), on the substrate 10
The first metal layer is deposited, processing is patterned to the first metal layer by lithographic process, obtains being located at the of NMOS area
One light shield layer (21) and the second light shield layer (22) positioned at the areas PMOS；
Step 2 forms buffer layer (30) on first light shield layer (21), the second light shield layer (22) and substrate (10), in institute
Deposition of amorphous silicon layers on buffer layer (30) is stated, the amorphous silicon layer is converted by polysilicon layer using low temperature crystallization technique, is passed through
Lithographic process is patterned processing to the polysilicon layer, obtains being located at the first polysilicon layer (40) of NMOS area and be located at
Second polysilicon layer (90) in the areas PMOS；
Step 3 deposits gate insulator on first polysilicon layer (40), the second polysilicon layer (90) and buffer layer (30)
Layer (51), the depositing second metal layer on the gate insulating layer (51) carry out the second metal layer by lithographic process
Graphical treatment obtains corresponding respectively to the first polysilicon layer (40) and the first grid (52) above the second polysilicon layer (90)
With second grid (93)；
It is both ends and more than second of the light shield to first polysilicon layer (40) with the first grid (52), second grid (93)
The both ends of crystal silicon layer (90) carry out N-type heavy doping, obtain two first N-types for being located at the first polysilicon layer (40) both sides
Heavily doped region (41) and the two second N-type heavily doped regions (92) for being located at the second polysilicon layer (90) both sides；
Step 4 is coated with photoresist layer (31) on first grid (52), second grid (93) and gate insulating layer (51), using one
Halftone mask is patterned processing to the photoresist layer (31), and described two first N-types are corresponded on the photoresist layer (31)
The inside of heavily doped region (41) forms two grooves (32), while it is heavily doped to correspond on the photoresist layer (31) described two second N-types
Miscellaneous area (92) forms two first through hole (33)；With the photoresist layer (31) for mask, to described two second N-type heavily doped regions (92)
Carry out p-type heavy doping；
Ashing processing is carried out to the photoresist layer (31), keeps its thickness thinning, to make two groove (32) be converted into two
Two through-holes (34)；It is logical to corresponding to two second on described two first N-type heavily doped regions (41) with the photoresist layer (31) for mask
The part in hole (34) carries out p-type heavy doping, passes through the neutralization of p-type ion pair N-type ion so that the subregion is converted into N-type
Lightly doped district (43)；P-type heavy doping is carried out to described two second N-type heavily doped regions (92) simultaneously so that described two second N-type weights
Doped region (92) is being converted into two p-type heavily doped regions (91) after p-type heavy doping twice；
Remaining photoresist layer (31) is completely exfoliated using photoresist stripping processing procedure.
2. the production method of array substrate as described in claim 1, which is characterized in that further include following steps：
Step 5 deposits interlayer insulating film on the first grid (52), second grid (93) and gate insulating layer (51)
(53), processing is patterned to the interlayer insulating film (53) and gate insulating layer (51) by lithographic process, is located at
The first via (55) above described two first N-type heavily doped regions (41) and the above the p-type heavily doped region (91)
Two vias (95)；
Step 6, on the interlayer insulating film (53) deposit third metal layer, by lithographic process to the third metal layer into
Row graphical treatment, obtain the first source electrode (61), first drain electrode (62), the second source electrode (96), second drain electrode (97), described first
Source electrode (61), the first drain electrode (62) are in contact by the first via (55) with two first N-type heavily doped regions (41) respectively, and described the
Two source electrodes (96), the second drain electrode (97) are in contact by the second via (95) with p-type heavily doped region (91) respectively；
Step 7, first source electrode (61), first drain electrode (62), the second source electrode (96), second drain electrode (97) and interlayer it is exhausted
Flatness layer (70) is formed in edge layer (53), and processing is patterned to the flatness layer (70) by lithographic process, is located at
Third via (71) above first drain electrode (62)；
Step 8 deposits the first including transparent conducting oxide layer on the flatness layer (70), saturating to described first by lithographic process
Bright conductive oxide layer is patterned processing, obtains public electrode (80)；
Step 9 deposits passivation protection layer (81), the passivation protection layer on the public electrode (80) and flatness layer (70)
(81) coat the third via (71) on the flatness layer (70), later by lithographic process to the passivation protection layer (81) into
Row graphical treatment obtains the 4th via (85) on the passivation protection layer (81) of third via (71) bottom；
Step 10 deposits the second including transparent conducting oxide layer on the passivation protection layer (81), by lithographic process to described
Second including transparent conducting oxide layer is patterned processing, obtains pixel electrode (82), and the pixel electrode (82) passes through the 4th
Via (85) is in contact with the first drain electrode (62).
3. the production method of array substrate as described in claim 1, which is characterized in that the step 2 further includes：To described
One polysilicon layer (40) and the second polysilicon layer (90) carry out p-type and are lightly doped, to realize to first polysilicon layer (40) and
The channel doping of second polysilicon layer (90).
4. the production method of array substrate as described in claim 1, which is characterized in that in the step 2, the low temperature crystallization
Technique is quasi-molecule laser annealing method or metal-induced lateral crystallization method.
5. the production method of array substrate as described in claim 1, which is characterized in that in the step 3, the first grid
(52) it is 6 μm with the width of second grid (93).
6. the production method of array substrate as described in claim 1, which is characterized in that in the step 3, the N-type is heavily doped
The N-type ion being implanted into miscellaneous processing procedure is phosphonium ion.
7. the production method of array substrate as claimed in claim 3, which is characterized in that processing procedure is lightly doped in the p-type of the step 2
And the p-type ion being implanted into the p-type heavy doping processing procedure of the step 4 is boron ion.
8. the production method of array substrate as claimed in claim 2, which is characterized in that the step 5 further includes：To the layer
Between insulating layer (53) carry out dehydrogenation and activation process.
9. the production method of array substrate as claimed in claim 8, which is characterized in that using rapid thermal anneal process to described
Interlayer insulating film (53) carries out dehydrogenation and activation process.
10. the production method of array substrate as claimed in claim 2, which is characterized in that the substrate (10) is glass substrate；
The first metal layer, second metal layer, third metal layer material be molybdenum, titanium, aluminium, one or more storehouse groups in copper
It closes；The buffer layer (30), gate insulating layer (51), interlayer insulating film (53) and passivation protection layer (81) are silicon oxide layer, nitrogen
SiClx layer or the composite layer constituted is superimposed with silicon nitride layer by silicon oxide layer；The material of the flatness layer (70) is organic light
Resistance；The material of first including transparent conducting oxide layer and the second including transparent conducting oxide layer is metal oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610065012.1A CN105679705B (en) | 2016-01-29 | 2016-01-29 | The production method of array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610065012.1A CN105679705B (en) | 2016-01-29 | 2016-01-29 | The production method of array substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105679705A CN105679705A (en) | 2016-06-15 |
| CN105679705B true CN105679705B (en) | 2018-10-26 |
Family
ID=56303126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610065012.1A Active CN105679705B (en) | 2016-01-29 | 2016-01-29 | The production method of array substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105679705B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108666272B (en) * | 2017-03-29 | 2020-09-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN108766935B (en) * | 2018-05-30 | 2020-11-06 | 武汉华星光电技术有限公司 | Array substrate, preparation method thereof and display device |
| CN109065499A (en) * | 2018-07-06 | 2018-12-21 | 武汉华星光电半导体显示技术有限公司 | A kind of preparation method and its array substrate of low temperature polycrystalline silicon tft array substrate |
| CN109860107B (en) * | 2019-01-31 | 2021-03-16 | 武汉华星光电半导体显示技术有限公司 | Array substrate and manufacturing method thereof |
| CN110993613A (en) * | 2019-11-27 | 2020-04-10 | 武汉华星光电技术有限公司 | Array substrate and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102683354A (en) * | 2012-03-22 | 2012-09-19 | 京东方科技集团股份有限公司 | Top grid type N-TFT (thin film transistor), array substrate, preparation method of array substrate, and display device |
| CN104701254A (en) * | 2015-03-16 | 2015-06-10 | 深圳市华星光电技术有限公司 | Manufacturing method of low-temperature polycrystalline silicon thin-film transistor array substrate |
| CN105118807A (en) * | 2015-07-29 | 2015-12-02 | 深圳市华星光电技术有限公司 | Low-temperature polycrystalline silicon thin-film transistor and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100721553B1 (en) * | 2004-06-30 | 2007-05-23 | 삼성에스디아이 주식회사 | fabrication method of CMOS TFT and CMOS TFT fabricated using the same |
| KR100793357B1 (en) * | 2005-03-18 | 2008-01-11 | 삼성에스디아이 주식회사 | Thin Film Transitor and Flat Panel Display Device, and Method of fabricating thereof |
-
2016
- 2016-01-29 CN CN201610065012.1A patent/CN105679705B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102683354A (en) * | 2012-03-22 | 2012-09-19 | 京东方科技集团股份有限公司 | Top grid type N-TFT (thin film transistor), array substrate, preparation method of array substrate, and display device |
| CN104701254A (en) * | 2015-03-16 | 2015-06-10 | 深圳市华星光电技术有限公司 | Manufacturing method of low-temperature polycrystalline silicon thin-film transistor array substrate |
| CN105118807A (en) * | 2015-07-29 | 2015-12-02 | 深圳市华星光电技术有限公司 | Low-temperature polycrystalline silicon thin-film transistor and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105679705A (en) | 2016-06-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105552027B (en) | The production method and array substrate of array substrate | |
| CN105489552B (en) | The production method of LTPS array substrates | |
| CN105470197B (en) | The preparation method of low temperature polycrystalline silicon array base palte | |
| US10013124B2 (en) | Array substrate, touch screen, touch display device, and fabrication method thereof | |
| CN105679705B (en) | The production method of array substrate | |
| CN105390451B (en) | The preparation method of low temperature polycrystalline silicon TFT substrate | |
| CN106531692A (en) | Array substrate and preparation method therefor, and display apparatus | |
| CN105702623B (en) | The production method of tft array substrate | |
| US9741752B1 (en) | Method for manufacturing TFT substrate | |
| CN106098699B (en) | A kind of array substrate, its production method, display panel and preparation method thereof | |
| CN105097675A (en) | Array substrate and preparation method thereof | |
| KR20190086587A (en) | Method of making oxide thin film transistor array, and device incorporating the same | |
| CN101540342A (en) | Thin film transistor and display device | |
| US10121883B2 (en) | Manufacturing method of top gate thin-film transistor | |
| CN106449655A (en) | Thin film transistor array substrate and manufacturing method thereof | |
| CN107799466A (en) | TFT substrate and preparation method thereof | |
| CN101740524B (en) | Method for manufacturing thin film transistor array substrate | |
| US10211232B2 (en) | Manufacture method of array substrate and array substrate manufactured by the method | |
| CN108337905A (en) | A kind of array substrate and preparation method thereof, liquid crystal display panel | |
| CN105355593A (en) | TFT substrate manufacturing method and TFT substrate | |
| CN101937875A (en) | Complementary metal-oxide-semiconductor (CMOS) transistor and manufacturing method thereof | |
| KR20120067108A (en) | Array substrate and method of fabricating the same | |
| WO2017096660A1 (en) | Method for preparing thin-film transistor connected with data line , and thin-film transistor | |
| CN112331680A (en) | Array substrate and preparation method thereof | |
| CN105161458A (en) | Manufacturing method for TFT (thin film transistor) substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |