CN105679218A - Time delay circuit and test tool - Google Patents
Time delay circuit and test tool Download PDFInfo
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- CN105679218A CN105679218A CN201610040763.8A CN201610040763A CN105679218A CN 105679218 A CN105679218 A CN 105679218A CN 201610040763 A CN201610040763 A CN 201610040763A CN 105679218 A CN105679218 A CN 105679218A
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- resistance
- signal
- bipolar transistor
- drive circuit
- transistor
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- Engineering & Computer Science (AREA)
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a time delay circuit which is used to delay input signals for preset delay time. The time delay circuit comprises a first resistor, a second resistor, a third resistor, a bipolarity transistor, a field effect transistor (FET) and a capacitor, wherein the first resistor and the second resistor are connected in series between a signal input and a grounding end; a base electrode of the bipolarity transistor is connected with a common point between the first resistor and the second resistor, a collector electrode of the bipolarity transistor is connected with the signal input end via the third resistor, and an emitter electrode of the bipolarity transistor is connected with the grounding end; the capacitor is connected between the base electrode of the bipolarity transistor and the grounding end; and a gate electrode of the FET is connected with the collector electrode of the bipolarity transistor, a source electrode with the signal input end, and a drain electrode with the signal output end. The invention also provides a test tool. ON/OFF of the bipolarity transistor is controlled via the resistance-capacitance network, connection of the FET is further controlled, test signals are delayed, and the cost is reduced.
Description
Technical field
The invention belongs to display apparatus test field, more particularly, to a kind of delay circuit and measurement jig.
Background technology
Liquid crystal indicator (LiquidCrystalDisplay, LCD) possesses the plurality of advantages such as frivolous, energy-conservation, radiationless, has therefore replaced traditional cathode ray tube (CRT) display gradually. Current liquid crystal display is widely used in the electronic equipments such as HD digital TV, desk computer, personal digital assistant (PDA), notebook computer, mobile phone, digital camera.
Liquid crystal indicator includes display panels (LiquidCrystalPanel) and backlight module (BackLightModule). Wherein, display panels is mainly by thin film transistor base plate (also referred to as Array substrate) and colored filter substrate (ColorFilter, CF) combine, and between thin film transistor base plate and colored filter substrate, irrigate liquid crystal and formed. Backlight module for providing sufficient brightness and equally distributed light source for display panels so that it is can normal show image. And liquid crystal indicator is before dispatching from the factory, it is necessary to carry out lighting test, to ensure its quality.
Fig. 1 is the module diagram of the measurement jig of the liquid crystal indicator of prior art, and Fig. 2 illustrates the input signal of this measurement jig and the oscillogram of output signal. As it is shown in figure 1, described measurement jig includes main switch 10, power module 11 and drive circuit chip 12. Wherein, when main switch 10 closes, headend equipment is to measurement jig input voltage, and after the modules in tool to be tested configures complete and entrance steady operation, measurement jig starts output voltage and signal to liquid crystal indicator.
In the past, the requirement of drive circuit chip (IC) the 12 pairs of electrifying timing sequences on same measurement jig is all consistent, therefore when opening main switch 10, generally all IC are powered on simultaneously, then the source electrode malleation VSP of drive circuit chip 12 output, source electrode negative pressure VSN signal electrifying timing sequence consistent (as shown in Figure 2). But electrifying timing sequence is required higher by the IC on measurement jig, electrifying timing sequence exists nonsynchronous situation, as required, source electrode malleation VSP that the drive circuit chip 12 on measurement jig exports is than source electrode negative pressure VSN signal delay certain time.As it is shown on figure 3, we can increase a delay circuit 13 and microcontroller (MicrocontrollerUnit, MCU) 14 at the VSP outfan of drive circuit chip 12, wherein, the time delay of delay circuit 13 is controlled by MCU14. As shown in Figure 4, delay circuit 13 is made up of a bipolar transistor Q1, a field-effect transistor Q2 and a resistance R3, the base stage of bipolar transistor Q1 is connected with MCU14, and colelctor electrode is connected with the VSP outfan of drive circuit chip 12 by resistance R3, and emitter stage is connected with earth terminal; The grid of field-effect transistor Q2 is connected with bipolar transistor Q1 colelctor electrode, and source electrode is connected with the VSP outfan of drive circuit chip 12, and the VSP signal after drain electrode output delay is to display panels; MCU14 whether and then controls time delay by controlling the conducting of bipolar transistor Q1; Fig. 5 shows the schematic diagram of the delay circuit in another measurement jig being the prior art shown in Fig. 3.
Summary of the invention
It is an object of the invention to provide a kind of delay circuit and measurement jig.
According to an aspect of the present invention, a kind of delay circuit is provided, for input signal delay is preset delay time, including the first resistance, the second resistance, the 3rd resistance, bipolar transistor, field-effect transistor and electric capacity, wherein, described first resistance and the second resistant series are connected between signal input part and earth terminal; Common point between the base stage of described bipolar transistor with described first resistance and the second resistance is connected, and colelctor electrode is connected with signal input part by the 3rd resistance, and emitter stage is connected with earth terminal; Electric capacity is connected between the base stage of bipolar transistor and earth terminal; The grid of described field-effect transistor is connected with the colelctor electrode of described bipolar transistor, and source electrode is connected with signal input part, and drain electrode is connected with signal output part.
Preferably, the size of described electric capacity is arranged according to described default delay time.
Preferably, described default delay time is more than 1ms.
According to a further aspect in the invention, it is provided that a kind of measurement jig, for providing test signal to display floater, including: main switch, it is used for controlling main power input; Supply module, described supply module is connected with described main switch; Drive circuit chip, at least includes an input and two outfans, and wherein, described input is connected with described supply module, described outfan output test signal, and wherein, described test signal includes the first test signal and the second test signal; Delay circuit, is connected with one of them outfan of described drive circuit chip and described display floater, is supplied to described display floater for testing default delay time formation the 3rd test signal of signal delay by first; Wherein, another outfan of described drive circuit chip is connected with described display floater, is supplied to described display floater for testing signal by described second; Described delay circuit includes the first resistance, the second resistance, the 3rd resistance, bipolar transistor, field-effect transistor and electric capacity, wherein, described first resistance and the second resistant series are connected between the first output and ground of described drive circuit chip; Common point between the base stage of described bipolar transistor with described first resistance and the second resistance is connected, and colelctor electrode is connected with the first outfan of described drive circuit chip by the 3rd resistance, and emitter stage is connected with earth terminal; Electric capacity is connected between the base stage of bipolar transistor and earth terminal;The grid of described field-effect transistor is connected with the colelctor electrode of described bipolar transistor, and source electrode is connected with the first outfan of described drive circuit chip, and drain electrode is connected with described display floater.
Preferably, the size of described electric capacity is arranged according to described default delay time.
Preferably, described default delay time is more than 1ms.
Delay circuit provided by the invention and measurement jig realize the conducting to bipolar transistor by resistance-capacitance network and turn off control and then the conducting of controlling filed effect transistor, it is achieved the delay of test signal, reduce cost.
Accompanying drawing explanation
By referring to the accompanying drawing description to the embodiment of the present invention, above-mentioned and other purposes of the present invention, feature and advantage will be apparent from, in the accompanying drawings:
Fig. 1 illustrates the module diagram of measurement jig of the prior art;
Fig. 2 illustrates the input signal of the measurement jig shown in Fig. 1 and the oscillogram of output signal;
Fig. 3 illustrates the module diagram of another measurement jig of the prior art;
Fig. 4 illustrates the input signal of the measurement jig shown in Fig. 3 and the oscillogram of output signal;
Fig. 5 illustrates the schematic diagram of the delay circuit in the measurement jig shown in Fig. 3;
Fig. 6 illustrates the schematic diagram of delay circuit according to embodiments of the present invention;
Fig. 7 a illustrates the input signal of delay circuit according to embodiments of the present invention and a kind of oscillogram of output signal;
Fig. 7 b illustrates the input signal of delay circuit according to embodiments of the present invention and the another kind of oscillogram of output signal;
Fig. 8 illustrates the module diagram of measurement jig according to embodiments of the present invention.
Detailed description of the invention
It is more fully described various embodiments of the present invention hereinafter with reference to accompanying drawing. In various figures, identical element adopts same or similar accompanying drawing labelling to represent. For the sake of clarity, the various piece in accompanying drawing is not necessarily to scale.
The present invention can present in a variety of manners, some of them example explained below.
Fig. 6 illustrates the schematic diagram of delay circuit according to embodiments of the present invention. As shown in Figure 6, described delay circuit is for presetting delay time by input signal lag, including the first resistance R1, the second resistance R2, the 3rd resistance R3, bipolar transistor Q1, field-effect transistor Q2 and electric capacity C1.
Wherein, described first resistance R1 and the second resistance R2 is connected in series between signal input part and earth terminal.
In the present embodiment, what this signal input part inputted is the source electrode malleation VSP signal of drive circuit chip offer.
Common point between the base stage of described bipolar transistor Q1 with described first resistance R1 and the second resistance R2 is connected, and colelctor electrode is connected with signal input part by the 3rd resistance R3, and emitter stage is connected with earth terminal.
In the present embodiment, bipolar transistor Q1 is NPN type triode, has cut-in voltage Uon. Electric potential difference U between base stage and emitter stagebe≤UonTime, Ube<Uce, bipolar transistor Q1 is in cut-off state; Work as Ube>UonTime, Ube>Uce, bipolar transistor Q1 is in the conduction state.
Electric capacity C1 is connected between base stage and the earth terminal of bipolar transistor Q1.
In the present embodiment, when bipolar transistor Q1 is in cut-off state, electric current is charged to electric capacity C1 by R1; When electric capacity C1 both end voltage is more than UonTime, i.e. Ube>Uon, now bipolar transistor Q1 conducting.
The grid of described field-effect transistor Q2 is connected with the colelctor electrode of described bipolar transistor Q1, and source electrode is connected with signal input part, and drain electrode is connected with signal output part.
In the present embodiment, field-effect transistor Q2 is P-channel enhancement type MOS transistor, has cut-in voltage UGS(th), wherein, UGS(th)< 0. Work as UGS<UGS(th)Time, field-effect transistor Q2 is in the conduction state; Work as UGS>UGS(th)Time, field-effect transistor Q2 is in cut-off state.
When bipolar transistor Q1 is in cut-off state, the grid voltage U of field-effect transistor Q2GEqual to source voltage US, now, UGS>UGS(th), field-effect transistor Q2 is in cut-off state, and electric current is charged to electric capacity C1 by the first resistance R1, when electric capacity C1 both end voltage is more than UonTime, bipolar transistor Q1 turns on, then the 3rd resistance R3 both end voltage increases, and then causes the grid voltage U of field-effect transistor Q2GLess than source voltage US, work as UGS<UGS(th)Time field-effect transistor Q2 conducting, it is achieved that input signal VSP signal delay.
In a preferred embodiment, the size of described electric capacity C1 is arranged according to described default delay time, and described default delay time is more than 1ms.
In the present embodiment, the first resistance R1=8k Ω, the second resistance R2=4k Ω, the 3rd resistance R3=10k Ω. The input signal of delay circuit according to embodiments of the present invention and a kind of oscillogram of output signal is illustrated such as Fig. 7 a; Work as C1=0.1uF, VSP1 time delay t1=1.4ms; Fig. 7 b illustrates the input signal of delay circuit according to embodiments of the present invention and the another kind of oscillogram of output signal; Work as C1=0.68uF, VSP1 time delay t2=7.6ms. Owing to requiring that Preset Time is more than 1ms, selects C1=0.1uF.
Fig. 8 illustrates the module diagram of measurement jig according to embodiments of the present invention. As shown in Figure 8, described measurement jig is for providing test signal to display floater 20, including main switch 10, supply module 11, drive circuit chip 12 and delay circuit 13.
Wherein, main switch 10 is used for controlling main power input.
Supply module 11 is connected with described main switch 10.
Drive circuit chip 12 at least includes an input and two outfans, and wherein, described input is connected with supply module, described outfan output test signal, and wherein, described test signal includes the first test signal and the second test signal.
In the present embodiment, drive circuit chip 12 includes an input 121 and first outfan the 122, second outfan 123, described input 121 is connected with described supply module 11, first outfan output the first test signal, second outfan output the second test signal. Wherein, described first test signal is source electrode malleation VSP signal, and the second test signal is source electrode negative pressure VSN signal.
Delay circuit 13 is connected with one of them outfan and the described display floater 20 of described drive circuit chip 12, is supplied to described display floater 20 for testing default delay time formation the 3rd test signal of signal delay by first.
In the present embodiment, delay circuit 13 is connected with the first outfan 122 of described drive circuit chip 12, described source electrode malleation VSP signal enters from the signal input part of delay circuit 13, out form the 3rd test signal from the outfan of the signal of delay circuit 13, and described 3rd test signal is supplied to described display floater.
Described delay circuit 13 includes the first resistance R1, the second resistance R2, the 3rd resistance R3, bipolar transistor Q1, field-effect transistor Q2 and electric capacity C1, wherein, described first resistance R1 and the second resistance R2 is connected in series between the first output and ground of described drive circuit chip 12;Common point between the base stage of described bipolar transistor Q1 with described first resistance R1 and the second resistance R2 is connected, and colelctor electrode is connected with the first outfan of described drive circuit chip 12 by the 3rd resistance R3, and emitter stage is connected with earth terminal; Electric capacity C1 is connected between base stage and the earth terminal of bipolar transistor Q1; The grid of described field-effect transistor Q2 is connected with the colelctor electrode of described bipolar transistor Q1, and source electrode is connected with the first outfan of described drive circuit chip 12, and drain electrode is connected with described display floater 20.
When the signal input part of delay circuit has just begun with voltage input, the U of bipolar transistor Q1be≤UonTime, Ube<Uce, bipolar transistor Q1 is in cut-off state, the grid voltage U of field-effect transistor Q2GEqual to source voltage US, now UGS>UGS(th), field-effect transistor Q2 is in cut-off state, and electric current is charged to electric capacity C1 by the first resistance R1, when electric capacity C1 both end voltage is more than UonTime, bipolar transistor Q1 turns on, then the 3rd resistance R3 both end voltage increases, and then causes the grid voltage U of field-effect transistor Q2GLess than source voltage US, now UGS<UGS(th), field-effect transistor Q2 turns on, it is achieved that the signal delay of input signal VSP.
Second outfan 123 of drive circuit chip 12 is connected with described display floater 20, is supplied to described display floater 20 for testing signal by described second.
Delay circuit provided by the invention and measurement jig realize the conducting to bipolar transistor by resistance-capacitance network and turn off control and then the conducting of controlling filed effect transistor, it is achieved the delay of test signal, reduce cost.
According to embodiments of the invention as described above, these embodiments do not have all of details of detailed descriptionthe, are not intended to the specific embodiment that this invention is only described yet. Obviously, as described above, can make many modifications and variations. These embodiments are chosen and specifically described to this specification, is to explain principles of the invention and practical application better, so that skilled artisan can utilize the present invention and the amendment on basis of the present invention to use well. Protection scope of the present invention should be as the criterion with the scope that the claims in the present invention define.
Claims (6)
1. a delay circuit, for input signal delay is preset delay time, including the first resistance, the second resistance, the 3rd resistance, bipolar transistor, field-effect transistor and electric capacity,
Wherein, described first resistance and the second resistant series are connected between signal input part and earth terminal;
Common point between the base stage of described bipolar transistor with described first resistance and the second resistance is connected, and colelctor electrode is connected with signal input part by the 3rd resistance, and emitter stage is connected with earth terminal;
Electric capacity is connected between the base stage of bipolar transistor and earth terminal;
The grid of described field-effect transistor is connected with the colelctor electrode of described bipolar transistor, and source electrode is connected with signal input part, and drain electrode is connected with signal output part.
2. delay circuit according to claim 1, wherein, the size of described electric capacity is arranged according to described default delay time.
3. delay circuit according to claim 1, wherein, described default delay time is more than 1ms.
4. a measurement jig, for providing test signal to display floater, including:
Main switch, is used for controlling main power input;
Supply module, described supply module is connected with described main switch;
Drive circuit chip, at least includes an input and two outfans, and wherein, described input is connected with described supply module, described outfan output test signal, and wherein, described test signal includes the first test signal and the second test signal;
Delay circuit, is connected with one of them outfan of described drive circuit chip and described display floater, is supplied to described display floater for testing default delay time formation the 3rd test signal of signal delay by first;
Wherein, another outfan of described drive circuit chip is connected with described display floater, is supplied to described display floater for testing signal by described second;
Described delay circuit includes the first resistance, the second resistance, the 3rd resistance, bipolar transistor, field-effect transistor and electric capacity,
Wherein, described first resistance and the second resistant series are connected between the first output and ground of described drive circuit chip;
Common point between the base stage of described bipolar transistor with described first resistance and the second resistance is connected, and colelctor electrode is connected with the first outfan of described drive circuit chip by the 3rd resistance, and emitter stage is connected with earth terminal;
Electric capacity is connected between the base stage of bipolar transistor and earth terminal;
The grid of described field-effect transistor is connected with the colelctor electrode of described bipolar transistor, and source electrode is connected with the first outfan of described drive circuit chip, and drain electrode is connected with described display floater.
5. measurement jig according to claim 4, wherein, the size of described electric capacity is arranged according to described default delay time.
6. measurement jig according to claim 4, wherein, described default delay time is more than 1ms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610040763.8A CN105679218A (en) | 2016-01-21 | 2016-01-21 | Time delay circuit and test tool |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610040763.8A CN105679218A (en) | 2016-01-21 | 2016-01-21 | Time delay circuit and test tool |
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| CN105679218A true CN105679218A (en) | 2016-06-15 |
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| CN201610040763.8A Pending CN105679218A (en) | 2016-01-21 | 2016-01-21 | Time delay circuit and test tool |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105762781A (en) * | 2016-04-28 | 2016-07-13 | 昆山龙腾光电有限公司 | Surge current control circuit and power supply device |
| CN108109568A (en) * | 2018-01-10 | 2018-06-01 | 京东方科技集团股份有限公司 | Power supply adjusting circuit and method, test system |
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| CN108109568A (en) * | 2018-01-10 | 2018-06-01 | 京东方科技集团股份有限公司 | Power supply adjusting circuit and method, test system |
| US10796615B2 (en) | 2018-01-10 | 2020-10-06 | Boe Technology Group Co., Ltd. | Circuit and method for regulating power supplying, and test system |
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Application publication date: 20160615 |