CN105675955A

CN105675955A - Voltage detection circuit of zero power consumption

Info

Publication number: CN105675955A
Application number: CN201610039075.XA
Authority: CN
Inventors: 方镜清
Original assignee: ZHONGSHAN XINDA ELECTRONIC TECHNOLOGY Co Ltd
Current assignee: ZHONGSHAN XINDA ELECTRONIC TECHNOLOGY Co Ltd
Priority date: 2016-01-21
Filing date: 2016-01-21
Publication date: 2016-06-15
Anticipated expiration: 2036-01-21
Also published as: CN105675955B

Abstract

The invention discloses a voltage detection circuit of zero power consumption. The detection circuit composed of multiple MOS tubes and a phase-locked loop to detect voltage change of an input power supply, work of the detection circuit is stopped when the power voltage reaches a working power supply of an integrated circuit, and thus, zero power consumption is realized; and a time delay circuit arranged at the input end further satisfies the working requirements when the power supply of the integrated circuit reaches a working voltage.

Description

A kind of zero-power voltage detecting circuit

Technical field

The invention belongs to the voltage detection circuit technical field in unicircuit, especially relate to a kind of zero-power voltage detecting circuit.

Background technology

At present, unicircuit is in the moment of energising, due to the time delay reason of power supply boosting, when voltage of supply does not reach the operating voltage of unicircuit, unicircuit is it is possible to this situation of starting working not only can not ensure the normal operation of unicircuit but also unicircuit can be caused damage, need to arrange one for detecting the circuit of voltage of supply, in the middle of prior art relatively normal adopt as

Circuit structure shown in Fig. 1 carries out judging sampling, and owing to there is voltage on the Vref of circuit all the time, so have watt consumption with unicircuit work always, this causes the waste of resource, and increases and have impact on cost and the use of unicircuit.

Summary of the invention

For solving the deficiencies in the prior art problem, the present invention provides a kind of zero-power voltage detecting circuit, this circuit adopts multiple MOS to manage the detection circuit with phaselocked loop composition to detect the change of input supply voltage, and can stop detecting the work of circuit after voltage of supply reaches the working power of unicircuit, thus reach the function of zero-power; The unicircuit that meets that the time delay circuit of input terminus setting is further reaches, at power supply, the requirement that operating voltage is work.

A kind of zero-power voltage detecting circuit, comprises power input, output terminal, ground terminal and voltage time delay detection circuit, and described detection circuit comprises a MOS pipe, the 2nd MOS pipe, the 3rd MOS pipe, the 4th MOS pipe, the 5th MOS pipe and phase-locked circuit; The grid of the one MOS pipe and the grid junction circuit output terminal of the 4th MOS pipe, a MOS pipe source electrode connects power input, and the drain electrode of a MOS pipe connects the drain electrode pole of the 2nd MOS pipe; The source electrode of the 2nd MOS pipe connects ground terminal, and the grid of the 2nd MOS pipe connects the grid of the 3rd MOS pipe; The source electrode of the 3rd MOS pipe connects ground terminal, and its drain electrode connects the grid of the 5th MOS pipe; The source electrode of the 5th MOS pipe and drain electrode connect power input, and the source electrode of the 4th MOS pipe and drain electrode connect ground terminal; Phase-locked circuit comprises the first phase inverter and the 2nd phase inverter, the input terminus of the first phase inverter and the output terminal of the 2nd phase inverter connect between the grid of the 5th MOS pipe and the drain electrode of the 3rd MOS pipe respectively, between the grid that the output terminal of the first phase inverter and the input terminus of the 2nd phase inverter are connected to a described MOS pipe and the grid of the 4th MOS pipe.

Preferably, a described MOS pipe and described 5th MOS pipe are PMOS, described 2nd MOS pipe,

Described 3rd MOS pipe and described 4th MOS pipe are NMOS tube.

Preferably, being connected with the first standby circuit between the grid of a described MOS pipe and source electrode, first is attached

Add a circuit PMOS at least in parallel.

Preferably, being connected with the 2nd standby circuit between the grid of described 3rd MOS pipe and source electrode, the 2nd is attached

Add the few NMOS tube in parallel of circuit.

Preferably, described output terminal is connected with time delay circuit, and time delay circuit comprises the 3rd phase inverter, the 4th phase inverter and the 5th phase inverter mutually connected.

A kind of zero-power voltage detecting circuit of the present invention adopts multiple MOS to manage the detection circuit with phaselocked loop composition to detect the change of input supply voltage, and can stop detecting the work of circuit after voltage of supply reaches the working power of unicircuit, thus reach the function of zero-power; The unicircuit that meets that the time delay circuit of input terminus setting is further reaches, at power supply, the requirement that operating voltage is work.

Accompanying drawing explanation

Fig. 1 is the schematic circuit of voltage compare sample circuit in prior art.

Fig. 2 is the schematic circuit of the zero-power voltage detecting circuit of the present invention.

Embodiment

As follows by reference to the accompanying drawings, the application's scheme is further described:

As shown in Figure 2, a kind of zero-power voltage detecting circuit, comprising power input Vcc, output end vo ut, ground terminal Vgnd and voltage time delay detection circuit, this detection circuit comprises a MOS pipe N1, the 2nd MOS pipe N2, the 3rd MOS pipe N3, the 4th MOS pipe N4, the 5th MOS pipe N5 and phase-locked circuit.

The grid of the one MOS pipe N1 and the grid junction circuit output end vo ut of the 4th MOS pipe N4, a MOS pipe N1 source electrode connects the drain electrode pole of drain electrode connection the 2nd MOS pipe N2 of power input Vcc, a MOS pipe N1; The source electrode of the 2nd MOS pipe N2 connects the grid of grid connection the 3rd MOS pipe N3 of ground terminal Vgnd, the 2nd MOS pipe N2; The source electrode of the 3rd MOS pipe N3 connects ground terminal Vgnd, and its drain electrode connects the grid of the 5th MOS pipe N5; The source electrode of the 5th MOS pipe N5 and drain electrode connect power input Vcc, and the source electrode of the 4th MOS pipe N4 and drain electrode connect ground terminal Vgnd; A MOS pipe N1 and described 5th MOS pipe N5 in the present embodiment are PMOS, and the 2nd MOS pipe N2, the 3rd MOS pipe N3 and the 4th MOS pipe N4 are NMOS tube.

Phase-locked circuit comprises the first phase inverter D1 and the 2nd phase inverter D2, the input terminus 11 of the first phase inverter D1 and the output terminal 22 of the 2nd phase inverter D2 are connected between the grid of the 5th MOS pipe N5 and the drain electrode of the 3rd MOS pipe N3, between the grid that the output terminal 12 of the first phase inverter D1 and the input terminus 21 of the 2nd phase inverter D2 are connected to a described MOS pipe N1 and the grid of the 4th MOS pipe N4.

Further, in order to prevent the MOS pipe N1 from causing circuit can not work due to fault, the

Being connected with the first standby circuit between the grid of one MOS pipe N1 and source electrode, the first standby circuit PMOS at least in parallel, the first standby circuit in the present embodiment comprises the PMOS N11 and N12 of two series connection.

Further, in order to prevent the 3rd MOS pipe N3 from causing circuit can not work due to fault, institute

Stating and be connected with the 2nd standby circuit between the grid of the 3rd MOS pipe N3 and source electrode, the few NMOS tube in parallel of the 2nd standby circuit, the first standby circuit in the present embodiment comprises the NMOS tube N31 and N32 of two series connection.

Further, in order to meet the requirement that unicircuit works when power supply reaches operating voltage, described output end vo ut is connected with time delay circuit, and time delay circuit comprises the 3rd phase inverter D3, the 4th phase inverter D4 and the 5th phase inverter D5 of series connection mutually.

Above-mentioned preferred implementation should be considered as the illustration of the application's scheme implementation mode, all identical with the application's scheme, approximate or make based on this technology deduction, replacement, improvement etc., the protection domain of this patent all should be considered as.

Claims

1. a zero-power voltage detecting circuit, comprise power input, output terminal, ground terminal and voltage time delay detection circuit, it is characterised in that: described detection circuit comprises a MOS pipe, the 2nd MOS pipe, the 3rd MOS pipe, the 4th MOS pipe, the 5th MOS pipe and phase-locked circuit; The grid of the one MOS pipe and the grid junction circuit output terminal of the 4th MOS pipe, a MOS pipe source electrode connects power input, and the drain electrode of a MOS pipe connects the drain electrode pole of the 2nd MOS pipe; The source electrode of the 2nd MOS pipe connects ground terminal, and the grid of the 2nd MOS pipe connects the grid of the 3rd MOS pipe; The source electrode of the 3rd MOS pipe connects ground terminal, and its drain electrode connects the grid of the 5th MOS pipe; The source electrode of the 5th MOS pipe and drain electrode connect power input, and the source electrode of the 4th MOS pipe and drain electrode connect ground terminal; Phase-locked circuit comprises the first phase inverter and the 2nd phase inverter, the input terminus of the first phase inverter and the output terminal of the 2nd phase inverter connect between the grid of the 5th MOS pipe and the drain electrode of the 3rd MOS pipe respectively, between the grid that the output terminal of the first phase inverter and the input terminus of the 2nd phase inverter are connected to a described MOS pipe and the grid of the 4th MOS pipe.

2. a kind of zero-power voltage detecting circuit according to claim 1, it is characterised in that: described in

One MOS pipe and described 5th MOS pipe are PMOS, and described 2nd MOS pipe, described 3rd MOS pipe and described 4th MOS pipe are NMOS tube.

3. a kind of zero-power voltage detecting circuit according to claim 2, it is characterised in that: described in

It is connected with the first standby circuit, the first standby circuit PMOS at least in parallel between the grid of the one MOS pipe and source electrode.

4. a kind of zero-power voltage detecting circuit according to claim 2, it is characterised in that: described in

The 2nd standby circuit it is connected with, the few NMOS tube in parallel of the 2nd standby circuit between the grid of the 3rd MOS pipe and source electrode.

5. a kind of zero-power voltage detecting circuit according to claim 3 or 4, it is characterised in that: described output terminal is connected with time delay circuit, and time delay circuit comprises the 3rd phase inverter of series connection mutually, the 4th phase inverter and the 5th phase inverter.