CN105634471A - Counter capable of filtering - Google Patents
Counter capable of filtering Download PDFInfo
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- CN105634471A CN105634471A CN201511001553.XA CN201511001553A CN105634471A CN 105634471 A CN105634471 A CN 105634471A CN 201511001553 A CN201511001553 A CN 201511001553A CN 105634471 A CN105634471 A CN 105634471A
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- counter
- etv
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/02—Input circuits
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Abstract
The invention discloses a counter capable of filtering. The counter comprises a bidirectional IO port PAD, a synchronous circuit, a filter circuit and a counter, wherein the bidirectional IO port PAD is successively connected with the synchronous circuit, the filter circuit and the counter. According to the invention, jittering of waveforms during level conversion is filtered, the counter is enabled to work correctly, signal jittering is filtered out, the counter is enabled to count correctly, the program is simplified, and the operation workload of an mcu is reduced.
Description
Technical field
The present invention relates to a kind of counter, specifically a kind of can the counter of filtering.
Background technology
Along with the rapid rising of intelligence household, the integrated independent peripheral counter limitation of conventional one-piece machine central processing unit (mcu) is increasing, limitation is to need a large amount of software programs to go to coordinate counter to carry out work, add the complicacy of software, and occupy the resource of central processing unit, thus reduce the travelling speed of algorithm.
For when using the counting function of counter, owing to external input signal can be shaken when level transitions, cause counter error count number, thus the program having influence on whole system is run, traditional solution needs to add a delay process inside program exactly, causes mcu can not remove the algorithm processing other in time.
Summary of the invention
It is an object of the invention to provide a kind of can the counter of filtering, to solve in above-mentioned background technology the problem proposed.
For achieving the above object, the present invention provides following technical scheme:
Can the counter of filtering, comprise two-way I/O port PAD, synchronous circuit, filtering circuit and counter, described two-way I/O port PAD connects synchronous circuit, filtering circuit and counter successively.
As the scheme that the present invention is further: the input signal of described two-way I/O port PAD is after synchronous circuit, obtain etv_in signal, as pre-frequency division psc=0, represent that the clock clk1 of counter is without the need to carrying out frequency division, when pre-frequency division psc is other value, the clock of counter carries out psc+1 frequency division and obtains clk2, and clk1 and clk2 obtains clk_cnt clock by a selector switch; As 32 filter width N=0, represent that etv_in signal is without the need to carrying out filtering, it is a clean signal; When 32 filter width N are not equal to 0, represent and open filter function, it may also be useful to clock clk_cnt continuous sampling is to N+1 etv_in; When opening filtering, etv_in obtains etv_in_reg after a register, when etv_in is not equal to etv_in_reg, the count automatic clear of wave filter, or count adds one when each clk_cnt positive rise arrives, until when count equals 32 filter width N, just assert that current etv_in_reg is an effective signal, and count automatic clear; When obtaining an effective etv_in_reg signal, can, according to the configuration of counter, being just positive rise/negative edge, counter adds one/subtracts one.
As the present invention's further scheme: when the enable cen signal of counter is opened, two-way I/O port PAD automatically switches into input state.
Compared with prior art, the invention has the beneficial effects as follows: the shake of waveform during level transitions is carried out filtering by the present invention, thus counter is correctly worked, and filters signal jitter, counter is correctly counted, simplifies procedures, reduce the workload of operation of mcu.
Accompanying drawing explanation
Fig. 1 is can the structural representation of counter of filtering.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only the present invention's part embodiment, instead of whole embodiments. Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.
Refer to Fig. 1, in the embodiment of the present invention, a kind of can the counter of filtering, comprise two-way I/O port PAD, synchronous circuit, filtering circuit and counter, described two-way I/O port PAD connects synchronous circuit, filtering circuit and counter successively.
The input signal of described two-way I/O port PAD is after synchronous circuit, obtain etv_in signal, as pre-frequency division psc=0, represent that the clock clk1 of counter is without the need to carrying out frequency division, when pre-frequency division psc is other value, the clock of counter carries out psc+1 frequency division and obtains clk2, and clk1 and clk2 obtains clk_cnt clock by a selector switch; As 32 filter width N=0, represent that etv_in signal is without the need to carrying out filtering, it is a clean signal; When 32 filter width N are not equal to 0, represent and open filter function, it may also be useful to clock clk_cnt continuous sampling is to N+1 etv_in; When opening filtering, etv_in obtains etv_in_reg after a register, when etv_in is not equal to etv_in_reg, the count automatic clear of wave filter, or count adds one when each clk_cnt positive rise arrives, until when count equals 32 filter width N, just assert that current etv_in_reg is an effective signal, and count automatic clear; When obtaining an effective etv_in_reg signal, can, according to the configuration of counter, being just positive rise/negative edge, counter adds one/subtracts one.
When the enable cen signal of counter is opened, two-way I/O port PAD automatically switches into input state.
The principle of work of the present invention is: refer to Fig. 1, and the basic function of counter of the present invention comprises 32 and upwards adds/downward down counter (cnt), 32 pre-frequency divisions (psc), 32 filter width (N).
Being in of the present invention's innovation adds filter circuit, filters signal jitter, counter is correctly counted, simplifies procedures, and reduces the workload of operation of mcu.
1, PAD is a two-way I/O port, and when the enable cen signal of counter is opened, PAD automatically switches into input state;
2, PAD input signal is after synchronous circuit, it is possible to eliminates metastable state, obtains etv_in signal;
3, as psc=0, representing that the clock clk1 of counter is without the need to carrying out frequency division, during other value, the clock of counter carries out psc+1 frequency division and obtains clk2, and clk1 and clk2 obtains clk_cnt clock by a selector switch;
4, as N=0, represent that etv_in signal is without the need to carrying out filtering, it is a clean signal;
5, when N is not equal to 0, represent and open filter function, it may also be useful to clock clk_cnt continuous sampling is to N+1 etv_in
6, when opening filtering, etv_in obtains etv_in_reg after a register, when etv_in is not equal to etv_in_reg, the count automatic clear of wave filter, or count adds one when each clk_cnt positive rise arrives, until when count equals N, just assert that current etv_in_reg is an effective signal, and count automatic clear; When obtaining an effective etv_in_reg signal, so that it may with the configuration according to counter, being positive rise/negative edge, counter adds one/subtracts one.
To those skilled in the art, it is clear that the invention is not restricted to the details of above-mentioned one exemplary embodiment, and when not deviating from spirit or the essential characteristic of the present invention, it is possible to realize the present invention in other specific forms. Therefore, no matter from which point, embodiment all should be regarded as exemplary, and right and wrong are restrictive, the scope of the present invention is limited by claims instead of above-mentioned explanation, it is intended that all changes in the implication of the equivalent important document dropping on claim and scope included in the present invention. Any Reference numeral in claim should be considered as the claim involved by limiting.
In addition, it is to be understood that, although this specification sheets is described according to enforcement mode, but not each enforcement mode only comprises an independent technical scheme, this kind of narrating mode of specification sheets is only for clarity sake, those skilled in the art should by specification sheets integrally, and the technical scheme in each embodiment through appropriately combined, can also form other enforcement modes that it will be appreciated by those skilled in the art that.
Claims (3)
1. can the counter of filtering, comprise two-way I/O port PAD, synchronous circuit, filtering circuit and counter, it is characterised in that, described two-way I/O port PAD connects synchronous circuit, filtering circuit and counter successively.
2. according to claim 1 can the counter of filtering, it is characterized in that, the input signal of described two-way I/O port PAD is after synchronous circuit, obtain etv_in signal, as pre-frequency division psc=0, represent that the clock clk1 of counter is without the need to carrying out frequency division, when pre-frequency division psc is other value, the clock of counter carries out psc+1 frequency division and obtains clk2, and clk1 and clk2 obtains clk_cnt clock by a selector switch; As 32 filter width N=0, represent that etv_in signal is without the need to carrying out filtering, it is a clean signal; When 32 filter width N are not equal to 0, represent and open filter function, it may also be useful to clock clk_cnt continuous sampling is to N+1 etv_in; When opening filtering, etv_in obtains etv_in_reg after a register, when etv_in is not equal to etv_in_reg, the count automatic clear of wave filter, or count adds one when each clk_cnt positive rise arrives, until when count equals 32 filter width N, just assert that current etv_in_reg is an effective signal, and count automatic clear; When obtaining an effective etv_in_reg signal, can, according to the configuration of counter, being just positive rise/negative edge, counter adds one/subtracts one.
3. according to claim 1 can the counter of filtering, it is characterised in that, when the enable cen signal of counter is opened, two-way I/O port PAD automatically switches into input state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511001553.XA CN105634471B (en) | 2015-12-29 | 2015-12-29 | A kind of counter filtered |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511001553.XA CN105634471B (en) | 2015-12-29 | 2015-12-29 | A kind of counter filtered |
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| CN105634471A true CN105634471A (en) | 2016-06-01 |
| CN105634471B CN105634471B (en) | 2018-07-17 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109947226A (en) * | 2019-04-03 | 2019-06-28 | 深圳芯马科技有限公司 | A kind of UART wake-up circuit of MCU chip |
| CN110471520A (en) * | 2019-07-29 | 2019-11-19 | 广芯微电子（广州）股份有限公司 | A kind of MCU circuit anti-fluttering method based on external reset |
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| EP0449198A3 (en) * | 1990-03-26 | 1993-05-19 | Thomson Consumer Electronics, Inc. | Synchronized horizontal scanning at horizontal frequency multiples |
| CN2922277Y (en) * | 2005-10-25 | 2007-07-11 | 中兴通讯股份有限公司 | Clock burr testing circuit |
| US7598784B2 (en) * | 2005-10-07 | 2009-10-06 | Freescale Semiconductor, Inc. | System and method for controlling signal transitions |
| CN101788941A (en) * | 2010-01-27 | 2010-07-28 | 清华大学 | Data synchronization circuit of redundancy fault-tolerant computer based on programmable device |
| CN101871968A (en) * | 2009-04-24 | 2010-10-27 | 郑州威科姆科技股份有限公司 | Reliable time scale pulse measurement method and measurement device thereof |
| CN103427803A (en) * | 2012-05-22 | 2013-12-04 | 中国航空工业集团公司第六三一研究所 | Bur filtering method based on synchronous circuit |
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2015
- 2015-12-29 CN CN201511001553.XA patent/CN105634471B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0449198A3 (en) * | 1990-03-26 | 1993-05-19 | Thomson Consumer Electronics, Inc. | Synchronized horizontal scanning at horizontal frequency multiples |
| US7598784B2 (en) * | 2005-10-07 | 2009-10-06 | Freescale Semiconductor, Inc. | System and method for controlling signal transitions |
| CN2922277Y (en) * | 2005-10-25 | 2007-07-11 | 中兴通讯股份有限公司 | Clock burr testing circuit |
| CN101871968A (en) * | 2009-04-24 | 2010-10-27 | 郑州威科姆科技股份有限公司 | Reliable time scale pulse measurement method and measurement device thereof |
| CN101788941A (en) * | 2010-01-27 | 2010-07-28 | 清华大学 | Data synchronization circuit of redundancy fault-tolerant computer based on programmable device |
| CN103427803A (en) * | 2012-05-22 | 2013-12-04 | 中国航空工业集团公司第六三一研究所 | Bur filtering method based on synchronous circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109947226A (en) * | 2019-04-03 | 2019-06-28 | 深圳芯马科技有限公司 | A kind of UART wake-up circuit of MCU chip |
| CN110471520A (en) * | 2019-07-29 | 2019-11-19 | 广芯微电子（广州）股份有限公司 | A kind of MCU circuit anti-fluttering method based on external reset |
Also Published As
| Publication number | Publication date |
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| CN105634471B (en) | 2018-07-17 |
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Address after: 518000 Shenzhen Nanshan District, Guangdong Province, Guangdong Province, Yuehai Street High-tech Zone Community Science and Technology South Road 18 Shenzhen Bay Science and Technology Eco-Park 12 Skirt Building 732 Patentee after: Shenzhen Bojuxing Microelectronics Technology Co., Ltd. Address before: 518000 4th Floor, New Material Port D(4) Building, No.2 Changyuan New Material Port, Zhongxin Road, Nanshan District, Shenzhen City, Guangdong Province Patentee before: Shenzhen Bojuxing Industrial Development Co., Ltd. |
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