CN102055469A - Phase discriminator and phase locked loop circuit - Google Patents
Phase discriminator and phase locked loop circuit Download PDFInfo
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- CN102055469A CN102055469A CN2009102220912A CN200910222091A CN102055469A CN 102055469 A CN102055469 A CN 102055469A CN 2009102220912 A CN2009102220912 A CN 2009102220912A CN 200910222091 A CN200910222091 A CN 200910222091A CN 102055469 A CN102055469 A CN 102055469A
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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Abstract
The invention relates to a phase discriminator, which comprises a first clock input circuit, a second clock input circuit and a phase difference pulse output circuit, wherein the first clock input circuit is used for receiving a first clock signal, generating a first comparison signal according to the first clock signal and outputting the first comparison signal; the second clock input circuit is used for receiving a second clock signal, generating a second comparison signal according to the second clock signal and outputting the second comparison signal; and the phase difference pulse output circuit is connected to the output ends of the first and second clock input circuits, and is used for generating a positive phase difference pulse signal according to the first and second comparison signals and outputting the positive phase difference pulse signal. The invention also provides a phase locked loop circuit using the phase discriminator. The phase discriminator and the phase locked loop circuit provided by the invention can reduce the workload of programming a microprocessor and reduce the burden of the microprocessor.
Description
Technical field
The present invention relates to a kind of phase discriminator and phase-locked loop circuit, relate in particular to and realize phase-locked unidirectional clock phase discrimination device and the phase-locked loop circuit of clock in the synchronous communication system.
Background technology
Clock synchronization is very important some in communication network, and special digital synchronization network is set in the communication network of China, and this digital synchronization network is the supporting network of communication network, is used to communication network that synchronizing clock signals is provided.In order to guarantee the communication network operate as normal, utilize digital synchronization network to realize that the clock frequency and the phase place of all nodes in the communication network are consistent usually.The digital synchronization network system grade of China is that the principal and subordinate is synchronous, and low one-level node obtains frequency reference and is synchronized with its node from higher one-level node.Phase-locked loop circuit is exactly the basic circuit that is used to realize clock synchronization, and phase discriminator then is one of basic circuit of phase-locked loop circuit.Phase-locked loop circuit also will have loop filter, voltage controlled oscillator etc. except comprising phase discriminator, the effect of loop filter is that phase data is carried out filtering and processing, is used to regulate the output frequency of voltage controlled oscillator.Phase discriminator can be divided into simulation phase discriminator and digital phase discriminator, and the simulation phase discriminator is meant that the signal that participates in phase demodulation is an analog signal.Digital phase discriminator is meant that the signal that participates in phase demodulation is a digital signal.Digital phase discriminator normally compares the phase place of two reference signals and measured signal, thereby obtains the phase difference of the two.In clock synchronous network, reference signal is the clock reference signal of even higher level of node, measured signal obtains behind frequency division for the local clock signal of using, phase discriminator then be the phase difference that is used for reference signal detection and measured signal so that obtain the phase change rule and the frequency departure of measured clock signal.Thereby the identified result of phase discriminator generally is divided into two kinds: when the measured signal phase place lagged behind reference signal always, identified result was a forward; When the measured signal phase place was ahead of reference signal always, identified result was a negative sense.Yet phase discriminator is when carrying out phase demodulation to clock signal, because the frequency of measured signal always slowly changes, especially in the loose coupling phase-locked loop, the phase place of a certain moment measured signal may be ahead of reference signal, a certain moment measured signal then can lag behind reference signal, thus the identified result that obtains have just also have negative.Because the identified result of phase discriminator need be exported to loop filter and handle, and loop filter is realized by microprocessor, the existing burden that has negative identified result can increase processor just again.
Summary of the invention
The object of the present invention is to provide a kind of phase discriminator and phase-locked loop circuit, the phase difference pulse signal that makes output is always for just, the loop filter that the positive phase difference pulse signal that it is exported is fit to be realized by microprocessor is handled, and can alleviate workload that microprocessor is programmed and the burden that alleviates microprocessor.
The invention provides a kind of phase discriminator, comprise first clock input circuit, be used to receive first clock signal, and produce first comparison signal and output according to first clock signal; The second clock input circuit is used to receive the second clock signal, and produces second comparison signal and output according to the second clock signal; The phase difference impulse output circuit is connected in the output of described first clock input circuit and second clock input circuit, is used for producing positive phase difference pulse signal and output according to first comparison signal and second comparison signal.
Preferably, above-mentioned phase discriminator also comprises counter, be connected in the output of described phase difference impulse output circuit, be used for the count pick up clock signal, and described positive phase difference pulse signal is counted the digitized phase signal of back output according to described counting clock signal.
Preferably, above-mentioned first clock input circuit comprises that first inverter is used to receive first clock signal, and carries out anti-phase to first clock signal.
Preferably, above-mentioned first clock input circuit also comprises first trigger, is connected in the output of described first inverter, is used to receive first clock signal through after anti-phase.
Preferably, above-mentioned first trigger also is used to receive first data-signal, through first clock signal after anti-phase with start phase discrimination signal, and according to described first data-signal, through first clock signal after anti-phase with start phase discrimination signal and produce first comparison signal and second data-signal.
Preferably, above-mentioned second clock input circuit comprises that second inverter is used to receive the second clock signal, and carries out anti-phase to the second clock signal.
Preferably, above-mentioned second clock input circuit also comprises second trigger, is connected in the output of described second inverter, is used to receive the second clock signal through after anti-phase.
Preferably, above-mentioned second trigger is connected in the data output end of described first trigger, be used to receive second data-signal, second trigger also is used to receive through the second clock signal after anti-phase and starts phase discrimination signal, and according to described second data-signal, through the second clock signal after anti-phase with start phase discrimination signal and produce second comparison signal.
Preferably, above-mentioned phase difference impulse output circuit is an XOR gate, and when first comparison signal and second comparison signal were low level or high level, the signal that the phase difference impulse output circuit is exported was a low level.
Preferably, when one of them of first comparison signal and second comparison signal is output as low level, another output be high level the time, the signal that the phase difference impulse output circuit is exported is a high level.
The present invention also provides a kind of phase-locked loop circuit, comprises above-mentioned phase discriminator.
Phase discriminator among the present invention and phase-locked loop circuit, the relation that does not need the phase place lead and lag of definite first clock input circuit and second clock input circuit, the phase difference value that just can make phase discriminator output is always for just, the positive phase difference pulse signal that it is exported is given the loop filter of being realized by microprocessor, relatively be fit to microprocessor processes, can alleviate workload that microprocessor is programmed and the burden that alleviates microprocessor.
Description of drawings
Figure 1 shows that the structural representation of a kind of phase discriminator embodiment of the present invention;
Figure 2 shows that the concrete structure schematic diagram of phase discriminator shown in Figure 1;
Figure 3 shows that the schematic diagram of phase discriminator identified result;
Figure 4 shows that the structural representation of a kind of phase-locked loop circuit embodiment of the present invention.
The realization of the object of the invention, functional characteristics and advantage, will be in conjunction with the embodiments, be described further with reference to accompanying drawing.
Embodiment
Below in conjunction with the drawings and specific embodiments technical scheme of the present invention is described in further detail, can be implemented so that those skilled in the art can better understand the present invention also, but illustrated embodiment is not as a limitation of the invention.
Figure 1 shows that the structural representation of a kind of phase discriminator 100 embodiment of the present invention.
When phase discriminator 100 is used in present embodiment, also can counter 40 be set at phase discriminator 100, be connected in the output of described phase difference impulse output circuit 30, be used for the count pick up clock signal, and described positive phase difference pulse signal counted the digitized phase signal of back output according to described counting clock signal.
In the present embodiment, phase discriminator 100 is unidirectional digital phase discriminator, the relation that does not need the phase place lead and lag of definite first clock input circuit 10 and second clock input circuit 20, the phase difference pulse signal that just can make phase discriminator 100 output is always for just, the loop filter that the positive phase difference pulse signal that it is exported is fit to be realized by microprocessor is handled, and can alleviate workload that microprocessor is programmed and the burden that alleviates microprocessor.
Figure 2 shows that the concrete structure schematic diagram of phase discriminator shown in Figure 1 100.
In the present embodiment, first clock is a reference clock, and frequency is 8KHZ.First trigger 102 is a d type flip flop.Link the input end of clock of first trigger 102 behind the not circuit that first clock is constituted through first inverter 101, can guarantee that first trigger 102 triggers at the trailing edge of first clock, the signal of the data input pin of first trigger 102 input simultaneously remains high level, first trigger 102 is received the startup phase discrimination signal by removing termination, when the startup phase discrimination signal is low level, first trigger 102 is not worked, when the startup phase discrimination signal became high level by low level, first trigger 102 was started working.
In the present embodiment, second clock is a measured clock, and its frequency can be set to the frequency identical or approaching with the frequency of first clock.Second trigger 202 is a d type flip flop.Link the input end of clock of second trigger 202 behind the not circuit that second clock is constituted through second inverter 201, can guarantee that second trigger 202 triggers at the trailing edge of second clock, the signal of the signal of the data input pin of second trigger 202 input simultaneously and first input end input also is to remain high level, second trigger 202 is received the startup phase discrimination signal by removing termination, when the startup phase discrimination signal is low level, second trigger 202 is not worked, when the startup phase discrimination signal became high level by low level, second trigger 202 was started working.
Phase difference impulse output circuit 30 is an XOR gate 301, when first comparison signal and second comparison signal are low level or high level, the signal that phase difference impulse output circuit 30 is exported is a low level, when one of them of first comparison signal and second comparison signal is output as low level, another output be high level the time, the signal that phase difference impulse output circuit 30 is exported is a high level.
The data input pin of counter 40 connects the output of XOR gate 301, the input end of clock count pick up clock signal of counter 40.In the present embodiment, the figure place of counter 40 is 12, when the frequency of first comparison signal and second comparison signal is 8KHZ, when the counting clock frequency is 16MHZ, the maximum of the phase demodulation data that phase demodulation is exported is 16MHZ/8KHZ=2048, and the maximum count value of corresponding counter 40 is 2
12=2048, so the precision of phase discriminator 100 is 1/2048.The precision of the phase discriminator 100 in the present embodiment is 1/2048 can satisfy the requirement of China's clock synchronous network.Certainly, in order to improve the precision of phase discriminator 100, can improve the figure place of the counting clock frequency sum counter 40 of counter 40.
Figure 3 shows that the schematic diagram of phase discriminator 100 identified result.
In Fig. 3, CLK1 is a reference clock, and CLK2 is a measured clock, START is for starting phase discrimination signal, A is the signal of the output output of first trigger 102, and B is the signal of the output output of second trigger 202, and C is the signal of the output output of XOR gate 301.As can be seen from Figure 3, because the frequency of CLK2 (measured clock) and the frequency of CLK1 (reference clock) are very approaching, second trigger 202 and first trigger 102 all are to start phase demodulation when starting phase discrimination signal for high level, and all be to trigger at trailing edge, and the data input pin of second trigger 202 is the data output end of first trigger 102, second comparison signal that first comparison signal that first trigger 102 is exported and second trigger 202 are exported is through XOR gate 301, the output result that can guarantee phase discriminator 100 just is always, thereby makes phase difference value that counter 40 sampling obtains also for just.Thereby after the phase demodulation order started, the identified result of phase discriminator 100 was for to begin to the positive pulse (dotted portion of C oscillogram) the CLK2 trailing edge (dotted portion of B oscillogram) from CLK1 trailing edge (dotted portion of A oscillogram).
Figure 4 shows that the structural representation of a kind of phase-locked loop circuit embodiment of the present invention.
Phase-locked loop circuit in the present embodiment uses Fig. 1 or phase discriminator 100 shown in Figure 2 to carry out phase demodulation, and phase-locked loop circuit comprises phase discriminator 100, loop filter 200 and voltage controlled oscillator 300, and the common signal that constitutes of three differs automatic adjusting feedback control loop.The input of loop filter 200 is connected with the output of phase discriminator 100, and the input of voltage controlled oscillator 300 then is connected with the output of loop filter 200.Phase-locked loop circuit in the present embodiment is except the circuit structure of phase discriminator 100 and existing phase discriminator 100 are different, the circuit structure of loop filter 200 and voltage controlled oscillator 300 and function are all identical with voltage controlled oscillator 300 with existing loop filter 200, therefore do not repeat them here.
Phase-locked loop circuit in the present embodiment is owing to used unidirectional phase discriminator 100, the relation that does not need the phase place lead and lag of definite first clock input circuit 10 and second clock input circuit 20, the phase difference pulse signal that just can make phase discriminator 100 output is always for just, the loop filter 200 that the positive phase difference pulse signal that it is exported is fit to be realized by microprocessor is handled, and can alleviate workload that microprocessor is programmed and the burden that alleviates microprocessor.
The above only is the preferred embodiments of the present invention; be not so limit claim of the present invention; every equivalent structure or equivalent flow process conversion that utilizes specification of the present invention and accompanying drawing content to be done; or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present invention.
Claims (11)
1. a phase discriminator is characterized in that, comprising:
First clock input circuit is used to receive first clock signal, and produces first comparison signal and output according to first clock signal;
The second clock input circuit is used to receive the second clock signal, and produces second comparison signal and output according to the second clock signal;
The phase difference impulse output circuit is connected in the output of described first clock input circuit and second clock input circuit, is used for producing positive phase difference pulse signal and output according to first comparison signal and second comparison signal.
2. phase discriminator as claimed in claim 1, it is characterized in that, described phase discriminator also comprises counter, described counter is connected in the output of described phase difference impulse output circuit, be used for the count pick up clock signal, and described positive phase difference pulse signal counted the digitized phase signal of back output according to described counting clock signal.
3. phase discriminator as claimed in claim 1 is characterized in that, described first clock input circuit comprises first inverter, and described first inverter is used to receive first clock signal, and carries out anti-phase to first clock signal.
4. phase discriminator as claimed in claim 3 is characterized in that, described first clock input circuit also comprises first trigger, and described first trigger is connected in the output of described first inverter, is used to receive first clock signal through after anti-phase.
5. phase discriminator as claimed in claim 4, it is characterized in that, described first trigger also is used to receive first data-signal, through first clock signal after anti-phase with start phase discrimination signal, and according to described first data-signal, through first clock signal after anti-phase with start phase discrimination signal and produce first comparison signal and second data-signal.
6. phase discriminator as claimed in claim 1 is characterized in that, described second clock input circuit comprises second inverter, and described second inverter is used to receive the second clock signal, and carries out anti-phase to the second clock signal.
7. phase discriminator as claimed in claim 6 is characterized in that, described second clock input circuit also comprises second trigger, and described second trigger is connected in the output of described second inverter, is used to receive the second clock signal through after anti-phase.
8. phase discriminator as claimed in claim 7, it is characterized in that, described second trigger is connected in the data output end of described first trigger, be used to receive second data-signal, described second trigger also is used to receive through the second clock signal after anti-phase and starts phase discrimination signal, and according to described second data-signal, through the second clock signal after anti-phase with start phase discrimination signal and produce second comparison signal.
9. phase discriminator as claimed in claim 8 is characterized in that, described phase difference impulse output circuit is an XOR gate, and when first comparison signal and second comparison signal were low level or high level, the signal that the phase difference impulse output circuit is exported was a low level.
10. phase discriminator as claimed in claim 9 is characterized in that, when one of them of first comparison signal and second comparison signal is output as low level, another output be high level the time, the signal that the phase difference impulse output circuit is exported is a high level.
11. a phase-locked loop circuit is characterized in that, comprises as each described phase discriminator of claim 1 to 10.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200910222091.2A CN102055469B (en) | 2009-11-05 | 2009-11-05 | Phase discriminator and phase locked loop circuit |
| PCT/CN2010/077496 WO2011054242A1 (en) | 2009-11-05 | 2010-09-29 | Phase discriminator and phase-locked loop circuit |
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| CN200910222091.2A CN102055469B (en) | 2009-11-05 | 2009-11-05 | Phase discriminator and phase locked loop circuit |
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| CN102055469A true CN102055469A (en) | 2011-05-11 |
| CN102055469B CN102055469B (en) | 2014-04-30 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102426294A (en) * | 2011-08-05 | 2012-04-25 | 北京星网锐捷网络技术有限公司 | Clock phase difference measurement method and device |
| CN106093572A (en) * | 2016-06-23 | 2016-11-09 | 西安电子科技大学 | High-precision phase position testing circuit based on integrated phase discriminator AD8302 and method for self-calibrating thereof |
| CN109039471A (en) * | 2018-09-13 | 2018-12-18 | 上海微小卫星工程中心 | A kind of numerical model analysis demodulation method applied to high-rate laser communication |
| CN109217951A (en) * | 2018-09-07 | 2019-01-15 | 深圳市紫光同创电子有限公司 | A kind of transmission delay test method and device based on FPGA |
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| CN101471656A (en) * | 2007-12-28 | 2009-07-01 | 联发科技股份有限公司 | Clock generation devices and methods |
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| CN100558156C (en) * | 2006-06-08 | 2009-11-04 | 复旦大学 | Be applicable to the clock generation circuit in low dithering of digital TV in high resolution |
| CN101383613B (en) * | 2007-09-04 | 2011-03-30 | 锐迪科科技有限公司 | PLL circuit and oscillation signal phase control method |
| CN101572527A (en) * | 2009-06-09 | 2009-11-04 | 中国人民解放军国防科学技术大学 | High-speed high-jitter-tolerance random-data linear phase detector circuit |
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| CN1112753A (en) * | 1994-04-07 | 1995-11-29 | Rca汤姆森许可公司 | Phase detector for a phase-lock-loop |
| CN1983815A (en) * | 2005-12-13 | 2007-06-20 | 上海华虹Nec电子有限公司 | Time-delay locking loop |
| CN101459426A (en) * | 2007-12-11 | 2009-06-17 | 海力士半导体有限公司 | Dll clock signal generating circuit capable of correcting a distorted duty ratio |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102426294A (en) * | 2011-08-05 | 2012-04-25 | 北京星网锐捷网络技术有限公司 | Clock phase difference measurement method and device |
| CN102426294B (en) * | 2011-08-05 | 2014-06-04 | 北京星网锐捷网络技术有限公司 | Clock phase difference measurement method and device |
| CN106093572A (en) * | 2016-06-23 | 2016-11-09 | 西安电子科技大学 | High-precision phase position testing circuit based on integrated phase discriminator AD8302 and method for self-calibrating thereof |
| CN106093572B (en) * | 2016-06-23 | 2018-12-28 | 西安电子科技大学 | High-precision phase position detection circuit and its method for self-calibrating based on integrated phase discriminator AD8302 |
| CN109217951A (en) * | 2018-09-07 | 2019-01-15 | 深圳市紫光同创电子有限公司 | A kind of transmission delay test method and device based on FPGA |
| CN109217951B (en) * | 2018-09-07 | 2020-12-15 | 深圳市紫光同创电子有限公司 | Transmission delay testing method and device based on FPGA |
| CN109039471A (en) * | 2018-09-13 | 2018-12-18 | 上海微小卫星工程中心 | A kind of numerical model analysis demodulation method applied to high-rate laser communication |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102055469B (en) | 2014-04-30 |
| WO2011054242A1 (en) | 2011-05-12 |
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